Simple counter in VHDL

counter.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Counter is
    port (
        clk: in std_logic;
        rst: in std_logic;
        count: out std_logic_vector(3 downto 0)
    );
end;

architecture Behavioral of Counter is
    signal value: unsigned(3 downto 0);
begin

    process (clk)
    begin
        if (rising_edge(clk)) then
            if (rst = '1') then
                value <= x"0";
            else
                value <= value + x"1";
            end if;
        end if;
    end process;

    count <= std_logic_vector(value);
end;