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pipeline for Amaranth
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with FSM(): | |
with m.State("Begin"): | |
with m.If(self.strobe): | |
m.next = "Process" | |
with m.State("Process"): | |
# Automatically create pipe.mult, pipe.shift | |
with m.Pipeline([self.mult, self.shift]) as pipe: | |
with pipe.Stage(): | |
# manually set up pipe.xor | |
# XXX: Do we want pipe.foo or just foo in mPipeline() scope? | |
pipe.xor = signed(24) | |
pipe.ans = signed(24) | |
m.d.sync += [ | |
pipe.xor.eq(self.xor) | |
pipe.ans.eq(self.a + self.b) | |
] | |
with pipe.Stage(3): | |
# All pipe.* registers from prior stage are moved forward | |
# into a new set of registers for this stage | |
# 3 cycle delay, i.e. this stage takes 4 cycles, because the | |
# multiplier is slow. | |
m.d.sync += pipe.ans.eq(pipe.ans * pipe.mult) | |
with pipe.Stage(): | |
# This pipe.xor and pipe.shift contain the values from | |
# stage 1 2 clock ticks ago | |
m.d.sync += pipe.ans.eq((pipe.ans ^ pipe.xor) << pipe.shift) | |
with pipe.Stage(): | |
# Add a 1 cycle delay | |
pass | |
with m.If(!self.strobe): | |
m.next = "Start" | |
# Connect the output registers from the pipeline to this component's outputs. | |
# This is the same timing as the final pipeline stage containing | |
# the below but with m.d.sync | |
m.d.comb += [ | |
self.output_ready.eq(pipe.ready), | |
self.output_ans.eq(pipe.ans) | |
] |
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