snickerdoodle.cfg

# from interface/ftdi/digilent-hs1.cfg

adapter driver ftdi
#ftdi device_desc "Digilent Adept USB Device"
ftdi vid_pid 0x0403 0x6010

# james note: just changing this for the tigard board
ftdi channel 1 

# just TCK TDI TDO TMS, no reset
ftdi layout_init 0x0088 0x008b
reset_config none

transport select jtag

# from targets/zynq7000.cfg
set _CHIPNAME zynq
set _TARGETNAME $_CHIPNAME.cpu

# FROM OTHER zynq script from rtems.org
set _SMP 0

jtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \
    -expected-id 0x03723093 \
    -expected-id 0x03722093 \
    -expected-id 0x0373c093 \
    -expected-id 0x03728093 \
    -expected-id 0x0373B093 \
    -expected-id 0x03732093 \
    -expected-id 0x03727093 \
    -expected-id 0x0372C093 \
    -expected-id 0x03731093 \
    -expected-id 0x03736093

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477

dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80090000

adapter speed 1000

${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
if { $_SMP } {
    target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x80092000
    target smp ${_TARGETNAME}0 ${_TARGETNAME}1
    ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
}

pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
virtex2 set_user_codes zynq_pl.pld 0x02 0x03 0x22 0x23

# for loading bitstream: 
#> pld load zynq_pl.pld /home/jrsa/sandbox/build/krtkl_snickerdoodle/gateware/krtkl_snickerdoodle.bit
#loaded file /home/jrsa/sandbox/build/krtkl_snickerdoodle/gateware/krtkl_snickerdoodle.bit to pld device zynq_pl.pld in 4s 283485us

# from openocd log
# Debug: 697 155431 xilinx_bit.c:116 xilinx_read_bit_file(): bit_file: krtkl_snickerdoodle;UserID=0XFFFFFFFF;COMPRESS=TRUE;Version=2019.1 7z020clg400 2024/10/20,11:33:55 534880

# everything below here is helper functions for controlling the ARM cores
#
# Hack to get the registers into a stable state when first booting a zynq in
# JTAG mode. If r11 is pointing to an invalid address and you use gdb to set a
# register the write will fail because gdb attempts to scan or unwind the
# current frame and the bad address seems to lock the bus up. This code puts
# the registers into the OCM and hopefull safe.
#
proc zynq_clear_registers { target } {
    echo "Zynq-7000 Series setup: $target"
    set _OCM_END 0x0003FFF0
    mww phys 0xF8007000 0x4E00E07F
    reg r0 0
    reg r1 0
    reg r2 0
    reg r3 0
    reg r4 0
    reg r5 0
    reg r6 0
    reg r7 0
    reg r8 0
    reg r9 0
    reg r10 0
    reg r11 $_OCM_END
    reg sp_svc $_OCM_END
    reg lr_svc $_OCM_END
    reg sp_abt $_OCM_END
    reg lr_abt $_OCM_END
    reg sp_und $_OCM_END
    reg lr_und $_OCM_END
}

proc zynq_disable_mmu_and_caches { target } {
    # arm mcr pX op1 CRn CRm op2 value
    echo "Disable MMU and caches"
    # Invalidate caches
    catch {
        $target arm mcr 15 0 7 5 0 0
        $target arm mcr 15 0 7 7 0 0
        # Invalidate all TLBs
        $target arm mcr 15 0 8 5 0 0
        $target arm mcr 15 0 8 6 0 0
        $target arm mcr 15 0 8 7 0 0
        $target arm mcr 15 4 8 3 0 0
        $target arm mcr 15 4 8 7 0 0
        set cp [$target arm mrc 15 0 1 0 0]
        echo "SCTRL => [format 0x%x $cp]"
        set mask [expr 1 << 29 | 1 << 12 | 1 << 11 | 1 << 2 | 1 << 1 | 1 << 0]
        set cp [expr ($cp & ~$mask)]
        $target arm mcr 15 0 1 0 0 $cp
        echo "SCTRL <= [format 0x%x $cp]"
    }
}

proc zynq_boot_ocm_setup { } {
    #
    # Enable the OCM
    #
    echo "Zynq Boot OCM setup"
    catch {
      mww phys 0xF8000008 0xDF0D
      mww phys 0xF8000238 0
      mww phys 0xF8000910 0xC
    }
}

proc zynq_rtems_setup { } {
    cache_config l2x 0xF8F02000 8
    cortex_a maskisr on
}

proc zynq_restart { wait } {
    global _SMP
    global _TARGETNAME
    set target0 ${_TARGETNAME}0
    set target1 ${_TARGETNAME}1
    echo "Zynq reset, resetting the board ... "
    poll off
    #
    # Issue the reset via the SLCR
    #
    catch {
        mww phys 0xF8000008 0xDF0D
        mww phys 0xF8000200 1
    }
    echo "Zynq reset waiting for $wait msecs ... "
    sleep $wait
    #
    # Reconnect the DAP etc due to the reset.
    #
    $target0 cortex_a dbginit
    $target0 arm core_state arm
    if { $_SMP } {
        $target1 arm core_state arm
        $target1 cortex_a dbginit
        cortex_a smp off
    }
    poll on
    #
    # We can now halt the core.
    #
    if { $_SMP } {
        targets $target1
        halt
    }
    targets $target0
    halt
    #zynq_rtems_setup
}

proc zynq_gdb_attach { target } {
    catch {
      halt
    }
}

#--------------------------------------------------------------------------------

init
sleep 1000
halt
#pld load zynq_pl.pld /home/jrsa/sandbox/build/krtkl_snickerdoodle/gateware/krtkl_snickerdoodle.bit
#sleep 1000
#zynq_restart 20
#sleep 100
#zynq_restart 20
#
#zynq_clear_registers ${_TARGETNAME}0
##zynq_clear_registers ${_TARGETNAME}1
#zynq_disable_mmu_and_caches ${_TARGETNAME}0
##zynq_disable_mmu_and_caches ${_TARGETNAME}1
#

# loading bitstream here still not working
# j/k its working now 
pld load zynq_pl.pld /home/jrsa/sandbox/build/krtkl_snickerdoodle/gateware/krtkl_snickerdoodle.bit
#pld load zynq_pl.pld /home/jrsa/src/kintex-demo-projects/blinky-snickerdoodle/blinky.bit

load_image "/home/jrsa/snick/snickerdoodle-examples/snickerdoodle-black/snickerdoodle-black-vitis-hello-world/sdk3/hello3/zynq_fsbl/fsbl.elf" 0x00000000 elf
#
resume 0

sleep 1000

halt
load_image "/home/jrsa/sandbox/build/krtkl_snickerdoodle/software/bios/bios.elf" 0x00000000 elf

# NOTE: this does load the bitstream but several other things have to be done to clock the fabric 
# and enable AXI communication back and forth with the arm cores. i am looking at the FSBL and the
# fpga manager driver in linux to see what those steps are.

# per linux driver (which also refers to UG585 p. 211)

# the bitstream loading itself is done via JTAG obviously
#     * assert axi interface resets
#     * disable all level shifters
#     * enable ps->pl level shifters
#     * other stuff ;)
#     * load bitstream
#pld load zynq_pl.pld /home/jrsa/sandbox/build/krtkl_snickerdoodle/gateware/krtkl_snickerdoodle.bit
#     * enable PL->PS level shifters (other direction is already enabled above)
#     * de-assert axi interface resets
# 
resume 0