I hereby claim:
- I am justtryingthingsout on github.
- I am plzdonthaxme (https://keybase.io/plzdonthaxme) on keybase.
- I have a public key ASAW4lFJbkGpEA_Pi2p_zkUhtJzqwiwNuTYFaooXpkfXGwo
To claim this, I am signing this object:
S3_3_c4_c5_0 at min EL0: DSPSR | |
S3_3_c4_c5_1 at min EL0: DLR | |
S3_6_c4_c0_0 at min EL3: SPSR_EL3 | |
S3_6_c4_c0_1 at min EL3: ELR_EL3 | |
S3_1_c0_c0_0 at min EL1: CCSIDR_EL1 | |
S3_6_c1_c0_0 at min EL3: SCTLR_EL3 | |
S3_6_c1_c0_1 at min EL3: ACTLR_EL3 | |
S3_6_c1_c1_2 at min EL3: CPTR_EL3 | |
S3_6_c1_c1_0 at min EL3: SCR_EL3 | |
S3_6_c1_c3_1 at min EL3: MDCR_EL3 |
S3_3_c4_c5_0 at min EL0: DSPSR | |
S3_3_c4_c5_1 at min EL0: DLR | |
S3_6_c4_c0_0 at min EL3: SPSR_EL3 | |
S3_6_c4_c0_1 at min EL3: ELR_EL3 | |
S3_1_c0_c0_0 at min EL1: CCSIDR_EL1 | |
S3_6_c1_c0_0 at min EL3: SCTLR_EL3 | |
S3_6_c1_c0_1 at min EL3: ACTLR_EL3 | |
S3_6_c1_c1_2 at min EL3: CPTR_EL3 | |
S3_6_c1_c1_0 at min EL3: SCR_EL3 | |
S3_6_c1_c3_1 at min EL3: MDCR_EL3 |
b[31]: dbghalt | |
External halt request, equivalent to the halt from CTI. | |
Auto-cleared after ACC Core is halted. | |
b[30]: dbgrestart | |
External restart request, equivalent to the restart from CTI. | |
Auto-cleared after ACC Core is restarted. | |
b[29]: dbghaltonrst | |
Halt the ACC Core from the following boot, either cold or warm. |
0x206140008: | |
rsvd_63 | |
cfgerren Enable error register locking and asynch reporting when CfgErrESV is set | |
chksnphit Deprecated | |
chkdatecc If set check data ECC, enable single bit error correction, log status. If clear | |
do not check data ECC, don't correct errors, don't log status. | |
injdatratedbe Rate at which double random ECC errors are injected. The rate is approximately | |
(2^(2*InjDatRateDbe)) accesses |
0x206140108: | |
b[63]: ready RAM available for use | |
b[62:30]: rsvd_62_30 | |
b[29:24]: regionbase Base region within LLC (starting way). Base address does not change. | |
(EnableSize+RegionBase) must be less than or equal to (RegionNum+1) and EnableSize must be less than or equal to RegionNum. | |
b[23:22]: rsvd_23_22 | |
b[21:16]: regionnum Number of supported regions | |
b[15:14]: rsvd_15_14 | |
b[13:8]: regionsize Size of each region 2^N (000000:No L2 - feature not supported; ... ; 001110:16KB; 001111: 32KB; 010000:64KB; ...) | |
b[7:6]: rsvd_7_6 |
ascwrap_rev: 0x0 | |
ascwrap_ctr: 0x4 | |
ascwrap_idle_ctrl: 0x40 | |
ascwrap_cpu_ctrl: 0x44 | |
ascwrap_idle_status: 0x48 | |
ascwrap_status: 0x4C | |
ascwrap_kic_cap0: 0x800 | |
ascwrap_kic_glb_reset: 0x808 | |
ascwrap_kic_glb_cfg: 0x80C | |
ascwrap_kic_iack0: 0x818 |
S0_0_c4_c0_3 at min EL1: UAOIMM | |
S0_0_c4_c0_4 at min EL1: PANIMM | |
S0_0_c4_c0_5 at min EL1: SPSELIMM | |
S0_3_c4_c0_1 at min EL1: SSBSIMM | |
S0_3_c4_c0_2 at min EL1: DITIMM | |
S0_3_c4_c0_6 at min EL1: DAIFSET | |
S0_3_c4_c0_7 at min EL1: DAIFCLR | |
S1_0_c7_c10_2 at min EL1: DCCSW | |
S1_0_c7_c14_2 at min EL1: DCCISW | |
S1_0_c7_c1_0 at min EL1: ICIALLUIS |
S0_0_c4_c0_3 at min EL1: UAOIMM | |
S0_0_c4_c0_4 at min EL1: PANIMM | |
S0_0_c4_c0_5 at min EL1: SPSELIMM | |
S0_3_c4_c0_1 at min EL1: SSBSIMM | |
S0_3_c4_c0_2 at min EL1: DITIMM | |
S0_3_c4_c0_6 at min EL1: DAIFSET | |
S0_3_c4_c0_7 at min EL1: DAIFCLR | |
S1_0_c7_c10_2 at min EL1: DCCSW | |
S1_0_c7_c14_2 at min EL1: DCCISW | |
S1_0_c7_c1_0 at min EL1: ICIALLUIS |
I hereby claim:
To claim this, I am signing this object: