x86info -c on AMD EPYC 7281

x86info.txt

$ ./x86info -c
x86info v1.31pre
Found 32 identical CPUs
Extended Family: 8 Extended Model: 0 Family: 15 Model: 1 Stepping: 2
CPU Model (x86info's best guess): Unknown CPU 0x800f12
Processor name string (BIOS programmed): AMD EPYC 7281 16-Core Processor                

Monitor/Mwait: min/max line size 64/64, ecx bit 0 support, enumeration extension
SVM: revision 1, 32768 ASIDs, np, lbrVirt, SVMLock, NRIPSave, TscRateMsr, VmcbClean, FlushByAsid, DecodeAssists, PauseFilter, PauseFilterThreshold
Address Size: 48 bits virtual, 48 bits physical
The physical package has 16 of 64 possible cores implemented.
L1 Data TLB (1G):           Fully associative. 64 entries.
L1 Instruction TLB (1G):    Fully associative. 64 entries.
L1 Data TLB (2M/4M):        Fully associative. 64 entries.
L1 Instruction TLB (2M/4M): Fully associative. 64 entries.
L1 Data TLB (4K):           Fully associative. 64 entries.
L1 Instruction TLB (4K):    Fully associative. 64 entries.
L1 Data cache:
	Size: 32Kb	8-way associative. 
	lines per tag=1	line size=64 bytes.
L1 Instruction cache:
	Size: 64Kb	4-way associative. 
	lines per tag=1	line size=64 bytes.
L2 Data TLB (1G):           Disabled. 0 entries.
L2 Instruction TLB (1G):    Disabled. 0 entries.
L2 Data TLB (2M/4M):        1536 entries.
L2 Instruction TLB (2M/4M): 8-way associative. 1024 entries.
L2 Data TLB (4K):           1536 entries.
L2 Instruction TLB (4K):    8-way associative. 1024 entries.
L2 cache:
	Size: 512Kb	8-way associative. 
	lines per tag=1	line size=64 bytes.

 running at an estimated 2.10GHz