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FROM gusanagy/xilinx-vivado:2024.1-x11 | |
USER root | |
RUN <<EOF | |
apt-get update && apt-get install -y --no-install-recommends locales gcc g++ make build-essential && dpkg-reconfigure locales | |
apt-get autoclean && apt-get autoremove && apt-get -s clean | |
locale-gen en_US.UTF-8 && update-locale LANG=en_US.UTF-8 | |
EOF |
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// I cut and paste this from a bigger project, so there could be missing imports/etc | |
import chisel3._ | |
import chisel3.util._ | |
import chisel3.experimental.{DataMirror, Direction} | |
import chiseltest._ | |
import chiseltest.testableData | |
import scala.util.Random | |
import scala.language.implicitConversions | |
trait Stalls { |
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import chisel3.util.log2Ceil | |
import chisel3.experimental.EnumAnnotations.{EnumComponentAnnotation, EnumVecAnnotation, EnumDefAnnotation} | |
import firrtl.{CircuitState, DependencyAPIMigration, Transform} | |
import firrtl.options.TargetDirAnnotation | |
import firrtl.stage.{Forms, RunFirrtlTransformAnnotation} | |
import firrtl.analyses.InstanceKeyGraph | |
import firrtl.ir.{GroundType, SIntType, IntWidth, Port} | |
import chiseltest.internal.{VerilatorBackendAnnotation, WriteVcdAnnotation} | |
import logger.LazyLogging |
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module NttRam : | |
input clock : Clock | |
input reset : Reset | |
output io : {port : {flip req : {valid : UInt<1>, bits : {addr : UInt<8>, write : {valid : UInt<1>, bits : SInt<13>[4]}}}, resp : {valid : UInt<1>, bits : SInt<13>[4]}}[2]} | |
node _T = asUInt(io.port[0].resp.bits[0]) @[Ram.scala 54:62] | |
node _T_1 = asUInt(io.port[0].resp.bits[1]) @[Ram.scala 54:62] | |
node _T_2 = asUInt(io.port[0].resp.bits[2]) @[Ram.scala 54:62] | |
node _T_3 = asUInt(io.port[0].resp.bits[3]) @[Ram.scala 54:62] | |
node _T_4 = cat(_T_1, _T) @[Ram.scala 54:62] |
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import chisel3._ | |
import chisel3.util._ | |
import chisel3.ExplicitCompileOptions.Strict | |
import chisel3.internal.naming.chiselName | |
@chiselName | |
class Ram[T <: Data](size: Int, elType: T, numPorts: Int = 2) extends Module { | |
val io = IO(new Bundle { | |
val port = Vec(numPorts, new Bundle { | |
val req = Flipped(Valid(new Bundle { |
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import gmpy2 | |
from gmpy2 import powmod | |
import random | |
def sr(n): | |
s = 0 | |
n = n - 1 | |
while n%2 == 0: | |
n = n // 2 | |
s += 1 |
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import re | |
import gmpy2 | |
from gmpy2 import mpz, divm, powmod, gcd, gcdext, invert | |
import itertools | |
import operator | |
from itertools import combinations, permutations, groupby | |
## solve system of equation: | |
# a * l1 + b = l1_p mod 26 | |
# a * l2 + b = l2_p mod 26 |
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import jnr.ffi._ | |
import jnr.ffi.annotations.{Out, Transient} | |
import jnr.ffi.types.pid_t | |
import scala.util.Random | |
object SimpleFfi { | |
val libc = LibraryLoader.create(classOf[SimpleFfi.LibC]).load("c") |
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import jnr.ffi._ | |
import jnr.ffi.annotations.{Out, Transient} | |
import jnr.ffi.types.pid_t | |
import scala.util.Random | |
object SimpleFfi { | |
val libc = LibraryLoader.create(classOf[SimpleFfi.LibC]).load("c") |