cxxrtl: Segfault when assigning an array element indexed with a wire

callstack.txt

Program terminated with signal SIGSEGV, Segmentation fault.
#0  0x0000561db819718a in std::vector<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t, std::allocator<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t> >::size (this=<optimized out>)
    at /usr/include/c++/10.2.0/bits/stl_vector.h:919
919	      { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }
(gdb) bt
#0  0x0000561db819718a in std::vector<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t, std::allocator<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t> >::size (this=<optimized out>)
    at /usr/include/c++/10.2.0/bits/stl_vector.h:919
#1  Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::begin (this=<optimized out>) at ./kernel/hashlib.h:639
#2  (anonymous namespace)::CxxrtlWorker::dump_attrs (this=this@entry=0x7ffe3cc538e0, 
    object=object@entry=0x0) at backends/cxxrtl/cxxrtl_backend.cc:831
#3  0x0000561db81a71d2 in (anonymous namespace)::CxxrtlWorker::dump_memory (memory=0x0, 
    module=<optimized out>, this=0x7ffe3cc538e0) at backends/cxxrtl/cxxrtl_backend.cc:1666
#4  (anonymous namespace)::CxxrtlWorker::dump_module_intf (this=this@entry=0x7ffe3cc538e0, 
    module=<optimized out>, module@entry=0x561dba1d3890)
    at backends/cxxrtl/cxxrtl_backend.cc:2052
#5  0x0000561db81a8e3f in (anonymous namespace)::CxxrtlWorker::dump_design (
    this=this@entry=0x7ffe3cc538e0, design=design@entry=0x561dba122fe0)
    at backends/cxxrtl/cxxrtl_backend.cc:2259
#6  0x0000561db81af162 in (anonymous namespace)::CxxrtlBackend::execute (
    this=this@entry=0x561db84ee240 <(anonymous namespace)::CxxrtlBackend>, 
    f=@0x7ffe3cc53de8: 0x7faca8cb6480 <std::cout>, filename="<stdout>", 
    args=std::vector of length 1, capacity 1 = {...}, design=design@entry=0x561dba122fe0)
    at backends/cxxrtl/cxxrtl_backend.cc:3203
#7  0x0000561db7d06994 in Yosys::Backend::execute (
    this=this@entry=0x561db84ee240 <(anonymous namespace)::CxxrtlBackend>, 
    args=std::vector of length 1, capacity 1 = {...}, design=design@entry=0x561dba122fe0)
    at kernel/register.cc:644
#8  0x0000561db7d07a43 in Yosys::Pass::call (design=design@entry=0x561dba122fe0, 
    args=std::vector of length 1, capacity 1 = {...}) at kernel/register.cc:316
#9  0x0000561db7d07e09 in Yosys::Pass::call (design=design@entry=0x561dba122fe0, command="")
    at kernel/register.cc:293
#10 0x0000561db7d60ee0 in Yosys::run_pass (command="read_verilog top2.v; write_cxxrtl", 
    design=0x561dba122fe0, design@entry=0x0) at kernel/yosys.cc:1086
#11 0x0000561db7c10811 in main (argc=3, argv=0x7ffe3cc54498) at kernel/driver.cc:538

top.v

// yosys -p "read_verilog top.v; write_cxxrtl"

module testcase(input wire clk, input wire addr, input wire write_data);
  reg data [0 : 1];
  always @(posedge clk)
    data[addr] <= write_data;
endmodule

module top(input wire clk, input wire addr, input wire write_data);
  testcase testcase_instance (
    .clk(clk),
    .addr(addr),
    .write_data(write_data),
  ); 
endmodule