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ipq5018 build test
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build.patch
From 1234567890 Mon Sep 17 00:00:00 2001
From: kimocoder <[email protected]>
Date: Mon, 28 Jul 2025 07:20:00 +0200
Subject: [PATCH] IPQ5018 build test
---
build.sh | 6 ++++++
1 file changed, 6 insertions(+)
create mode 100755 build.sh
diff --git a/build.sh b/build.sh
new file mode 100755
index 0000000..1111111
--- /dev/null
+++ b/build.sh
@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+
+export FORCE_UNSAFE_CONFIGURE=1
+make -j8 V=sc
+cp target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/tsens-v1.c ./build_dir/target-aarch64_cortex-a53_musl/linux-qualcommax_ipq50xx/linux-6.12.40/drivers/thermal/qcom/tsens-v1.c
+make -j8 V=sc
--
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ax6000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ax6000.dts
index 1d2e4f0e85..8133e97d2f 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ax6000.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ax6000.dts
@@ -402,6 +402,8 @@
reg = <17>;
ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
port@1 {
reg = <1>;
label = "lan1";
diff --git a/target/linux/qualcommax/patches-6.12/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch b/target/linux/qualcommax/patches-6.12/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch
deleted file mode 100644
index 9dadee2154..0000000000
--- a/target/linux/qualcommax/patches-6.12/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch
+++ /dev/null
@@ -1,381 +0,0 @@
-From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <[email protected]>
-Date: Tue, 22 Oct 2024 17:47:26 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case
-
-DTS coding style expects labels to be lowercase. No functional impact.
-Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
-
-Signed-off-by: Krzysztof Kozlowski <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---
- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++-----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++-------
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++-----
- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++--------------
- 5 files changed, 61 insertions(+), 61 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -31,27 +31,27 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- CPU0: cpu@0 {
-+ cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- operating-points-v2 = <&cpu_opp_table>;
- };
-
-- CPU1: cpu@1 {
-+ cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- operating-points-v2 = <&cpu_opp_table>;
- };
-
-- L2_0: l2-cache {
-+ l2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x80000>;
---- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
-@@ -31,47 +31,47 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- CPU0: cpu@0 {
-+ cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- operating-points-v2 = <&cpu_opp_table>;
- };
-
-- CPU1: cpu@1 {
-+ cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- operating-points-v2 = <&cpu_opp_table>;
- };
-
-- CPU2: cpu@2 {
-+ cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x2>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- operating-points-v2 = <&cpu_opp_table>;
- };
-
-- CPU3: cpu@3 {
-+ cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x3>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- operating-points-v2 = <&cpu_opp_table>;
- };
-
-- L2_0: l2-cache {
-+ l2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -34,12 +34,12 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- CPU0: cpu@0 {
-+ cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -47,12 +47,12 @@
- #cooling-cells = <2>;
- };
-
-- CPU1: cpu@1 {
-+ cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x1>;
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -60,12 +60,12 @@
- #cooling-cells = <2>;
- };
-
-- CPU2: cpu@2 {
-+ cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x2>;
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -73,12 +73,12 @@
- #cooling-cells = <2>;
- };
-
-- CPU3: cpu@3 {
-+ cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x3>;
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -86,7 +86,7 @@
- #cooling-cells = <2>;
- };
-
-- L2_0: l2-cache {
-+ l2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
-@@ -1015,10 +1015,10 @@
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
-- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -32,39 +32,39 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- CPU0: cpu@0 {
-+ cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- enable-method = "psci";
- };
-
-- CPU1: cpu@1 {
-+ cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x1>;
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- };
-
-- CPU2: cpu@2 {
-+ cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x2>;
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- };
-
-- CPU3: cpu@3 {
-+ cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x3>;
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- };
-
-- L2_0: l2-cache {
-+ l2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
---- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-@@ -34,12 +34,12 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- CPU0: cpu@0 {
-+ cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x0>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -47,12 +47,12 @@
- #cooling-cells = <2>;
- };
-
-- CPU1: cpu@1 {
-+ cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x1>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -60,12 +60,12 @@
- #cooling-cells = <2>;
- };
-
-- CPU2: cpu@2 {
-+ cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x2>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -73,12 +73,12 @@
- #cooling-cells = <2>;
- };
-
-- CPU3: cpu@3 {
-+ cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x3>;
- enable-method = "psci";
-- next-level-cache = <&L2_0>;
-+ next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
-@@ -86,7 +86,7 @@
- #cooling-cells = <2>;
- };
-
-- L2_0: l2-cache {
-+ l2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
-@@ -865,10 +865,10 @@
- cooling-maps {
- map0 {
- trip = <&cpu0_alert>;
-- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-@@ -893,10 +893,10 @@
- cooling-maps {
- map0 {
- trip = <&cpu1_alert>;
-- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-@@ -921,10 +921,10 @@
- cooling-maps {
- map0 {
- trip = <&cpu2_alert>;
-- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-@@ -949,10 +949,10 @@
- cooling-maps {
- map0 {
- trip = <&cpu3_alert>;
-- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
diff --git a/target/linux/qualcommax/patches-6.12/0047-v6.16-PCI-qcom-Add-support-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.12/0047-v6.16-PCI-qcom-Add-support-for-IPQ5018.patch
deleted file mode 100644
index 70e681475f..0000000000
--- a/target/linux/qualcommax/patches-6.12/0047-v6.16-PCI-qcom-Add-support-for-IPQ5018.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 3e5127469a8d41153fb30031a271788f52dd17ec Mon Sep 17 00:00:00 2001
-From: Nitheesh Sekar <[email protected]>
-Date: Wed, 26 Mar 2025 12:10:58 +0400
-Subject: [PATCH] PCI: qcom: Add support for IPQ5018
-
-Add IPQ5018 platform with is based on Qcom IP rev. 2.9.0 and Synopsys IP
-rev. 5.00a.
-
-The platform itself has two PCIe Gen2 controllers: one single-lane and
-one dual-lane. So add the IPQ5018 compatible and re-use 2_9_0 ops.
-
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
-Signed-off-by: Manivannan Sadhasivam <[email protected]>
-Reviewed-by: Manivannan Sadhasivam <[email protected]>
-Link: https://patch.msgid.link/[email protected]
----
- drivers/pci/controller/dwc/pcie-qcom.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -1827,6 +1827,7 @@ static const struct of_device_id qcom_pc
- { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
- { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
- { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
-+ { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 },
- { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
- { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
- { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
diff --git a/target/linux/qualcommax/patches-6.12/0048-v6.16-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch b/target/linux/qualcommax/patches-6.12/0048-v6.16-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch
deleted file mode 100644
index a7fceeba65..0000000000
--- a/target/linux/qualcommax/patches-6.12/0048-v6.16-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch
+++ /dev/null
@@ -1,286 +0,0 @@
-From 18a5bf00a02ca54d51266b861518f2844c4f08d7 Mon Sep 17 00:00:00 2001
-From: Nitheesh Sekar <[email protected]>
-Date: Wed, 14 May 2025 09:52:13 +0400
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PCIe related nodes
-
-Add phy and controller nodes for a 2-lane Gen2 and
-a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
-one global interrupt.
-
-NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2.
-
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Reviewed-by: Manivannan Sadhasivam <[email protected]>
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 240 +++++++++++++++++++++++++-
- 1 file changed, 238 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -147,6 +147,40 @@
- status = "disabled";
- };
-
-+ pcie1_phy: phy@7e000 {
-+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
-+ reg = <0x0007e000 0x800>;
-+
-+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-+
-+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
-+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
-+
-+ #clock-cells = <0>;
-+ #phy-cells = <0>;
-+
-+ num-lanes = <1>;
-+
-+ status = "disabled";
-+ };
-+
-+ pcie0_phy: phy@86000 {
-+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
-+ reg = <0x00086000 0x1000>;
-+
-+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-+
-+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
-+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
-+
-+ #clock-cells = <0>;
-+ #phy-cells = <0>;
-+
-+ num-lanes = <2>;
-+
-+ status = "disabled";
-+ };
-+
- tlmm: pinctrl@1000000 {
- compatible = "qcom,ipq5018-tlmm";
- reg = <0x01000000 0x300000>;
-@@ -170,8 +204,8 @@
- reg = <0x01800000 0x80000>;
- clocks = <&xo_board_clk>,
- <&sleep_clk>,
-- <0>,
-- <0>,
-+ <&pcie0_phy>,
-+ <&pcie1_phy>,
- <0>,
- <0>,
- <0>,
-@@ -387,6 +421,208 @@
- status = "disabled";
- };
- };
-+
-+ pcie1: pcie@80000000 {
-+ compatible = "qcom,pcie-ipq5018";
-+ reg = <0x80000000 0xf1d>,
-+ <0x80000f20 0xa8>,
-+ <0x80001000 0x1000>,
-+ <0x00078000 0x3000>,
-+ <0x80100000 0x1000>,
-+ <0x0007b000 0x1000>;
-+ reg-names = "dbi",
-+ "elbi",
-+ "atu",
-+ "parf",
-+ "config",
-+ "mhi";
-+ device_type = "pci";
-+ linux,pci-domain = <1>;
-+ bus-range = <0x00 0xff>;
-+ num-lanes = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* The controller supports Gen3, but the connected PHY is Gen2-capable */
-+ max-link-speed = <2>;
-+
-+ phys = <&pcie1_phy>;
-+ phy-names ="pciephy";
-+
-+ ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
-+ <0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
-+
-+ msi-map = <0x0 &v2m0 0x0 0xff8>;
-+
-+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "msi0",
-+ "msi1",
-+ "msi2",
-+ "msi3",
-+ "msi4",
-+ "msi5",
-+ "msi6",
-+ "msi7",
-+ "global";
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>,
-+ <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>,
-+ <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>;
-+
-+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
-+ <&gcc GCC_PCIE1_AXI_M_CLK>,
-+ <&gcc GCC_PCIE1_AXI_S_CLK>,
-+ <&gcc GCC_PCIE1_AHB_CLK>,
-+ <&gcc GCC_PCIE1_AUX_CLK>,
-+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
-+ clock-names = "iface",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "aux",
-+ "axi_bridge";
-+
-+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
-+ <&gcc GCC_PCIE1_SLEEP_ARES>,
-+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
-+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
-+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
-+ <&gcc GCC_PCIE1_AHB_ARES>,
-+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
-+ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
-+ reset-names = "pipe",
-+ "sleep",
-+ "sticky",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "axi_m_sticky",
-+ "axi_s_sticky";
-+
-+ status = "disabled";
-+
-+ pcie@0 {
-+ device_type = "pci";
-+ reg = <0x0 0x0 0x0 0x0 0x0>;
-+ bus-range = <0x01 0xff>;
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+ };
-+ };
-+
-+ pcie0: pcie@a0000000 {
-+ compatible = "qcom,pcie-ipq5018";
-+ reg = <0xa0000000 0xf1d>,
-+ <0xa0000f20 0xa8>,
-+ <0xa0001000 0x1000>,
-+ <0x00080000 0x3000>,
-+ <0xa0100000 0x1000>,
-+ <0x00083000 0x1000>;
-+ reg-names = "dbi",
-+ "elbi",
-+ "atu",
-+ "parf",
-+ "config",
-+ "mhi";
-+ device_type = "pci";
-+ linux,pci-domain = <0>;
-+ bus-range = <0x00 0xff>;
-+ num-lanes = <2>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* The controller supports Gen3, but the connected PHY is Gen2-capable */
-+ max-link-speed = <2>;
-+
-+ phys = <&pcie0_phy>;
-+ phy-names ="pciephy";
-+
-+ ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
-+ <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
-+
-+ msi-map = <0x0 &v2m0 0x0 0xff8>;
-+
-+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "msi0",
-+ "msi1",
-+ "msi2",
-+ "msi3",
-+ "msi4",
-+ "msi5",
-+ "msi6",
-+ "msi7",
-+ "global";
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
-+ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
-+ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
-+ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
-+
-+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
-+ <&gcc GCC_PCIE0_AXI_M_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_CLK>,
-+ <&gcc GCC_PCIE0_AHB_CLK>,
-+ <&gcc GCC_PCIE0_AUX_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
-+ clock-names = "iface",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "aux",
-+ "axi_bridge";
-+
-+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
-+ <&gcc GCC_PCIE0_SLEEP_ARES>,
-+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
-+ <&gcc GCC_PCIE0_AHB_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
-+ reset-names = "pipe",
-+ "sleep",
-+ "sticky",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "axi_m_sticky",
-+ "axi_s_sticky";
-+
-+ status = "disabled";
-+
-+ pcie@0 {
-+ device_type = "pci";
-+ reg = <0x0 0x0 0x0 0x0 0x0>;
-+ bus-range = <0x01 0xff>;
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+ };
-+ };
- };
-
- timer {
diff --git a/target/linux/qualcommax/patches-6.12/0049-v6.16-arm64-dts-qcom-ipq5018-enable-the-download-mode-supp.patch b/target/linux/qualcommax/patches-6.12/0049-v6.16-arm64-dts-qcom-ipq5018-enable-the-download-mode-supp.patch
deleted file mode 100644
index 08200516a3..0000000000
--- a/target/linux/qualcommax/patches-6.12/0049-v6.16-arm64-dts-qcom-ipq5018-enable-the-download-mode-supp.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 43fefd6c71291b5793e7c4052b6e3e54d1d87715 Mon Sep 17 00:00:00 2001
-From: George Moussalem <[email protected]>
-Date: Mon, 12 May 2025 18:36:47 +0400
-Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the download mode support
-
-Enable support for download mode to collect RAM dumps in case of a
-system crash, allowing post mortem analysis.
-
-Signed-off-by: George Moussalem <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -79,6 +79,7 @@
- firmware {
- scm {
- compatible = "qcom,scm-ipq5018", "qcom,scm";
-+ qcom,dload-mode = <&tcsr 0x6100>;
- qcom,sdi-enabled;
- };
- };
-@@ -221,6 +222,11 @@
- #hwlock-cells = <1>;
- };
-
-+ tcsr: syscon@1937000 {
-+ compatible = "qcom,tcsr-ipq5018", "syscon";
-+ reg = <0x01937000 0x21000>;
-+ };
-+
- sdhc_1: mmc@7804000 {
- compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
- reg = <0x7804000 0x1000>;
diff --git a/target/linux/qualcommax/patches-6.12/0053-v6.16-thermal-drivers-qcom-tsens-Add-support-for-IPQ5018-t.patch b/target/linux/qualcommax/patches-6.12/0053-v6.16-thermal-drivers-qcom-tsens-Add-support-for-IPQ5018-t.patch
deleted file mode 100644
index 1c09ffc70e..0000000000
--- a/target/linux/qualcommax/patches-6.12/0053-v6.16-thermal-drivers-qcom-tsens-Add-support-for-IPQ5018-t.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 04b31cc53fe0df0e87a37d18a3c0363d7dee218f Mon Sep 17 00:00:00 2001
-From: Sricharan Ramabadhran <[email protected]>
-Date: Fri, 28 Feb 2025 09:11:38 +0400
-Subject: [PATCH] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens
-
-IPQ5018 has tsens IP V1.0, 5 sensors of which 4 are in use and 1
-interrupt. The IP does not have a RPM, hence use init routine for
-tsens v1.0 without RPM which does not early enable.
-
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
-Link: https://lore.kernel.org/r/DS7PR19MB8883BD0E36C08DD1D03CE1CB9DCC2@DS7PR19MB8883.namprd19.prod.outlook.com
-Signed-off-by: Daniel Lezcano <[email protected]>
----
- drivers/thermal/qcom/tsens-v1.c | 14 ++++++++++++++
- drivers/thermal/qcom/tsens.c | 3 +++
- drivers/thermal/qcom/tsens.h | 3 +++
- 3 files changed, 20 insertions(+)
-
---- a/drivers/thermal/qcom/tsens-v1.c
-+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -242,3 +242,17 @@ struct tsens_plat_data data_8976 = {
- .feat = &tsens_v1_feat,
- .fields = tsens_v1_regfields,
- };
-+
-+const struct tsens_ops ops_ipq5018 = {
-+ .init = init_tsens_v1_no_rpm,
-+ .calibrate = tsens_calibrate_common,
-+ .get_temp = get_temp_tsens_valid,
-+};
-+
-+const struct tsens_plat_data data_ipq5018 = {
-+ .num_sensors = 5,
-+ .ops = &ops_ipq5018,
-+ .hw_ids = (unsigned int []){0, 1, 2, 3, 4},
-+ .feat = &tsens_v1_no_rpm_feat,
-+ .fields = tsens_v1_regfields,
-+};
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -1108,6 +1108,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t
-
- static const struct of_device_id tsens_table[] = {
- {
-+ .compatible = "qcom,ipq5018-tsens",
-+ .data = &data_ipq5018,
-+ }, {
- .compatible = "qcom,ipq5332-tsens",
- .data = &data_ipq5332,
- }, {
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -652,6 +652,9 @@ extern struct tsens_plat_data data_8226,
- /* TSENS v1 targets */
- extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956;
-
-+/* TSENS v1 with no RPM targets */
-+extern const struct tsens_plat_data data_ipq5018;
-+
- /* TSENS v2 targets */
- extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
- extern const struct tsens_plat_data data_ipq5332, data_ipq5424;
diff --git a/target/linux/qualcommax/patches-6.12/0122-arm64-dts-ipq8074-add-CPU-clock.patch b/target/linux/qualcommax/patches-6.12/0122-arm64-dts-ipq8074-add-CPU-clock.patch
deleted file mode 100644
index a6265ff006..0000000000
--- a/target/linux/qualcommax/patches-6.12/0122-arm64-dts-ipq8074-add-CPU-clock.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 31 Dec 2021 17:56:14 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
-
-Now that CPU clock is exposed and can be controlled, add the necessary
-properties to the CPU nodes.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -5,6 +5,7 @@
-
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
-+#include <dt-bindings/clock/qcom,apss-ipq.h>
-
- / {
- #address-cells = <2>;
-@@ -38,6 +39,8 @@
- reg = <0x0>;
- next-level-cache = <&l2_0>;
- enable-method = "psci";
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- cpu1: cpu@1 {
-@@ -46,6 +49,8 @@
- enable-method = "psci";
- reg = <0x1>;
- next-level-cache = <&l2_0>;
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- cpu2: cpu@2 {
-@@ -54,6 +59,8 @@
- enable-method = "psci";
- reg = <0x2>;
- next-level-cache = <&l2_0>;
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- cpu3: cpu@3 {
-@@ -62,6 +69,8 @@
- enable-method = "psci";
- reg = <0x3>;
- next-level-cache = <&l2_0>;
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- l2_0: l2-cache {
diff --git a/target/linux/qualcommax/patches-6.12/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch b/target/linux/qualcommax/patches-6.12/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch
deleted file mode 100644
index bea358045f..0000000000
--- a/target/linux/qualcommax/patches-6.12/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 347ca56e86c99021fad059b9a8ef101245b8507e Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 31 Dec 2021 20:38:06 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes
-
-Since there is CPU Freq support as well as thermal sensor support
-now for the IPQ8074, add cooling cells to CPU nodes so that they can
-be used as cooling devices using CPU Freq.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -41,6 +41,7 @@
- enable-method = "psci";
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
-@@ -51,6 +52,7 @@
- next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
-@@ -61,6 +63,7 @@
- next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
-@@ -71,6 +74,7 @@
- next-level-cache = <&l2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- l2_0: l2-cache {
diff --git a/target/linux/qualcommax/patches-6.12/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch b/target/linux/qualcommax/patches-6.12/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch
deleted file mode 100644
index 9de502c4c3..0000000000
--- a/target/linux/qualcommax/patches-6.12/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Sat, 31 Dec 2022 13:56:26 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table
-
-Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
-table for SoC.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -42,6 +42,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- cpu1: cpu@1 {
-@@ -53,6 +54,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- cpu2: cpu@2 {
-@@ -64,6 +66,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- cpu3: cpu@3 {
-@@ -75,6 +78,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- l2_0: l2-cache {
-@@ -84,6 +88,54 @@
- };
- };
-
-+ cpu_opp_table: opp-table {
-+ compatible = "operating-points-v2-kryo-cpu";
-+ nvmem-cells = <&cpr_efuse_speedbin>;
-+ opp-shared;
-+
-+ opp-1017600000 {
-+ opp-hz = /bits/ 64 <1017600000>;
-+ opp-microvolt = <1>;
-+ opp-supported-hw = <0xf>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1382400000 {
-+ opp-hz = /bits/ 64 <1382400000>;
-+ opp-microvolt = <2>;
-+ opp-supported-hw = <0xf>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1651200000 {
-+ opp-hz = /bits/ 64 <1651200000>;
-+ opp-microvolt = <3>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1843200000 {
-+ opp-hz = /bits/ 64 <1843200000>;
-+ opp-microvolt = <4>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1920000000 {
-+ opp-hz = /bits/ 64 <1920000000>;
-+ opp-microvolt = <5>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-2208000000 {
-+ opp-hz = /bits/ 64 <2208000000>;
-+ opp-microvolt = <6>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+ };
-+
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
diff --git a/target/linux/qualcommax/patches-6.12/0150-arm64-dts-qcom-ipq5018-Add-tsens-node.patch b/target/linux/qualcommax/patches-6.12/0150-arm64-dts-qcom-ipq5018-Add-tsens-node.patch
deleted file mode 100644
index bed9a1dc00..0000000000
--- a/target/linux/qualcommax/patches-6.12/0150-arm64-dts-qcom-ipq5018-Add-tsens-node.patch
+++ /dev/null
@@ -1,203 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Fri, 28 Feb 2025 09:11:39 +0400
-Subject: [PATCH v9 6/6] arm64: dts: qcom: ipq5018: Add tsens node
-
-From: Sricharan Ramabadhran <[email protected]>
-
-IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
-There is no RPM, so tsens has to be manually enabled. Adding the tsens
-and nvmem nodes and adding 4 thermal sensors (zones). With the
-critical temperature being 120'C and action is to reboot.
-
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++
- 1 file changed, 169 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -182,6 +182,117 @@
- status = "disabled";
- };
-
-+ qfprom: qfprom@a0000 {
-+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
-+ reg = <0x000a0000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ tsens_mode: mode@249 {
-+ reg = <0x249 0x1>;
-+ bits = <0 3>;
-+ };
-+
-+ tsens_base1: base1@249 {
-+ reg = <0x249 0x2>;
-+ bits = <3 8>;
-+ };
-+
-+ tsens_base2: base2@24a {
-+ reg = <0x24a 0x2>;
-+ bits = <3 8>;
-+ };
-+
-+ tsens_s0_p1: s0-p1@24b {
-+ reg = <0x24b 0x2>;
-+ bits = <2 6>;
-+ };
-+
-+ tsens_s0_p2: s0-p2@24c {
-+ reg = <0x24c 0x1>;
-+ bits = <1 6>;
-+ };
-+
-+ tsens_s1_p1: s1-p1@24c {
-+ reg = <0x24c 0x2>;
-+ bits = <7 6>;
-+ };
-+
-+ tsens_s1_p2: s1-p2@24d {
-+ reg = <0x24d 0x2>;
-+ bits = <5 6>;
-+ };
-+
-+ tsens_s2_p1: s2-p1@24e {
-+ reg = <0x24e 0x2>;
-+ bits = <3 6>;
-+ };
-+
-+ tsens_s2_p2: s2-p2@24f {
-+ reg = <0x24f 0x1>;
-+ bits = <1 6>;
-+ };
-+
-+ tsens_s3_p1: s3-p1@24f {
-+ reg = <0x24f 0x2>;
-+ bits = <7 6>;
-+ };
-+
-+ tsens_s3_p2: s3-p2@250 {
-+ reg = <0x250 0x2>;
-+ bits = <5 6>;
-+ };
-+
-+ tsens_s4_p1: s4-p1@251 {
-+ reg = <0x251 0x2>;
-+ bits = <3 6>;
-+ };
-+
-+ tsens_s4_p2: s4-p2@254 {
-+ reg = <0x254 0x1>;
-+ bits = <0 6>;
-+ };
-+ };
-+
-+ tsens: thermal-sensor@4a9000 {
-+ compatible = "qcom,ipq5018-tsens";
-+ reg = <0x004a9000 0x1000>, /* TM */
-+ <0x004a8000 0x1000>; /* SROT */
-+
-+ nvmem-cells = <&tsens_mode>,
-+ <&tsens_base1>,
-+ <&tsens_base2>,
-+ <&tsens_s0_p1>,
-+ <&tsens_s0_p2>,
-+ <&tsens_s1_p1>,
-+ <&tsens_s1_p2>,
-+ <&tsens_s2_p1>,
-+ <&tsens_s2_p2>,
-+ <&tsens_s3_p1>,
-+ <&tsens_s3_p2>,
-+ <&tsens_s4_p1>,
-+ <&tsens_s4_p2>;
-+
-+ nvmem-cell-names = "mode",
-+ "base1",
-+ "base2",
-+ "s0_p1",
-+ "s0_p2",
-+ "s1_p1",
-+ "s1_p2",
-+ "s2_p1",
-+ "s2_p2",
-+ "s3_p1",
-+ "s3_p2",
-+ "s4_p1",
-+ "s4_p2";
-+
-+ interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
-+ interrupt-names = "uplow";
-+ #qcom,sensors = <5>;
-+ #thermal-sensor-cells = <1>;
-+ };
-+
- tlmm: pinctrl@1000000 {
- compatible = "qcom,ipq5018-tlmm";
- reg = <0x01000000 0x300000>;
-@@ -630,6 +741,64 @@
- };
- };
- };
-+
-+ thermal-zones {
-+ cpu-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 2>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ gephy-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 4>;
-+
-+ trips {
-+ gephy-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ top-glue-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 3>;
-+
-+ trips {
-+ top_glue-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ ubi32-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 1>;
-+
-+ trips {
-+ ubi32-critical {
-+ temperature = <120000>;
-+ hysteresis = <2>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+ };
-
- timer {
- compatible = "arm,armv8-timer";
diff --git a/target/linux/qualcommax/patches-6.12/0304-dt-bindings-pwm-add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.12/0304-dt-bindings-pwm-add-IPQ5018-compatible.patch
deleted file mode 100644
index 5705028931..0000000000
--- a/target/linux/qualcommax/patches-6.12/0304-dt-bindings-pwm-add-IPQ5018-compatible.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] dt-bindings: mfd: qcom,tcsr: Add IPQ5018 compatible
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add compatible for IPQ5018.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml
-+++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml
-@@ -11,7 +11,10 @@ maintainers:
-
- properties:
- compatible:
-- const: qcom,ipq6018-pwm
-+ items:
-+ - enum:
-+ - qcom,ipq5018-pwm
-+ - const: qcom,ipq6018-pwm
-
- reg:
- description: Offset of PWM register in the TCSR block.
diff --git a/target/linux/qualcommax/patches-6.12/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch b/target/linux/qualcommax/patches-6.12/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch
deleted file mode 100644
index 476e5f6ba1..0000000000
--- a/target/linux/qualcommax/patches-6.12/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] pinctrl: qcom: IPQ5018: update pwm groups
-Date: Wed, 27 Nov 2024 09:14:11 +0400
-
-GPIO 1, 30, and 46 are used to control PWM1, PWM3, and PWM0 respectively which
-in turn drive the PWM led, so let's update the pwm# and pingroups accordingly.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c
-+++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
-@@ -541,7 +541,7 @@ static const char * const qdss_tracectl_
- };
-
- static const char * const pwm0_groups[] = {
-- "gpio42",
-+ "gpio42", "gpio46",
- };
-
- static const char * const qdss_cti_trig_out_b0_groups[] = {
-@@ -549,7 +549,7 @@ static const char * const qdss_cti_trig_
- };
-
- static const char * const pwm1_groups[] = {
-- "gpio43",
-+ "gpio43", "gpio1",
- };
-
- static const char * const qdss_cti_trig_in_b0_groups[] = {
-@@ -565,7 +565,7 @@ static const char * const qdss_cti_trig_
- };
-
- static const char * const pwm3_groups[] = {
-- "gpio45",
-+ "gpio45", "gpio30",
- };
-
- static const char * const qdss_cti_trig_in_b1_groups[] = {
-@@ -679,7 +679,7 @@ static const struct pinfunction ipq5018_
-
- static const struct msm_pingroup ipq5018_groups[] = {
- PINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _),
-- PINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
-+ PINGROUP(1, atest_char, pwm1, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
- PINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _),
- PINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _),
- PINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _),
-@@ -708,7 +708,7 @@ static const struct msm_pingroup ipq5018
- PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _),
- PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _),
- PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _),
-- PINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _),
-+ PINGROUP(30, audio_txd, led2, led0, pwm3, _, _, _, _, _),
- PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
- PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
- PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
-@@ -724,7 +724,7 @@ static const struct msm_pingroup ipq5018
- PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
- PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
- PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
-- PINGROUP(46, led0, _, _, _, _, _, _, _, _),
-+ PINGROUP(46, led0, pwm0, _, _, _, _, _, _, _),
- };
-
- static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {
diff --git a/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch b/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
deleted file mode 100644
index b97aa11ebc..0000000000
--- a/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PWM node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add PWM node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -338,6 +338,16 @@
- reg = <0x01937000 0x21000>;
- };
-
-+ pwm: pwm@1941010 {
-+ compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm";
-+ reg = <0x01941010 0x20>;
-+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+ assigned-clock-rates = <100000000>;
-+ #pwm-cells = <2>;
-+ status = "disabled";
-+ };
-+
- sdhc_1: mmc@7804000 {
- compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
- reg = <0x7804000 0x1000>;
diff --git a/target/linux/qualcommax/patches-6.12/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch b/target/linux/qualcommax/patches-6.12/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
deleted file mode 100644
index 135624d97a..0000000000
--- a/target/linux/qualcommax/patches-6.12/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add crypto nodes
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add dma controller and crypto nodes.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -293,6 +293,30 @@
- #thermal-sensor-cells = <1>;
- };
-
-+ cryptobam: dma-controller@704000 {
-+ compatible = "qcom,bam-v1.7.0";
-+ reg = <0x00704000 0x20000>;
-+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
-+ clock-names = "bam_clk";
-+ #dma-cells = <1>;
-+ qcom,ee = <1>;
-+ qcom,controlled-remotely;
-+ status = "disabled";
-+ };
-+
-+ crypto: crypto@73a000 {
-+ compatible = "qcom,crypto-v5.1";
-+ reg = <0x0073a000 0x6000>;
-+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
-+ <&gcc GCC_CRYPTO_AXI_CLK>,
-+ <&gcc GCC_CRYPTO_CLK>;
-+ clock-names = "iface", "bus", "core";
-+ dmas = <&cryptobam 2>, <&cryptobam 3>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
- tlmm: pinctrl@1000000 {
- compatible = "qcom,ipq5018-tlmm";
- reg = <0x01000000 0x300000>;
diff --git a/target/linux/qualcommax/patches-6.12/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch b/target/linux/qualcommax/patches-6.12/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
deleted file mode 100644
index 23fb94e0e7..0000000000
--- a/target/linux/qualcommax/patches-6.12/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PRNG node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add PRNG node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -254,6 +254,14 @@
- };
- };
-
-+ prng: rng@e3000 {
-+ compatible = "qcom,prng-ee";
-+ reg = <0x000e3000 0x1000>;
-+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
-+ clock-names = "core";
-+ status = "disabled";
-+ };
-+
- tsens: thermal-sensor@4a9000 {
- compatible = "qcom,ipq5018-tsens";
- reg = <0x004a9000 0x1000>, /* TM */
diff --git a/target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch b/target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
deleted file mode 100644
index c875690b58..0000000000
--- a/target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add QUP1-UART2 node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add QUP1-UART2 node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -417,6 +417,16 @@
- status = "disabled";
- };
-
-+ blsp1_uart2: serial@78b0000 {
-+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+ reg = <0x078b0000 0x200>;
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
-+ };
-+
- blsp1_spi1: spi@78b5000 {
- compatible = "qcom,spi-qup-v2.2.1";
- #address-cells = <1>;
diff --git a/target/linux/qualcommax/patches-6.12/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch b/target/linux/qualcommax/patches-6.12/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
deleted file mode 100644
index 70ddcc7147..0000000000
--- a/target/linux/qualcommax/patches-6.12/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add QUP3 I2C node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add QUP3-I2C node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -441,6 +441,21 @@
- status = "disabled";
- };
-
-+ blsp1_i2c3: i2c@78b7000 {
-+ compatible = "qcom,i2c-qup-v2.2.1";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x078b7000 0x600>;
-+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ clock-frequency = <400000>;
-+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
-+ dma-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
- usb: usb@8af8800 {
- compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
- reg = <0x08af8800 0x400>;
diff --git a/target/linux/qualcommax/patches-6.12/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch b/target/linux/qualcommax/patches-6.12/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
deleted file mode 100644
index 516b46743b..0000000000
--- a/target/linux/qualcommax/patches-6.12/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From c2019f64539dd24e6e0da3cea2219d6f9e6b03e4 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:11 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add SPI nand node
-
-Add SPI NAND support for IPQ5018 SoC.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
- 1 file changed, 40 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -456,6 +456,36 @@
- status = "disabled";
- };
-
-+ qpic_bam: dma@7984000 {
-+ compatible = "qcom,bam-v1.7.0";
-+ reg = <0x07984000 0x1c000>;
-+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
-+ clock-names = "bam_clk";
-+ #dma-cells = <1>;
-+ qcom,ee = <0>;
-+ status = "disabled";
-+ };
-+
-+ qpic_nand: qpic-nand@79b0000 {
-+ compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand";
-+ reg = <0x079b0000 0x10000>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ clocks = <&gcc GCC_QPIC_CLK>,
-+ <&gcc GCC_QPIC_AHB_CLK>,
-+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
-+ clock-names = "core", "aon", "iom";
-+
-+ dmas = <&qpic_bam 0>,
-+ <&qpic_bam 1>,
-+ <&qpic_bam 2>,
-+ <&qpic_bam 3>;
-+ dma-names = "tx", "rx", "cmd", "status";
-+
-+ status = "disabled";
-+ };
-+
- usb: usb@8af8800 {
- compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
- reg = <0x08af8800 0x400>;
diff --git a/target/linux/qualcommax/patches-6.12/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch b/target/linux/qualcommax/patches-6.12/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch
deleted file mode 100644
index 75b37df9aa..0000000000
--- a/target/linux/qualcommax/patches-6.12/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From a28797563b8c97c9abced82e0cf89302fcd2bf37 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:11 +0800
-Subject: [PATCH 1/2] clk: qcom: cmn-pll: add IPQ5018 support
-
-Add support for IPQ5018 (and removing dependency on the IPQ9574 platform).
-The common network block in IPQ5018 must be enabled first through a
-specific register at a fixed offset in the TCSR area, set in the DTS.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- drivers/clk/qcom/Kconfig | 1 -
- drivers/clk/qcom/clk-ipq-cmn-pll.c | 29 +++++++++++++++++++++++++++++
- 2 files changed, 29 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/Kconfig
-+++ b/drivers/clk/qcom/Kconfig
-@@ -192,7 +192,6 @@ config IPQ_APSS_6018
-
- config IPQ_CMN_PLL
- tristate "IPQ CMN PLL Clock Controller"
-- depends on IPQ_GCC_9574
- help
- Support for CMN PLL clock controller on IPQ platform. The
- CMN PLL feeds the reference clocks to the Ethernet devices
---- a/drivers/clk/qcom/clk-ipq-cmn-pll.c
-+++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c
-@@ -42,6 +42,9 @@
- #include <linux/platform_device.h>
- #include <linux/slab.h>
-
-+#define TCSR_ETH_CMN 0x0
-+#define TCSR_ETH_CMN_ENABLE BIT(0)
-+
- #define CMN_PLL_REFCLK_SRC_SELECTION 0x28
- #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8)
-
-@@ -79,6 +82,28 @@ static const struct cmn_pll_fixed_output
- CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
- };
-
-+static int ipq_cmn_pll_tcsr_enable(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ void __iomem *tcsr_base;
-+ u32 val;
-+
-+ /* For IPQ50xx, tcsr is necessary to enable cmn block */
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr");
-+ if (!res)
-+ return 0;
-+
-+ tcsr_base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR_OR_NULL(tcsr_base))
-+ return PTR_ERR(tcsr_base);
-+
-+ val = readl(tcsr_base + TCSR_ETH_CMN);
-+ val |= TCSR_ETH_CMN_ENABLE;
-+ writel(val, (tcsr_base + TCSR_ETH_CMN));
-+
-+ return 0;
-+}
-+
- static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
- {
- void __iomem *base;
-@@ -181,6 +206,10 @@ static int ipq_cmn_pll_clk_probe(struct
- struct clk *clk;
- int ret;
-
-+ ret = ipq_cmn_pll_tcsr_enable(pdev);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Enable CMN PLL failed\n");
-+
- /*
- * To access the CMN PLL registers, the GCC AHB & SYSY clocks
- * for CMN PLL block need to be enabled.
diff --git a/target/linux/qualcommax/patches-6.12/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch b/target/linux/qualcommax/patches-6.12/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
deleted file mode 100644
index e528a9b86d..0000000000
--- a/target/linux/qualcommax/patches-6.12/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 1b625a37b96b0448aac126d7720eec38de8e5956 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:11 +0800
-Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: Add ethernet cmn node
-
-Signed-off-by: Ziyang Huang <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -16,6 +16,12 @@
- #size-cells = <2>;
-
- clocks {
-+ cmn_pll_ref_clk: cmn-pll-ref-clk {
-+ compatible = "fixed-clock";
-+ clock-frequency = <96000000>;
-+ #clock-cells = <0>;
-+ };
-+
- sleep_clk: sleep-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
-@@ -182,6 +188,17 @@
- status = "disabled";
- };
-
-+ cmn_pll: clock-controller@9b000 {
-+ compatible = "qcom,ipq9574-cmn-pll";
-+ reg = <0x0009b000 0x800>;
-+ reg-names = "cmn";
-+ clocks = <&cmn_pll_ref_clk>,
-+ <&gcc GCC_CMN_BLK_AHB_CLK>,
-+ <&gcc GCC_CMN_BLK_SYS_CLK>;
-+ clock-names = "ref", "ahb", "sys";
-+ #clock-cells = <1>;
-+ };
-+
- qfprom: qfprom@a0000 {
- compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
- reg = <0x000a0000 0x1000>;
diff --git a/target/linux/qualcommax/patches-6.12/0711-clk-qcom-gcc-ipq5018-fix-ge-phy-reset.patch b/target/linux/qualcommax/patches-6.12/0711-clk-qcom-gcc-ipq5018-fix-ge-phy-reset.patch
deleted file mode 100644
index 72d86c6783..0000000000
--- a/target/linux/qualcommax/patches-6.12/0711-clk-qcom-gcc-ipq5018-fix-ge-phy-reset.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 19600588e6403ff9f6c1e985fc025afb9160a56f Mon Sep 17 00:00:00 2001
-From: George Moussalem <[email protected]>
-Date: Wed, 28 May 2025 08:37:25 +0400
-Subject: [PATCH v2 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <[email protected]>
-
-The MISC reset is supposed to trigger a resets across the MDC, DSP, and
-RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
-of the reset definition accordingly in the GCC as per the downstream
-driver.
-
-Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
-
-Signed-off-by: George Moussalem <[email protected]>
----
- drivers/clk/qcom/gcc-ipq5018.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/gcc-ipq5018.c
-+++ b/drivers/clk/qcom/gcc-ipq5018.c
-@@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_i
- [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
- [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
- [GCC_WCSSAON_RESET] = { 0x59010, 0},
-- [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
-+ [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) },
- };
-
- static const struct of_device_id gcc_ipq5018_match_table[] = {
diff --git a/target/linux/qualcommax/patches-6.12/0712-net-phy-qcom-at803x-add-qualcomm-ipq5018-internal-phy-support.patch b/target/linux/qualcommax/patches-6.12/0712-net-phy-qcom-at803x-add-qualcomm-ipq5018-internal-phy-support.patch
deleted file mode 100644
index 394eca19da..0000000000
--- a/target/linux/qualcommax/patches-6.12/0712-net-phy-qcom-at803x-add-qualcomm-ipq5018-internal-phy-support.patch
+++ /dev/null
@@ -1,277 +0,0 @@
-From 9a89cb300c1ed5b90bae5684c88c85895a15c849 Mon Sep 17 00:00:00 2001
-From: George Moussalem <[email protected]>
-Date: Mon, 02 Jun 2025 12:50:39 +0400
-Subject: [PATCH v3 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <[email protected]>
-
-The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which
-provides an MDI interface directly to an RJ45 connector or an external
-switch over a PHY to PHY link.
-
-The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and
-802.3az EEE.
-
-Let's add support for this PHY in the at803x driver as it falls within
-the Qualcomm Atheros OUI.
-
-Signed-off-by: George Moussalem <[email protected]>
----
- drivers/net/phy/qcom/Kconfig | 2 +-
- drivers/net/phy/qcom/at803x.c | 185 ++++++++++++++++++++++++++++++++++++++++--
- 2 files changed, 178 insertions(+), 9 deletions(-)
-
---- a/drivers/net/phy/qcom/Kconfig
-+++ b/drivers/net/phy/qcom/Kconfig
-@@ -7,7 +7,7 @@ config AT803X_PHY
- select QCOM_NET_PHYLIB
- depends on REGULATOR
- help
-- Currently supports the AR8030, AR8031, AR8033, AR8035 model
-+ Currently supports the AR8030, AR8031, AR8033, AR8035, IPQ5018 model
-
- config QCA83XX_PHY
- tristate "Qualcomm Atheros QCA833x PHYs"
---- a/drivers/net/phy/qcom/at803x.c
-+++ b/drivers/net/phy/qcom/at803x.c
-@@ -7,19 +7,24 @@
- * Author: Matus Ujhelyi <[email protected]>
- */
-
--#include <linux/phy.h>
--#include <linux/module.h>
--#include <linux/string.h>
--#include <linux/netdevice.h>
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
- #include <linux/etherdevice.h>
- #include <linux/ethtool_netlink.h>
--#include <linux/bitfield.h>
--#include <linux/regulator/of_regulator.h>
--#include <linux/regulator/driver.h>
--#include <linux/regulator/consumer.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/netdevice.h>
- #include <linux/of.h>
-+#include <linux/phy.h>
- #include <linux/phylink.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/of_regulator.h>
-+#include <linux/reset.h>
- #include <linux/sfp.h>
-+#include <linux/string.h>
- #include <dt-bindings/net/qca-ar803x.h>
-
- #include "qcom.h"
-@@ -93,6 +98,8 @@
- #define ATH8035_PHY_ID 0x004dd072
- #define AT8030_PHY_ID_MASK 0xffffffef
-
-+#define IPQ5018_PHY_ID 0x004dd0c0
-+
- #define QCA9561_PHY_ID 0x004dd042
-
- #define AT803X_PAGE_FIBER 0
-@@ -105,6 +112,50 @@
- /* disable hibernation mode */
- #define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
-
-+#define IPQ5018_PHY_FIFO_CONTROL 0x19
-+#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0)
-+
-+#define IPQ5018_PHY_DEBUG_EDAC 0x4380
-+#define IPQ5018_PHY_MMD1_MDAC 0x8100
-+#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8)
-+
-+/* MDAC and EDAC values for short cable length */
-+#define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10
-+#define IPQ5018_PHY_MMD1_MDAC_VAL 0x10
-+
-+#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000
-+#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001
-+#define IPQ5018_PHY_PCS_AZ_CTRL1 0x8008
-+#define IPQ5018_PHY_PCS_AZ_CTRL2 0x8009
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f
-+
-+#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1
-+#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6
-+#define IPQ5018_PHY_PCS_AZ_CTRL1_VAL 0x7880
-+#define IPQ5018_PHY_PCS_AZ_CTRL2_VAL 0xc8
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060
-+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060
-+#define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0
-+
-+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1
-+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4)
-+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50
-+#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080
-+
-+#define IPQ5018_TCSR_ETH_LDO_READY BIT(0)
-+
- MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
- MODULE_AUTHOR("Matus Ujhelyi");
- MODULE_LICENSE("GPL");
-@@ -130,6 +181,11 @@ struct at803x_context {
- u16 led_control;
- };
-
-+struct ipq5018_priv {
-+ struct reset_control *rst;
-+ bool set_short_cable_dac;
-+};
-+
- static int at803x_write_page(struct phy_device *phydev, int page)
- {
- int mask;
-@@ -960,6 +1016,105 @@ static int at8035_probe(struct phy_devic
- return at8035_parse_dt(phydev);
- }
-
-+static int ipq5018_cable_test_start(struct phy_device *phydev)
-+{
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
-+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4,
-+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5,
-+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6,
-+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7,
-+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9,
-+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13,
-+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
-+ IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL);
-+
-+ /* we do all the (time consuming) work later */
-+ return 0;
-+}
-+
-+static int ipq5018_config_init(struct phy_device *phydev)
-+{
-+ struct ipq5018_priv *priv = phydev->priv;
-+ u16 val = 0;
-+
-+ /*
-+ * set LDO efuse: first temporarily store ANA_DAC_FILTER value from
-+ * debug register as it will be reset once the ANA_LDO_EFUSE register
-+ * is written to
-+ */
-+ val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER);
-+ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE,
-+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK,
-+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
-+ at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
-+
-+ /* set 8023AZ CTRL values */
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL1,
-+ IPQ5018_PHY_PCS_AZ_CTRL1_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL2,
-+ IPQ5018_PHY_PCS_AZ_CTRL2_VAL);
-+
-+ /* set MSE threshold values */
-+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1,
-+ IPQ5018_PHY_MMD1_MSE_THRESH1_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2,
-+ IPQ5018_PHY_MMD1_MSE_THRESH2_VAL);
-+
-+ /* PHY DAC values are optional and only set in a PHY to PHY link architecture */
-+ if (priv->set_short_cable_dac) {
-+ /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */
-+ phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC,
-+ IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL);
-+
-+ /* setting EDAC (Error-detection and Correction) in debug register */
-+ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC,
-+ IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL);
-+ }
-+
-+ return 0;
-+}
-+
-+static void ipq5018_link_change_notify(struct phy_device *phydev)
-+{
-+ mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
-+ IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET,
-+ phydev->link ? IPQ5018_PHY_FIFO_RESET : 0);
-+}
-+
-+static int ipq5018_probe(struct phy_device *phydev)
-+{
-+ struct device *dev = &phydev->mdio.dev;
-+ struct ipq5018_priv *priv;
-+ int ret;
-+
-+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->set_short_cable_dac = of_property_read_bool(dev->of_node,
-+ "qcom,dac-preset-short-cable");
-+
-+ priv->rst = devm_reset_control_array_get_exclusive(dev);
-+ if (IS_ERR_OR_NULL(priv->rst))
-+ return dev_err_probe(dev, PTR_ERR(priv->rst),
-+ "failed to acquire reset\n");
-+
-+ ret = reset_control_reset(priv->rst);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "failed to reset\n");
-+
-+ phydev->priv = priv;
-+
-+ return 0;
-+}
-+
- static struct phy_driver at803x_driver[] = {
- {
- /* Qualcomm Atheros AR8035 */
-@@ -1052,6 +1207,19 @@ static struct phy_driver at803x_driver[]
- .soft_reset = genphy_soft_reset,
- .config_aneg = at803x_config_aneg,
- }, {
-+ PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID),
-+ .name = "Qualcomm Atheros IPQ5018 internal PHY",
-+ .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST,
-+ .probe = ipq5018_probe,
-+ .config_init = ipq5018_config_init,
-+ .link_change_notify = ipq5018_link_change_notify,
-+ .read_status = at803x_read_status,
-+ .config_intr = at803x_config_intr,
-+ .handle_interrupt = at803x_handle_interrupt,
-+ .cable_test_start = ipq5018_cable_test_start,
-+ .cable_test_get_status = qca808x_cable_test_get_status,
-+ .soft_reset = genphy_soft_reset,
-+}, {
- /* Qualcomm Atheros QCA9561 */
- PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
- .name = "Qualcomm Atheros QCA9561 built-in PHY",
-@@ -1077,6 +1245,7 @@ static const struct mdio_device_id __may
- { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
- { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
- { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
-+ { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) },
- { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
- { }
- };
diff --git a/target/linux/qualcommax/patches-6.12/0713-arm64-dts-qcom-ipq5018-add-mdio-buses.patch b/target/linux/qualcommax/patches-6.12/0713-arm64-dts-qcom-ipq5018-add-mdio-buses.patch
deleted file mode 100644
index d99f49ccad..0000000000
--- a/target/linux/qualcommax/patches-6.12/0713-arm64-dts-qcom-ipq5018-add-mdio-buses.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 97a159dd7747724619e54cb3460d9b8d4ed08be7 Mon Sep 17 00:00:00 2001
-From: George Moussalem <[email protected]>
-Date: Mon, 02 Jun 2025 12:50:40 +0400
-Subject: [PATCH v3 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <[email protected]>
-
-IPQ5018 contains two mdio buses of which one bus is used to control the
-SoC's internal GE PHY, while the other bus is connected to external PHYs
-or switches.
-
-There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's
-simply add the mdio nodes for them.
-
-Reviewed-by: Konrad Dybcio <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -188,6 +188,30 @@
- status = "disabled";
- };
-
-+ mdio0: mdio@88000 {
-+ compatible = "qcom,ipq5018-mdio";
-+ reg = <0x00088000 0x64>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ clocks = <&gcc GCC_MDIO0_AHB_CLK>;
-+ clock-names = "gcc_mdio_ahb_clk";
-+
-+ status = "disabled";
-+ };
-+
-+ mdio1: mdio@90000 {
-+ compatible = "qcom,ipq5018-mdio";
-+ reg = <0x00090000 0x64>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ clocks = <&gcc GCC_MDIO1_AHB_CLK>;
-+ clock-names = "gcc_mdio_ahb_clk";
-+
-+ status = "disabled";
-+ };
-+
- cmn_pll: clock-controller@9b000 {
- compatible = "qcom,ipq9574-cmn-pll";
- reg = <0x0009b000 0x800>;
diff --git a/target/linux/qualcommax/patches-6.12/0714-arm64-dts-qcom-ipq5018-add-ge-phy-to-internal-mdio-bus.patch b/target/linux/qualcommax/patches-6.12/0714-arm64-dts-qcom-ipq5018-add-ge-phy-to-internal-mdio-bus.patch
deleted file mode 100644
index e3b1fa970d..0000000000
--- a/target/linux/qualcommax/patches-6.12/0714-arm64-dts-qcom-ipq5018-add-ge-phy-to-internal-mdio-bus.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 1b733e878ac1292c6e0f2e9a49685b80c35619b0 Mon Sep 17 00:00:00 2001
-From: George Moussalem <[email protected]>
-Date: Mon, 02 Jun 2025 12:50:41 +0400
-Subject: [PATCH v3 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <[email protected]>
-
-The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
-As such, let's add the GE PHY node to the SoC dtsi.
-
-The LDO controller found in the SoC must be enabled to provide constant
-low voltages to the PHY. The mdio-ipq4019 driver already has support
-for this, so adding the appropriate TCSR register offset.
-
-In addition, the GE PHY outputs both the RX and TX clocks to the GCC
-which gate controls them and routes them back to the PHY itself.
-So let's create two DT fixed clocks and register them in the GCC node.
-
-Reviewed-by: Konrad Dybcio <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++---
- 1 file changed, 23 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -22,6 +22,18 @@
- #clock-cells = <0>;
- };
-
-+ gephy_rx_clk: gephy-rx-clk {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ #clock-cells = <0>;
-+ };
-+
-+ gephy_tx_clk: gephy-tx-clk {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ #clock-cells = <0>;
-+ };
-+
- sleep_clk: sleep-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
-@@ -190,7 +202,8 @@
-
- mdio0: mdio@88000 {
- compatible = "qcom,ipq5018-mdio";
-- reg = <0x00088000 0x64>;
-+ reg = <0x00088000 0x64>,
-+ <0x019475c4 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
-
-@@ -198,6 +211,13 @@
- clock-names = "gcc_mdio_ahb_clk";
-
- status = "disabled";
-+
-+ ge_phy: ethernet-phy@7 {
-+ compatible = "ethernet-phy-id004d.d0c0";
-+ reg = <7>;
-+
-+ resets = <&gcc GCC_GEPHY_MISC_ARES>;
-+ };
- };
-
- mdio1: mdio@90000 {
-@@ -392,8 +412,8 @@
- <&pcie0_phy>,
- <&pcie1_phy>,
- <0>,
-- <0>,
-- <0>,
-+ <&gephy_rx_clk>,
-+ <&gephy_tx_clk>,
- <0>,
- <0>;
- #clock-cells = <1>;
diff --git a/target/linux/qualcommax/patches-6.12/0715-arm64-dts-qcom-ipq5018-add-vendor-compatible-to-mdio-node.patch b/target/linux/qualcommax/patches-6.12/0715-arm64-dts-qcom-ipq5018-add-vendor-compatible-to-mdio-node.patch
deleted file mode 100644
index e7dffa8910..0000000000
--- a/target/linux/qualcommax/patches-6.12/0715-arm64-dts-qcom-ipq5018-add-vendor-compatible-to-mdio-node.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Wed, 28 May 2025 08:37:28 +0400
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add vendor compatible to mdio bus
-
-QCA SSDK needs to register the MDIO bus in its driver. Without a proper reference,
-it will crash. Since it tries to look up the MDIO bus using compatible strings that
-aren't upstreamed, add the vendor compatible.
-
-Signed-off-by: George Moussalem <[email protected]>
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -201,7 +201,7 @@
- };
-
- mdio0: mdio@88000 {
-- compatible = "qcom,ipq5018-mdio";
-+ compatible = "qcom,ipq5018-mdio", "qcom,ipq40xx-mdio";
- reg = <0x00088000 0x64>,
- <0x019475c4 0x4>;
- #address-cells = <1>;
diff --git a/target/linux/qualcommax/patches-6.12/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch b/target/linux/qualcommax/patches-6.12/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch
deleted file mode 100644
index c6225f62b3..0000000000
--- a/target/linux/qualcommax/patches-6.12/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From f71366e0530db2c5cecbbbb6edfbf7344bd6f83b Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:12 +0800
-Subject: [PATCH 1/2] clk: gcc-ipq5018: remove the unsupported clk
- combination for gmac
-
-Comment out the unsupported clock combination in the frequency table
-for GMAC1.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- drivers/clk/qcom/gcc-ipq5018.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq5018.c
-+++ b/drivers/clk/qcom/gcc-ipq5018.c
-@@ -678,7 +678,7 @@ static const struct freq_tbl ftbl_gmac1_
- F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
- F(24000000, P_XO, 1, 0, 0),
- F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
-- F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
-+ /* F(125000000, P_UNIPHY_RX, 2.5, 0, 0), */
- F(125000000, P_UNIPHY_RX, 1, 0, 0),
- F(312500000, P_UNIPHY_RX, 1, 0, 0),
- { }
-@@ -718,7 +718,7 @@ static const struct freq_tbl ftbl_gmac1_
- F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
- F(24000000, P_XO, 1, 0, 0),
- F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
-- F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
-+ /* F(125000000, P_UNIPHY_TX, 2.5, 0, 0), */
- F(125000000, P_UNIPHY_TX, 1, 0, 0),
- F(312500000, P_UNIPHY_TX, 1, 0, 0),
- { }
diff --git a/target/linux/qualcommax/patches-6.12/0722-clk-qcom-gcc-ipq5018-refer-to-uniphy-rx-and-tx-clk-providers-by-name.patch b/target/linux/qualcommax/patches-6.12/0722-clk-qcom-gcc-ipq5018-refer-to-uniphy-rx-and-tx-clk-providers-by-name.patch
deleted file mode 100644
index 6ecdee0161..0000000000
--- a/target/linux/qualcommax/patches-6.12/0722-clk-qcom-gcc-ipq5018-refer-to-uniphy-rx-and-tx-clk-providers-by-name.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:12 +0800
-Subject: [PATCH] clk: gcc-ipq5018: refer to UNIPHY rx and tx clk providers by name
-
-QCA-SSDK does not register the output clocks of the onboard uniphy so the
-GCC and DTS can't reference them by their index.
-The SSDK references them by name, so let's change the GCC driver
-accordingly.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq5018.c
-+++ b/drivers/clk/qcom/gcc-ipq5018.c
-@@ -368,8 +368,8 @@ static const struct parent_map gcc_xo_ge
-
- static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
- { .index = DT_XO },
-- { .index = DT_UNIPHY_RX_CLK },
-- { .index = DT_UNIPHY_TX_CLK },
-+ { .name = "uniphy_gcc_rx", .index = -1 },
-+ { .name = "uniphy_gcc_tx", .index = -1 },
- { .hw = &ubi32_pll.clkr.hw },
- { .hw = &gpll0.clkr.hw },
- };
-@@ -384,8 +384,8 @@ static const struct parent_map gcc_xo_un
-
- static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
- { .index = DT_XO },
-- { .index = DT_UNIPHY_TX_CLK },
-- { .index = DT_UNIPHY_RX_CLK },
-+ { .name = "uniphy_gcc_tx", .index = -1 },
-+ { .name = "uniphy_gcc_rx", .index = -1 },
- { .hw = &ubi32_pll.clkr.hw },
- { .hw = &gpll0.clkr.hw },
- };
diff --git a/target/linux/qualcommax/patches-6.12/0723-clk-qcom-gcc-ipq5018-fix-uniphy-soft-reset-issue.patch b/target/linux/qualcommax/patches-6.12/0723-clk-qcom-gcc-ipq5018-fix-uniphy-soft-reset-issue.patch
deleted file mode 100644
index f4d7742722..0000000000
--- a/target/linux/qualcommax/patches-6.12/0723-clk-qcom-gcc-ipq5018-fix-uniphy-soft-reset-issue.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Fri, 30 May 2025 09:12:23 +0400
-Subject: [PATCH] clk: qcom: gcc-ipq5018: fix UNIPHY soft reset issue
-
-The SOFT reset is supposed to trigger a resets across the SYS, RX, and
-TX lines of the IPQ5018 UNIPHY. So let's set the bitmask of the reset
-definition accordingly in the GCC as per the downstream driver.
-
-Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/036bdc62aca561e8ff94a29c447fc400de2b7304
-
-Signed-off-by: George Moussalem <[email protected]>
---- a/drivers/clk/qcom/gcc-ipq5018.c
-+++ b/drivers/clk/qcom/gcc-ipq5018.c
-@@ -3647,7 +3647,7 @@ static const struct qcom_reset_map gcc_i
- [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
- [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
- [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
-- [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
-+ [GCC_UNIPHY_SOFT_RESET] = {0x56104, .bitmask = 0x32 },
- [GCC_USB0_BCR] = { 0x3e070, 0 },
- [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
- [GCC_WCSS_BCR] = { 0x18000, 0 },
diff --git a/target/linux/qualcommax/patches-6.12/0814-remoteproc-qcom_q6v5_mpd-support-ipq5018.patch b/target/linux/qualcommax/patches-6.12/0814-remoteproc-qcom_q6v5_mpd-support-ipq5018.patch
deleted file mode 100644
index 9cdf59ad21..0000000000
--- a/target/linux/qualcommax/patches-6.12/0814-remoteproc-qcom_q6v5_mpd-support-ipq5018.patch
+++ /dev/null
@@ -1,111 +0,0 @@
-From 4ae334127f073aa5f7c9209c9f0a17fd9e331db1 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:12 +0800
-Subject: [PATCH] remoteproc: qcom_q6v5_mpd: support ipq5018
-
-Signed-off-by: Ziyang Huang <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_mpd.c | 37 +++++++++++++++++++++++++++---
- 1 file changed, 34 insertions(+), 3 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_mpd.c
-+++ b/drivers/remoteproc/qcom_q6v5_mpd.c
-@@ -156,6 +156,8 @@ static int q6_wcss_spawn_pd(struct rproc
- static int wcss_pd_start(struct rproc *rproc)
- {
- struct userpd *upd = rproc->priv;
-+ struct rproc *rpd_rproc = dev_get_drvdata(upd->dev->parent);
-+ struct q6_wcss *wcss = rpd_rproc->priv;
- u32 pasid = (upd->pd_asid << 8) | UPD_SWID;
- int ret;
-
-@@ -171,6 +173,14 @@ static int wcss_pd_start(struct rproc *r
- return ret;
- }
-
-+ if (upd->pd_asid == 1) {
-+ ret = qcom_scm_internal_wifi_powerup(wcss->desc->pasid);
-+ if (ret) {
-+ dev_err(upd->dev, "failed to power up internal radio\n");
-+ return ret;
-+ }
-+ }
-+
- return ret;
- }
-
-@@ -180,6 +190,12 @@ static int q6_wcss_stop(struct rproc *rp
- const struct wcss_data *desc = wcss->desc;
- int ret;
-
-+ ret = qcom_q6v5_request_stop(&wcss->q6, NULL);
-+ if (ret) {
-+ dev_err(wcss->dev, "pd not stopped\n");
-+ return ret;
-+ }
-+
- ret = qcom_scm_pas_shutdown(desc->pasid);
- if (ret) {
- dev_err(wcss->dev, "not able to shutdown\n");
-@@ -219,6 +235,7 @@ static int wcss_pd_stop(struct rproc *rp
- {
- struct userpd *upd = rproc->priv;
- struct rproc *rpd_rproc = dev_get_drvdata(upd->dev->parent);
-+ struct q6_wcss *wcss = rpd_rproc->priv;
- u32 pasid = (upd->pd_asid << 8) | UPD_SWID;
- int ret;
-
-@@ -230,6 +247,14 @@ static int wcss_pd_stop(struct rproc *rp
- }
- }
-
-+ if (upd->pd_asid == 1) {
-+ ret = qcom_scm_internal_wifi_shutdown(wcss->desc->pasid);
-+ if (ret) {
-+ dev_err(upd->dev, "failed to power down internal radio\n");
-+ return ret;
-+ }
-+ }
-+
- ret = qcom_scm_msa_unlock(pasid);
- if (ret) {
- dev_err(upd->dev, "failed to power down pd\n");
-@@ -431,15 +456,14 @@ static int wcss_pd_load(struct rproc *rp
- struct userpd *upd = rproc->priv;
- struct rproc *rpd_rproc = dev_get_drvdata(upd->dev->parent);
- struct q6_wcss *wcss = rpd_rproc->priv;
-- u32 pasid = (upd->pd_asid << 8) | UPD_SWID;
- int ret;
-
- ret = rproc_boot(rpd_rproc);
- if (ret)
- return ret;
-
-- return qcom_mdt_load(upd->dev, fw, rproc->firmware,
-- pasid, wcss->mem_region,
-+ return qcom_mdt_load_pd_seg(upd->dev, fw, rproc->firmware,
-+ wcss->desc->pasid, upd->pd_asid, wcss->mem_region,
- wcss->mem_phys, wcss->mem_size,
- NULL);
- }
-@@ -776,6 +800,12 @@ static void q6_wcss_remove(struct platfo
- rproc_free(rproc);
- }
-
-+static const struct wcss_data q6_ipq5018_res_init = {
-+ .pasid = MPD_WCNSS_PAS_ID,
-+ // .share_upd_info_to_q6 = true, /* Version 1 */
-+ // .mdt_load_sec = qcom_mdt_load_pd_seg,
-+};
-+
- static const struct wcss_data q6_ipq5332_res_init = {
- .pasid = MPD_WCNSS_PAS_ID,
- .share_upd_info_to_q6 = true,
-@@ -786,6 +816,7 @@ static const struct wcss_data q6_ipq9574
- };
-
- static const struct of_device_id q6_wcss_of_match[] = {
-+ { .compatible = "qcom,ipq5018-q6-mpd", .data = &q6_ipq5018_res_init },
- { .compatible = "qcom,ipq5332-q6-mpd", .data = &q6_ipq5332_res_init },
- { .compatible = "qcom,ipq9574-q6-mpd", .data = &q6_ipq9574_res_init },
- { },
diff --git a/target/linux/qualcommax/patches-6.12/0815-remoteproc-qcom_q6v5_mpd-add-support-for-passing-v1-bootargs.patch b/target/linux/qualcommax/patches-6.12/0815-remoteproc-qcom_q6v5_mpd-add-support-for-passing-v1-bootargs.patch
deleted file mode 100644
index f601377e47..0000000000
--- a/target/linux/qualcommax/patches-6.12/0815-remoteproc-qcom_q6v5_mpd-add-support-for-passing-v1-bootargs.patch
+++ /dev/null
@@ -1,163 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Mon, 09 Dec 2024 09:59:38 +0400
-Subject: [PATCH] remoteproc: qcom_q6v5_mpd: add support for passing v1 bootargs
-
-On multi-PD platforms such as IPQ5018, boot args are passed to the root PD
-run on the Q6 processor which in turn boots the user PDs for internal
-(IPQ5018) and external wifi radios (such as QCN6122). These boot args
-let the user PD process know details like what PCIE index, user PD ID, and
-reset GPIO is used. These are otherwise hardcoded in the firmware.
-
-Below is the structure expected of the version 1 boot args including the
-default values hardcoded in the firmware for IPQ5018:
-
-+------------+------+--------------+--------------+
-| Argument | type | def val UPD2 | def val UPD3 |
-+------------+------+--------------+--------------+
-| PCIE Index | u32 | 0x02 (PCIE1) | 0x01 (PCIE0) |
-| Length | u32 | 0x04 | 0x04 |
-| User PD ID | u32 | 0x02 | 0x03 |
-| Reset GPIO | u32 | 0x12 | 0x0f |
-| Reserved 1 | u32 | 0x00 | 0x00 |
-| Reserved 2 | u32 | 0x00 | 0x00 |
-+------------+------+--------------+--------------+
-
-On IPQ5018/QCN6122 boards, the default mapping is as follows:
-
- +-> UPD1 ----> IPQ5018 Internal 2.4G Radio
- /
- /
-Root PD +---> UPD2 ----> QCN6122 6G Radio on PCIE1 (if available)
- \
- \
- +-> UPD3 ----> QCN6102 5G Radio on PCIE0
-
-To support (future) boards with other mappings or control what UPD ID is
-used, let's add support for passing boot args for more flexibility.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/drivers/remoteproc/qcom_q6v5_mpd.c
-+++ b/drivers/remoteproc/qcom_q6v5_mpd.c
-@@ -43,7 +43,11 @@
- #define UPD_BOOT_INFO_SMEM_SIZE 4096
- #define UPD_BOOT_INFO_HEADER_TYPE 0x2
- #define UPD_BOOT_INFO_SMEM_ID 507
--#define VERSION2 2
-+
-+enum q6_bootargs_version {
-+ VERSION1 = 1,
-+ VERSION2,
-+};
-
- /**
- * struct userpd_boot_info_header - header of user pd bootinfo
-@@ -95,6 +99,7 @@ struct userpd {
- struct wcss_data {
- u32 pasid;
- bool share_upd_info_to_q6;
-+ u8 bootargs_version;
- };
-
- /**
-@@ -299,10 +304,13 @@ static void *q6_wcss_da_to_va(struct rpr
- static int share_upd_bootinfo_to_q6(struct rproc *rproc)
- {
- int i, ret;
-+ u32 rd_val;
- size_t size;
- u16 cnt = 0, version;
- void *ptr;
-+ u8 *bootargs_arr;
- struct q6_wcss *wcss = rproc->priv;
-+ struct device_node *np = wcss->dev->of_node;
- struct userpd *upd;
- struct userpd_boot_info upd_bootinfo = {0};
- const struct firmware *fw;
-@@ -324,10 +332,47 @@ static int share_upd_bootinfo_to_q6(stru
- }
-
- /*Version*/
-- version = VERSION2;
-+ version = (wcss->desc->bootargs_version) ? wcss->desc->bootargs_version : VERSION2;
- memcpy_toio(ptr, &version, sizeof(version));
- ptr += sizeof(version);
-
-+ cnt = ret = of_property_count_u32_elems(np, "boot-args");
-+ if (ret < 0) {
-+ if (ret == -ENODATA) {
-+ dev_err(wcss->dev, "failed to read boot args ret:%d\n", ret);
-+ return ret;
-+ }
-+ cnt = 0;
-+ }
-+
-+ /* No of elements */
-+ memcpy_toio(ptr, &cnt, sizeof(u16));
-+ ptr += sizeof(u16);
-+
-+ bootargs_arr = kzalloc(cnt, GFP_KERNEL);
-+ if (!bootargs_arr) {
-+ dev_err(wcss->dev, "failed to allocate memory\n");
-+ return PTR_ERR(bootargs_arr);
-+ }
-+
-+ for (i = 0; i < cnt; i++) {
-+ ret = of_property_read_u32_index(np, "boot-args", i, &rd_val);
-+ if (ret) {
-+ dev_err(wcss->dev, "failed to read boot args\n");
-+ kfree(bootargs_arr);
-+ return ret;
-+ }
-+ bootargs_arr[i] = (u8)rd_val;
-+ }
-+
-+ /* Copy bootargs */
-+ memcpy_toio(ptr, bootargs_arr, cnt);
-+ ptr += (cnt);
-+
-+ of_node_put(np);
-+ kfree(bootargs_arr);
-+ cnt = 0;
-+
- for (i = 0; i < ARRAY_SIZE(wcss->upd); i++)
- if (wcss->upd[i])
- cnt++;
-@@ -383,12 +428,14 @@ static int q6_wcss_load(struct rproc *rp
-
- /* Share user pd boot info to Q6 remote processor */
- if (desc->share_upd_info_to_q6) {
-- ret = share_upd_bootinfo_to_q6(rproc);
-- if (ret) {
-- dev_err(wcss->dev,
-- "user pd boot info sharing with q6 failed %d\n",
-- ret);
-- return ret;
-+ if (of_property_present(wcss->dev->of_node, "boot-args")) {
-+ ret = share_upd_bootinfo_to_q6(rproc);
-+ if (ret) {
-+ dev_err(wcss->dev,
-+ "user pd boot info sharing with q6 failed %d\n",
-+ ret);
-+ return ret;
-+ }
- }
- }
-
-@@ -802,13 +849,15 @@ static void q6_wcss_remove(struct platfo
-
- static const struct wcss_data q6_ipq5018_res_init = {
- .pasid = MPD_WCNSS_PAS_ID,
-- // .share_upd_info_to_q6 = true, /* Version 1 */
-+ .share_upd_info_to_q6 = true,
-+ .bootargs_version = VERSION1,
- // .mdt_load_sec = qcom_mdt_load_pd_seg,
- };
-
- static const struct wcss_data q6_ipq5332_res_init = {
- .pasid = MPD_WCNSS_PAS_ID,
- .share_upd_info_to_q6 = true,
-+ .bootargs_version = VERSION2,
- };
-
- static const struct wcss_data q6_ipq9574_res_init = {
diff --git a/target/linux/qualcommax/patches-6.12/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch b/target/linux/qualcommax/patches-6.12/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch
deleted file mode 100644
index d158688928..0000000000
--- a/target/linux/qualcommax/patches-6.12/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Wed, 27 Oct 2024 16:34:11 +0400
-Subject: [PATCH] arm64: dts: qcom: ipq5018: add wifi support
-
-The IPQ5018 SoC comes with an internal 2x2 2.4Ghz wifi radio.
-QCN6122 is a PCIe based wifi solution specific to the IPQ5018 platform which
-comes optinally packed with 1 or 2 QCN6122 chips or with an external
-PCIe based wifi solution (such as QCN9074) for 5/6 Ghz support.
-
-As such, add wifi nodes for both IPQ5018 and QCN6122.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -697,6 +697,225 @@
- };
- };
-
-+ wifi0: wifi@c000000 {
-+ compatible = "qcom,ipq5018-wifi";
-+ reg = <0xc000000 0x1000000>;
-+
-+ interrupts = <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 308 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 338 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>;
-+
-+ interrupt-names = "misc-pulse1",
-+ "misc-latch",
-+ "sw-exception",
-+ "watchdog",
-+ "ce0",
-+ "ce1",
-+ "ce2",
-+ "ce3",
-+ "ce4",
-+ "ce5",
-+ "ce6",
-+ "ce7",
-+ "ce8",
-+ "ce9",
-+ "ce10",
-+ "ce11",
-+ "host2wbm-desc-feed",
-+ "host2reo-re-injection",
-+ "host2reo-command",
-+ "host2rxdma-monitor-ring3",
-+ "host2rxdma-monitor-ring2",
-+ "host2rxdma-monitor-ring1",
-+ "reo2ost-exception",
-+ "wbm2host-rx-release",
-+ "reo2host-status",
-+ "reo2host-destination-ring4",
-+ "reo2host-destination-ring3",
-+ "reo2host-destination-ring2",
-+ "reo2host-destination-ring1",
-+ "rxdma2host-monitor-destination-mac3",
-+ "rxdma2host-monitor-destination-mac2",
-+ "rxdma2host-monitor-destination-mac1",
-+ "ppdu-end-interrupts-mac3",
-+ "ppdu-end-interrupts-mac2",
-+ "ppdu-end-interrupts-mac1",
-+ "rxdma2host-monitor-status-ring-mac3",
-+ "rxdma2host-monitor-status-ring-mac2",
-+ "rxdma2host-monitor-status-ring-mac1",
-+ "host2rxdma-host-buf-ring-mac3",
-+ "host2rxdma-host-buf-ring-mac2",
-+ "host2rxdma-host-buf-ring-mac1",
-+ "rxdma2host-destination-ring-mac3",
-+ "rxdma2host-destination-ring-mac2",
-+ "rxdma2host-destination-ring-mac1",
-+ "host2tcl-input-ring4",
-+ "host2tcl-input-ring3",
-+ "host2tcl-input-ring2",
-+ "host2tcl-input-ring1",
-+ "wbm2host-tx-completions-ring3",
-+ "wbm2host-tx-completions-ring2",
-+ "wbm2host-tx-completions-ring1",
-+ "tcl2host-status-ring";
-+
-+ status = "disabled";
-+ };
-+
-+ //QCN6102 5G
-+ wifi1: wifi1@c000000 {
-+ reg = <0x0b00a040 0x0>;
-+ compatible = "qcom,qcn6122-wifi";
-+ interrupts = <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 419 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 422 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 425 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
-+ status = "disabled";
-+ };
-+
-+ //QCN6122 5G/6G
-+ wifi2: wifi2@c000000 {
-+ reg = <0x0b00a040 0x0>;
-+ compatible = "qcom,qcn6122-wifi";
-+ interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 450 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 454 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 455 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 458 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
-+ status = "disabled";
-+ };
-+
-+ q6v5_wcss: remoteproc@cd00000 {
-+ compatible = "qcom,ipq5018-q6-mpd";
-+ reg = <0x0cd00000 0x4040>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_XO_CLK>,
-+ <&gcc GCC_SLEEP_CLK_SRC>,
-+ <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>;
-+
-+ interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
-+ <&wcss_smp2p_in 0 IRQ_TYPE_NONE>,
-+ <&wcss_smp2p_in 1 IRQ_TYPE_NONE>,
-+ <&wcss_smp2p_in 2 IRQ_TYPE_NONE>,
-+ <&wcss_smp2p_in 3 IRQ_TYPE_NONE>;
-+ interrupt-names = "wdog",
-+ "fatal",
-+ "ready",
-+ "handover",
-+ "stop-ack";
-+
-+ qcom,smem-states = <&wcss_smp2p_out 0>,
-+ <&wcss_smp2p_out 1>;
-+ qcom,smem-state-names = "shutdown",
-+ "stop";
-+
-+ status = "disabled";
-+
-+ glink-edge {
-+ interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
-+ label = "rtr";
-+ qcom,remote-pid = <1>;
-+ mboxes = <&apcs_glb 8>;
-+
-+ qrtr_requests {
-+ qcom,glink-channels = "IPCRTR";
-+ };
-+ };
-+ };
-+
-+ wcss: smp2p-wcss {
-+ compatible = "qcom,smp2p";
-+ qcom,smem = <435>, <428>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
-+
-+ mboxes = <&apcs_glb 9>;
-+
-+ qcom,local-pid = <0>;
-+ qcom,remote-pid = <1>;
-+
-+ wcss_smp2p_out: master-kernel {
-+ qcom,entry-name = "master-kernel";
-+ qcom,smp2p-feature-ssr-ack;
-+ #qcom,smem-state-cells = <1>;
-+ };
-+
-+ wcss_smp2p_in: slave-kernel {
-+ qcom,entry-name = "slave-kernel";
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+ };
-+
- pcie1: pcie@80000000 {
- compatible = "qcom,pcie-ipq5018";
- reg = <0x80000000 0xf1d>,
diff --git a/target/linux/qualcommax/patches-6.12/0817-arm64-dts-qcom-ipq5018-add-tz_apps-reserved-memory-region.patch b/target/linux/qualcommax/patches-6.12/0817-arm64-dts-qcom-ipq5018-add-tz_apps-reserved-memory-region.patch
deleted file mode 100644
index e2e63837a9..0000000000
--- a/target/linux/qualcommax/patches-6.12/0817-arm64-dts-qcom-ipq5018-add-tz_apps-reserved-memory-region.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Wed, 05 Feb 2025 12:12:47 +0400
-Subject: [PATCH] arm64: dts: qcom: ipq5018: add tz_apps reserved memory region
-
-Add tz_apps memory region needed for wifi to work.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -123,6 +123,11 @@
- #size-cells = <2>;
- ranges;
-
-+ tz_apps@4a400000 {
-+ reg = <0x0 0x4a400000 0x0 0x400000>;
-+ no-map;
-+ };
-+
- bootloader@4a800000 {
- reg = <0x0 0x4a800000 0x0 0x200000>;
- no-map;
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