FPGA Clock counter

hexseg.v

module hexseg(
  input clk,
	input [3:0] num,
	output [7:0] leds
);
	parameter brightness = 30;
	
	reg [7:0] cnt;
	always @(posedge clk) begin
		cnt = cnt + 1;
	end

	reg [7:0] pat;
	always @(num) begin
		case (num)
			4'h0:		pat = 8'b11000000;
			4'h1:		pat = 8'b11111001;
			4'h2:		pat = 8'b10100100;
			4'h3:		pat = 8'b10110000;
			4'h4:		pat = 8'b10011001;
			4'h5:		pat = 8'b10010010;
			4'h6:		pat = 8'b10000010;
			4'h7:		pat = 8'b11111000;
			4'h8:		pat = 8'b10000000;
			4'h9:		pat = 8'b10011000;
			4'ha:		pat = 8'b10001000;
			4'hb:		pat = 8'b10000011;
			4'hc:		pat = 8'b10100111;
			4'hd:		pat = 8'b10100001;
			4'he:		pat = 8'b10000110;
			4'hf:		pat = 8'b10001110;
			default:	pat = 8'b11111111;
		endcase
	end

	assign leds = (cnt < brightness) ? pat : 8'hff;

endmodule

ps2keyboard.v

module ps2keyboard(
  input clk, 
	input [9:0] sw, 
	input [2:0] btn, 
	output [9:0] led, 
	output [7:0] hled0, 
	output [7:0] hled1, 
	output [7:0] hled2, 
	output [7:0] hled3,
	input kclk,
	input kdat
);
	assign led[9:8]=2'h0;
	assign hled2=8'hff;
	assign hled3=8'hff;

	reg [7:0] dat;
	
	always @(negedge kclk)begin
		dat = dat + 1;
	end
	
	hexseg h0(clk, dat[3:0], hled0);
	hexseg h1(clk, dat[7:4], hled1);
	
	assign led[7:0] = dat;

endmodule