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source setup.sh
./scripts/generate_patch ++config config/mbj_singlebin.json
HistFitter.py -wtf -D "before,after,corrMatrix" -F bkg python/3b.py ++config config/mbj_singlebin.json patch0.json ++inputFiles /data/Bkg_21.2.18_mc16a.diboson.root /data/Bkg_21.2.18_mc16a.dijet.root /data/Bkg_21.2.18_mc16a.singletop.root /data/Bkg_21.2.18_mc16a.topEW.root /data/Bkg_21.2.18_mc16a.ttbar.root /data/Bkg_21.2.18_mc16a.W_jets.root /data/Bkg_21.2.18_mc16a.Z_jets.root /data/Data_21.2.18_20152016.root /data/Data_21.2.18_2017.root /data/Sig_21.2.18_mc16a.Gbb.root /data/Sig_21.2.18_mc16a.Gtb.root /data/Sig_21.2.18_mc16a.Gtt.root > logs/bkgfit_3b_tag21.2.18_79900_singlebin_Gbb_C.log
mv results/* /outresults/
python python/pullPlot.py ++config config/mbj_singlebin.json ++resultsDir /outresults ++outDir_plots /outplots/
HistFitter.py -wpl -F excl python/3b.py ++config config/mbj_singlebin.json patch0.json ++signalSample Gtt_2000_5000_200 ++inputFiles /data/Bkg_21.2.18_mc16a.diboson.root /data/Bkg_21.2.18_mc16a.dijet.root /data
@kratsg
kratsg / autolog.py
Created March 7, 2018 17:40 — forked from brendano/autolog.py
python decorators to log all method calls, show call graphs in realtime too
# Written by Brendan O'Connor, [email protected], www.anyall.org
# * Originally written Aug. 2005
# * Posted to gist.github.com/16173 on Oct. 2008
# Copyright (c) 2003-2006 Open Source Applications Foundation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
Xilinx Zynq MP First Stage Boot Loader
Release 2017.2 Dec 5 2017 - 15:52:54
Xilinx Zynq MP First Stage Boot Loader
Release 2017.2 Dec 5 2017 - 15:52:54
NOTICE: ATF running on XCZU19EG/silicon v3/RTL5.1 at 0xfffea000, with PMU firmware
NOTICE: BL31: Secure code at 0x0
NOTICE: BL31: Non secure code at 0x8000000
NOTICE: BL31: v1.3(release):7d1a673
NOTICE: BL31: Built : 14:42:17, Jan 3 2018
PMUFW: v0.3
Xilinx Zynq MP First Stage Boot Loader
Release 2016.4 Mar 21 2017 - 10:11:24
U-Boot 2016.07 (Mar 07 2017 - 14:06:33 -0600) Xilinx ZynqMP ZCU102 revB
I2C: ready
DRAM: 4 GiB
EL Level: EL3
MMC: sdhci@ff170000: 0