krupan · November 20, 2013 18:26
diff --git a/verilog internal exception b/verilog internal exception
 module top;
   int foo[16][byte];
   initial begin
      string bar = $psprintf("foo: %0d", foo[32]);
      $display(bar);
   end
 endmodule
	module top;
	int foo[16][byte];
	initial begin
	string bar = $psprintf("foo: %0d", foo[32]);
	$display(bar);
	end
	endmodule