Created
July 26, 2022 16:43
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Generic FF procedure
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library ieee; | |
use ieee.std_logic_1164.all; | |
package generic_ff_pack is | |
procedure FF | |
generic ( | |
type T) | |
parameter ( | |
signal q : out T; | |
constant d : in T; | |
constant INIT_VAL : in T; | |
constant rst : in std_logic; | |
signal clk : in std_logic; | |
constant en : in std_logic := '1'); | |
end package generic_ff_pack; | |
package body generic_ff_pack is | |
procedure FF | |
generic ( | |
type T) | |
parameter ( | |
signal q : out T; | |
constant d : in T; | |
constant INIT_VAL : in T; | |
constant rst : in std_logic; | |
signal clk : in std_logic; | |
constant en : in std_logic := '1') is | |
begin | |
if (rising_edge(clk)) then | |
if (rst /= '0') then | |
q <= INIT_VAL; | |
elsif (en = '1') then | |
q <= d; | |
end if; | |
end if; | |
end procedure FF; | |
end package body; |
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library ieee; | |
use ieee.std_logic_1164.all; | |
library generic_ff_lib; | |
use generic_ff_lib.generic_ff_pack.all; | |
entity generic_ff_tb is | |
port ( | |
clkIn : in std_logic; | |
rstIn : in std_logic; | |
enIn : in std_logic; | |
valIn : in std_logic_vector(7 downto 0); | |
valOut : out std_logic_vector(7 downto 0)); | |
end entity generic_ff_tb; | |
architecture behav of generic_ff_tb is | |
procedure ff_byte is new FF generic map (T => std_logic_vector(7 downto 0)); | |
constant INIT_VAL : std_logic_vector(7 downto 0) := (others=>'0'); | |
begin | |
ff_byte(valOut, valIn, INIT_VAL, rstIn, clkIn, enIn, '1'); | |
end architecture behav; |
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