wb_reg_jtag_access.sta.rpt

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                     ;
+---------------------------------------------------+-----------+----------+-----------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+
; Clock Name                                        ; Type      ; Period   ; Frequency ; Rise  ; Fall     ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source                                              ; Targets                                               ;
+---------------------------------------------------+-----------+----------+-----------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+
; altera_reserved_tck                               ; Base      ; 100.000  ; 10.0 MHz  ; 0.000 ; 50.000   ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { altera_reserved_tck }                               ;
; clk                                               ; Base      ; 20.000   ; 50.0 MHz  ; 0.000 ; 10.000   ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                     ; { CLOCK_50 }                                          ;
; inst1|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 5000.000 ; 0.2 MHz   ; 0.000 ; 2500.000 ; 50.00      ; 250       ; 1           ;       ;        ;           ;            ; false    ; clk    ; inst1|altpll_component|auto_generated|pll1|inclk[0] ; { inst1|altpll_component|auto_generated|pll1|clk[0] } ;
; inst1|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 100.000  ; 10.0 MHz  ; 0.000 ; 50.000   ; 50.00      ; 5         ; 1           ;       ;        ;           ;            ; false    ; clk    ; inst1|altpll_component|auto_generated|pll1|inclk[0] ; { inst1|altpll_component|auto_generated|pll1|clk[1] } ;
+---------------------------------------------------+-----------+----------+-----------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+-----------------------------------------------------+-------------------------------------------------------+