gistfile1.txt

oprofile: available events for CPU type "AMD64 processors"

CPU_CLK_UNHALTED: (counter: all)
        Cycles outside of halt state (min count: 3000)
RETIRED_INSTRUCTIONS: (counter: all)
        Retired instructions (includes exceptions, interrupts, re-syncs) (min count: 3000)
RETIRED_UOPS: (counter: all)
        Retired micro-ops (min count: 500)
INSTRUCTION_CACHE_FETCHES: (counter: all)
        Instruction cache fetches (RevE) (min count: 500)
INSTRUCTION_CACHE_MISSES: (counter: all)
        Instruction cache misses (min count: 500)
DATA_CACHE_ACCESSES: (counter: all)
        Data cache accesses (min count: 500)
DATA_CACHE_MISSES: (counter: all)
        Data cache misses (min count: 500)
DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM: (counter: all)
        Data cache refills from L2 or system (min count: 500)
        Unit masks (default 0x1e)
        ----------
        0x10: (M)odified cache state
        0x08: (O)wner cache state
        0x04: (E)xclusive cache state
        0x02: (S)hared cache state
        0x01: refill from system
        0x1e: All cache states except Invalid
DATA_CACHE_REFILLS_FROM_SYSTEM: (counter: all)
        Data cache refills from system (min count: 500)
        Unit masks (default 0x1f)
        ----------
        0x10: (M)odified cache state
        0x08: (O)wner cache state
        0x04: (E)xclusive cache state
        0x02: (S)hared cache state
        0x01: (I)nvalid cache state
        0x1f: All cache states
DATA_CACHE_LINES_EVICTED: (counter: all)
        Data cache lines evicted (min count: 500)
        Unit masks (default 0x1f)
        ----------
        0x10: (M)odified cache state
        0x08: (O)wner cache state
        0x04: (E)xclusive cache state
        0x02: (S)hared cache state
        0x01: (I)nvalid cache state
        0x1f: All cache states
RETIRED_BRANCH_INSTRUCTIONS: (counter: all)
        Retired branches (conditional, unconditional, exceptions, interrupts) (min count: 500)
RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS: (counter: all)
        Retired Mispredicted Branch Instructions (min count: 500)
RETIRED_TAKEN_BRANCH_INSTRUCTIONS: (counter: all)
        Retired taken branch instructions (min count: 500)
RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED: (counter: all)
        Retired taken branches mispredicted (min count: 500)
L1_DTLB_MISS_AND_L2_DTLB_HIT: (counter: all)
        L1 DTLB misses and L2 DTLB hits (min count: 500)
L1_DTLB_AND_L2_DTLB_MISS: (counter: all)
        L1 and L2 DTLB misses (min count: 500)
MISALIGNED_ACCESSES: (counter: all)
        Misaligned Accesses (min count: 500)
L1_ITLB_MISS_AND_L2_ITLB_HIT: (counter: all)
        L1 ITLB misses (and L2 ITLB hits) (min count: 500)
L1_ITLB_MISS_AND_L2_ITLB_MISS: (counter: all)
        L1 ITLB Miss, L2 ITLB Miss (min count: 500)
RETIRED_FAR_CONTROL_TRANSFERS: (counter: all)
        Retired far control transfers (min count: 500)
RETIRED_BRANCH_RESYNCS: (counter: all)
        Retired branches resyncs (only non-control transfer branches) (min count: 500)
INTERRUPTS_MASKED_CYCLES: (counter: all)
        Cycles with interrupts masked (IF=0) (min count: 500)
INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING: (counter: all)
        Cycles with interrupts masked while interrupt pending (min count: 500)
INTERRUPTS_TAKEN: (counter: all)
        Number of taken hardware interrupts (min count: 10)
DISPATCHED_FPU_OPS: (counter: all)
        Dispatched FPU ops (min count: 500)
        Unit masks (default 0x3f)
        ----------
        0x01: Add pipe ops
        0x02: Multiply pipe
        0x04: Store pipe ops
        0x08: Add pipe load ops
        0x10: Multiply pipe load ops
        0x20: Store pipe load ops
CYCLES_NO_FPU_OPS_RETIRED: (counter: all)
        Cycles with no FPU ops retired (min count: 500)
DISPATCHED_FPU_OPS_FAST_FLAG: (counter: all)
        Dispatched FPU ops that use the fast flag interface (min count: 500)
SEGMENT_REGISTER_LOADS: (counter: all)
        Segment register loads (min count: 500)
        Unit masks (default 0x7f)
        ----------
        0x01: ES register
        0x02: CS register
        0x04: SS register
        0x08: DS register
        0x10: FS register
        0x20: GS register
        0x40: HS register
PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE: (counter: all)
        Micro-architectural re-sync caused by self modifying code (min count: 500)
PIPELINE_RESTART_DUE_TO_PROBE_HIT: (counter: all)
        Micro-architectural re-sync caused by snoop (min count: 500)
LS_BUFFER_2_FULL_CYCLES: (counter: all)
        Cycles LS Buffer 2 Full (min count: 500)
LOCKED_OPS: (counter: all)
        Locked operations (min count: 500)
        Unit masks (default 0x4)
        ----------
        0x01: The number of locked instructions executed
        0x02: The number of cycles spent in speculative phase
        0x04: The number of cycles spent in non-speculative phase (including cache miss penalty)
OP_LATE_CANCEL: (counter: all)
        Micro-architectural late cancel of an operation (min count: 500)
RETIRED_CLFLUSH_INSTRUCTIONS: (counter: all)
        Retired CLFLUSH instructions (min count: 500)
RETIRED_CPUID_INSTRUCTIONS: (counter: all)
        Retired CPUID instructions (min count: 500)
MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS: (counter: all)
        Micro-architectural late cancel of an access (min count: 500)
MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS: (counter: all)
        Micro-architectural early cancel of an access (min count: 500)
SCRUBBER_SINGLE_BIT_ECC_ERRORS: (counter: all)
        One bit ECC error recorded by scrubber (min count: 500)
        Unit masks (default 0x3)
        ----------
        0x01: Scrubber error
        0x02: Piggyback scrubber errors
PREFETCH_INSTRUCTIONS_DISPATCHED: (counter: all)
        Prefetch Instructions Dispatched (min count: 500)
        Unit masks (default 0x7)
        ----------
        0x01: Load
        0x02: Store
        0x04: NTA
DCACHE_MISS_LOCKED_INSTRUCTIONS: (counter: all)
        DCACHE Misses by Locked Instructions (min count: 500)
        Unit masks (default 0x2)
        ----------
        0x02: Data Cache Misses by Locked Instructions
MEMORY_REQUESTS: (counter: all)
        Memory Requests by Type (min count: 500)
        Unit masks (default 0x83)
        ----------
        0x01: Requests to non-cacheable (UC) memory
        0x02: Requests to write-combining (WC) memory or WC buffer flushes to WB memory
        0x80: Streaming store (SS) requests
DATA_PREFETCHES: (counter: all)
        Data Prefetcher (min count: 500)
        Unit masks (default 0x3)
        ----------
        0x01: Cancelled prefetches
        0x02: Prefetch attempts
SYSTEM_READ_RESPONSES: (counter: all)
        System Read Responses by Coherency State (min count: 500)
        Unit masks (default 0x7)
        ----------
        0x01: Exclusive
        0x02: Modified
        0x04: Shared
QUADWORD_WRITE_TRANSFERS: (counter: all)
        Quadwords Written to System (min count: 500)
REQUESTS_TO_L2: (counter: all)
        Requests to L2 Cache (min count: 500)
        Unit masks (default 0x1f)
        ----------
        0x01: IC fill
        0x02: DC fill
        0x04: TLB reload
        0x08: Tag snoop request
        0x10: Canceled request
L2_CACHE_MISS: (counter: all)
        L2 Cache Misses (min count: 500)
        Unit masks (default 0x7)
        ----------
        0x01: IC fill
        0x02: DC fill
        0x04: TLB reload
L2_CACHE_FILL_WRITEBACK: (counter: all)
        L2 Fill/Writeback (min count: 500)
        Unit masks (default 0x3)
        ----------
        0x01: L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
        0x02: L2 Writebacks to system
INSTRUCTION_CACHE_REFILLS_FROM_L2: (counter: all)
        Instruction Cache Refills from L2 (min count: 500)
INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM: (counter: all)
        Instruction Cache Refills from System (min count: 500)
PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE: (counter: all)
        Pipeline Restart Due to Instruction Stream Probe (min count: 500)
INSTRUCTION_FETCH_STALL: (counter: all)
        Instruction fetch stall (min count: 500)
RETURN_STACK_HITS: (counter: all)
        Return stack hit (min count: 500)
RETURN_STACK_OVERFLOWS: (counter: all)
        Return stack overflow (min count: 500)
RETIRED_NEAR_RETURNS: (counter: all)
        Retired near returns (min count: 500)
RETIRED_NEAR_RETURNS_MISPREDICTED: (counter: all)
        Retired near returns mispredicted (min count: 500)
RETIRED_INDIRECT_BRANCHES_MISPREDICTED: (counter: all)
        Retired Indirect Branches Mispredicted (min count: 500)
RETIRED_MMX_FP_INSTRUCTIONS: (counter: all)
        Retired MMX/FP instructions (min count: 500)
        Unit masks (default 0xf)
        ----------
        0x01: x87 instructions
        0x02: Combined MMX & 3DNow instructions
        0x04: Combined packed SSE & SSE2 instructions
        0x08: Combined packed scalar SSE & SSE2 instructions
RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: (counter: all)
        Retired FastPath double-op instructions (min count: 500)
        Unit masks (default 0x7)
        ----------
        0x01: With low op in position 0
        0x02: With low op in position 1
        0x04: With low op in position 2
DECODER_EMPTY: (counter: all)
        Nothing to dispatch (decoder empty) (min count: 500)
DISPATCH_STALLS: (counter: all)
        Dispatch stalls (min count: 500)
DISPATCH_STALL_FOR_BRANCH_ABORT: (counter: all)
        Dispatch stall from branch abort to retire (min count: 500)
DISPATCH_STALL_FOR_SERIALIZATION: (counter: all)
        Dispatch stall for serialization (min count: 500)
DISPATCH_STALL_FOR_SEGMENT_LOAD: (counter: all)
        Dispatch stall for segment load (min count: 500)
DISPATCH_STALL_FOR_REORDER_BUFFER_FULL: (counter: all)
        Dispatch stall for reorder buffer full (min count: 500)
DISPATCH_STALL_FOR_RESERVATION_STATION_FULL: (counter: all)
        Dispatch stall when reservation stations are full (min count: 500)
DISPATCH_STALL_FOR_FPU_FULL: (counter: all)
        Dispatch stall when FPU is full (min count: 500)
DISPATCH_STALL_FOR_LS_FULL: (counter: all)
        Dispatch stall when LS is full (min count: 500)
DISPATCH_STALL_WAITING_FOR_ALL_QUIET: (counter: all)
        Dispatch stall when waiting for all to be quiet (min count: 500)
DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC: (counter: all)
        Dispatch Stall for Far Transfer or Resync to Retire (min count: 500)
FPU_EXCEPTIONS: (counter: all)
        FPU exceptions (min count: 1)
        Unit masks (default 0xf)
        ----------
        0x01: x87 reclass microfaults
        0x02: SSE retype microfaults
        0x04: SSE reclass microfaults
        0x08: SSE and x87 microtraps
DR0_BREAKPOINTS: (counter: all)
        Number of breakpoints for DR0 (min count: 1)
DR1_BREAKPOINTS: (counter: all)
        Number of breakpoints for DR1 (min count: 1)
DR2_BREAKPOINTS: (counter: all)
        Number of breakpoints for DR2 (min count: 1)
DR3_BREAKPOINTS: (counter: all)
        Number of breakpoints for DR3 (min count: 1)
DRAM_ACCESSES: (counter: all)
        DRAM Accesses (min count: 500)
        Unit masks (default 0x7)
        ----------
        0x01: Page hit
        0x02: Page miss
        0x04: Page conflict
MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS: (counter: all)
        Memory controller page table overflows (min count: 500)
MEMORY_CONTROLLER_TURNAROUNDS: (counter: all)
        Memory controller turnarounds (min count: 500)
        Unit masks (default 0x7)
        ----------
        0x01: DIMM (chip select) turnaround
        0x02: Read to write turnaround
        0x04: Write to read turnaround
MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION: (counter: all)
        Memory controller bypass saturation (min count: 500)
        Unit masks (default 0xf)
        ----------
        0x01: Memory controller high priority bypass
        0x02: Memory controller low priority bypass
        0x04: DRAM controller interface bypass
        0x08: DRAM controller queue bypass
THERMAL_STATUS_AND_DRAM_ECC_ERRORS: (counter: all)
        Thermal status and ECC errors (min count: 500)
        Unit masks (default 0x80)
        ----------
        0x01: Number of clocks CPU is active when HTC is active
        0x02: Number of clocks CPU clock is inactive when HTC is active