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leo60228/picosoc.json

Created September 7, 2021 13:48
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picosoc.json
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{
"creator": "Yosys 0.9+4052 (git sha1 687f381b69, gcc 10.3.0 -fPIC -Os)",
"modules": {
"$paramod$6b02c6e2b61a3396fb091bf3c2b7ebe66da395c1\\picorv32": {
"attributes": {
"dynports": "00000000000000000000000000000001",
"hdlname": "\\picorv32",
"src": "../picorv32.v:62.1-2162.10"
},
"parameter_default_values": {
"BARREL_SHIFTER": "0",
"CATCH_ILLINSN": "0",
"CATCH_MISALIGN": "0",
"COMPRESSED_ISA": "0",
"ENABLE_COUNTERS": "0",
"ENABLE_COUNTERS64": "1",
"ENABLE_DIV": "0",
"ENABLE_FAST_MUL": "0",
"ENABLE_IRQ": "0",
"ENABLE_IRQ_QREGS": "0",
"ENABLE_IRQ_TIMER": "1",
"ENABLE_MUL": "0",
"ENABLE_PCPI": "0",
"ENABLE_REGS_16_31": "0",
"ENABLE_REGS_DUALPORT": "0",
"ENABLE_TRACE": "0",
"LATCHED_IRQ": "11111111111111111111111111111111",
"LATCHED_MEM_RDATA": "0",
"MASKED_IRQ": "00000000000000000000000000000000",
"PROGADDR_IRQ": "00000000000000000000000000000000",
"PROGADDR_RESET": "00000000000100000000000000000000",
"REGS_INIT_ZERO": "0",
"STACKADDR": "00000000000000000000000010000000",
"TWO_CYCLE_ALU": "0",
"TWO_CYCLE_COMPARE": "0",
"TWO_STAGE_SHIFT": "0"
},
"ports": {
"clk": {
"direction": "input",
"bits": [ 2 ]
},
"resetn": {
"direction": "input",
"bits": [ 3 ]
},
"trap": {
"direction": "output",
"bits": [ 4 ]
},
"mem_valid": {
"direction": "output",
"bits": [ 5 ]
},
"mem_instr": {
"direction": "output",
"bits": [ 6 ]
},
"mem_ready": {
"direction": "input",
"bits": [ 7 ]
},
"mem_addr": {
"direction": "output",
"bits": [ "0", "0", 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 ]
},
"mem_wdata": {
"direction": "output",
"bits": [ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69 ]
},
"mem_wstrb": {
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"bits": [ 70, 71, 72, 73 ]
},
"mem_rdata": {
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"bits": [ 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105 ]
},
"mem_la_read": {
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},
"mem_la_write": {
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"bits": [ 107 ]
},
"mem_la_addr": {
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"bits": [ "0", "0", 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137 ]
},
"mem_la_wdata": {
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"bits": [ 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169 ]
},
"mem_la_wstrb": {
"direction": "output",
"bits": [ 170, 171, 172, 173 ]
},
"pcpi_valid": {
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"bits": [ "0" ]
},
"pcpi_insn": {
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"bits": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ]
},
"pcpi_rs1": {
"direction": "output",
"bits": [ 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205 ]
},
"pcpi_rs2": {
"direction": "output",
"bits": [ 138, 139, 140, 141, 142, 143, 144, 145, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229 ]
},
"pcpi_wr": {
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"pcpi_rd": {
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"bits": [ 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262 ]
},
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},
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"bits": [ 264 ]
},
"irq": {
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},
"eoi": {
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"bits": [ "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ]
},
"trace_valid": {
"direction": "output",
"bits": [ "0" ]
},
"trace_data": {
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