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use std::machines::binary::Binary;
use std::machines::range::Bit2;
use std::machines::range::Bit6;
use std::machines::range::Bit7;
use std::machines::range::Byte;
use std::machines::range::Byte2;
use std::machines::binary::ByteBinary;
use std::machines::split::ByteCompare;
use std::machines::shift::ByteShift;
use std::machines::shift::Shift;
use std::machines::split::split_gl::SplitGL;
let byte_binary = ByteBinary();
let binary = Binary(byte_binary);
let byte_shift = ByteShift();
let shift = Shift(byte_shift);
let byte2 = Byte2();
let mem = std::machines::memory::Memory(byte2);
let regs_mem = std::machines::memory::Memory(byte2);
let byte_compare = ByteCompare();
let split = SplitGL(byte_compare);
let bit2 = Bit2();
let bit6 = Bit6();
let bit7 = Bit7();
let main = Main(binary, shift, bit2, bit6, bit7, mem, regs_mem, split);
let p = proof(main);
machine Main(binary: Binary, shift: Shift, bit2: Bit2, bit6: Bit6, bit7: Bit7, mem: Memory, regs_mem: Memory, split: SplitGL) with degree: 262144 {
reg pc[@pc];
reg X[<=];
reg Y[<=];
reg Z[<=];
reg W[<=];
// Increased by 4 in each step, because we do up to 4 register memory accesses per step
col fixed STEP(i) { 4 * i };
// ============== memory instructions ==============
/// Loads one word from an address V = val(X) + Y, where V can be between 0 and 2**33 (sic!),
/// wraps the address to 32 bits and rounds it down to the next multiple of 4.
/// Writes the loaded word and the remainder of the division by 4 to registers Z and W,
/// respectively.
instr mload X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp3_col = memory.mload(X_b4 * 0x1000000 + X_b3 * 0x10000 + X_b2 * 0x100 + X_b1 * 4, STEP + 1)
link ~> regs.mstore(Z, STEP + 2, tmp3_col)
link ~> regs.mstore(W, STEP + 3, tmp4_col)
link => bit2.check(tmp4_col)
link => bit6.check(X_b1)
{
tmp1_col + Y = wrap_bit * 2**32 + X_b4 * 0x1000000 + X_b3 * 0x10000 + X_b2 * 0x100 + X_b1 * 4 + tmp4_col
}
// Stores val(W) at address (V = val(X) - val(Y) + Z) % 2**32.
// V can be between 0 and 2**33.
// V should be a multiple of 4, but this instruction does not enforce it.
instr mstore X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
link ~> tmp3_col = regs.mload(W, STEP + 2)
link ~> memory.mstore(X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000, STEP + 3, tmp3_col)
{
tmp1_col - tmp2_col + Z = (X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000) + wrap_bit * 2**32
}
// =============== Register memory =======================
// Get the value in register Y.
instr get_reg Y -> X link ~> X = regs.mload(Y, STEP);
// Set the value in register X to the value in register Y.
instr set_reg X, Y -> link ~> regs.mstore(X, STEP, Y);
// We still need these registers prover inputs.
reg query_arg_1;
reg query_arg_2;
// Witness columns used in instuctions for intermediate values inside instructions.
col witness tmp1_col;
col witness tmp2_col;
col witness tmp3_col;
col witness tmp4_col;
// We need to add these inline instead of using std::utils::is_zero
// because when XX is not constrained, witgen will try to set XX,
// XX_inv and XXIsZero to zero, which fails this constraint.
// Therefore, we have to activate constrained whenever XXIsZero is used.
// XXIsZero = 1 - XX * XX_inv
col witness XX, XX_inv, XXIsZero;
std::utils::force_bool(XXIsZero);
XXIsZero * XX = 0;
// ============== control-flow instructions ==============
// Load the value of label `l` into register X.
instr load_label X, l: label
link ~> regs.mstore(X, STEP, tmp1_col)
{
tmp1_col = l
}
// Jump to `l` and store the return program counter in register W.
instr jump l: label, W
link ~> regs.mstore(W, STEP, pc + 1)
{
pc' = l
}
// Jump to the address in register X and store the return program counter in register W.
instr jump_dyn X, W
link ~> pc' = regs.mload(X, STEP)
link ~> regs.mstore(W, STEP, pc + 1);
// Jump to `l` if val(X) - val(Y) is nonzero, where X and Y are register ids.
instr branch_if_diff_nonzero X, Y, l: label
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
{
XXIsZero = 1 - XX * XX_inv,
XX = tmp1_col - tmp2_col,
pc' = (1 - XXIsZero) * l + XXIsZero * (pc + 1)
}
// Jump to `l` if (val(X) - val(Y)) == Z, where X and Y are register ids and Z is a number.
instr branch_if_diff_equal X, Y, Z, l: label
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
{
XXIsZero = 1 - XX * XX_inv,
XX = tmp1_col - tmp2_col - Z,
pc' = XXIsZero * l + (1 - XXIsZero) * (pc + 1)
}
// Skips W instructions if val(X) - val(Y) + Z is zero, where X and Y are register ids and Z is a
// constant offset.
instr skip_if_equal X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
{
XXIsZero = 1 - XX * XX_inv,
XX = tmp1_col - tmp2_col + Z,
pc' = pc + 1 + (XXIsZero * W)
}
// Branches to `l` if V = val(X) - val(Y) - Z is positive, i.e. val(X) - val(Y) > Z,
// where X and Y are register ids and Z is a constant.
// V is required to be the difference of two 32-bit unsigned values.
// i.e. -2**32 < V < 2**32.
instr branch_if_diff_greater_than X, Y, Z, l: label
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
{
(tmp1_col - tmp2_col - Z) + 2**32 - 1 = X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000 + wrap_bit * 2**32,
pc' = wrap_bit * l + (1 - wrap_bit) * (pc + 1)
}
// Stores 1 in register W if V = val(X) - val(Y) - Z is positive,
// i.e. val(X) - val(Y) > Z, where X and Y are register ids and Z is a constant.
// V is required to be the difference of two 32-bit unsigend values.
// i.e. -2**32 < V < 2**32
instr is_diff_greater_than X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
link ~> regs.mstore(W, STEP + 2, wrap_bit)
{
(tmp1_col - tmp2_col - Z) + 2**32 - 1 = X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000 + wrap_bit * 2**32
}
// Stores val(X) * Z + W in register Y.
instr affine X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> regs.mstore(Y, STEP + 1, tmp1_col * Z + W);
// ================= wrapping instructions =================
// Computes V = val(X) + val(Y) + Z, wraps it in 32 bits, and stores the result in register W.
// Requires 0 <= V < 2**33.
instr add_wrap X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
link ~> regs.mstore(W, STEP + 2, tmp3_col)
{
tmp1_col + tmp2_col + Z = tmp3_col + wrap_bit * 2**32,
tmp3_col = X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000
}
// Computes V = val(X) - val(Y) + Z, wraps it in 32 bits, and stores the result in register W.
// Requires -2**32 <= V < 2**32.
instr sub_wrap_with_offset X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
link ~> regs.mstore(W, STEP + 2, tmp3_col)
{
(tmp1_col - tmp2_col + Z) + 2**32 = tmp3_col + wrap_bit * 2**32,
tmp3_col = X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000
}
// ================= logical instructions =================
// Stores 1 in register W if the value in register X is zero,
// otherwise stores 0.
instr is_equal_zero X, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> regs.mstore(W, STEP + 2, XXIsZero)
{
XXIsZero = 1 - XX * XX_inv,
XX = tmp1_col
}
// Stores 1 in register W if val(X) == val(Y), otherwise stores 0.
instr is_not_equal X, Y, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
link ~> regs.mstore(W, STEP + 2, tmp3_col)
{
XXIsZero = 1 - XX * XX_inv,
XX = tmp1_col - tmp2_col,
tmp3_col = 1 - XXIsZero
}
// ================= submachine instructions =================
instr and X, Y, Z, W link ~> tmp1_col = regs.mload(X, STEP) link ~> tmp2_col = regs.mload(Y, STEP + 1) link ~> tmp3_col = binary.and(tmp1_col, tmp2_col + Z) link ~> regs.mstore(W, STEP + 3, tmp3_col){ }
instr or X, Y, Z, W link ~> tmp1_col = regs.mload(X, STEP) link ~> tmp2_col = regs.mload(Y, STEP + 1) link ~> tmp3_col = binary.or(tmp1_col, tmp2_col + Z) link ~> regs.mstore(W, STEP + 3, tmp3_col){ }
instr xor X, Y, Z, W link ~> tmp1_col = regs.mload(X, STEP) link ~> tmp2_col = regs.mload(Y, STEP + 1) link ~> tmp3_col = binary.xor(tmp1_col, tmp2_col + Z) link ~> regs.mstore(W, STEP + 3, tmp3_col){ }
instr shl X, Y, Z, W link ~> tmp1_col = regs.mload(X, STEP) link ~> tmp2_col = regs.mload(Y, STEP + 1) link ~> tmp3_col = shift.shl(tmp1_col, tmp2_col + Z) link ~> regs.mstore(W, STEP + 3, tmp3_col){ }
instr shr X, Y, Z, W link ~> tmp1_col = regs.mload(X, STEP) link ~> tmp2_col = regs.mload(Y, STEP + 1) link ~> tmp3_col = shift.shr(tmp1_col, tmp2_col + Z) link ~> regs.mstore(W, STEP + 3, tmp3_col){ }
instr split_gl X, Z, W link ~> tmp1_col = regs.mload(X, STEP) link ~> (tmp3_col, tmp4_col) = split_gl.split(tmp1_col) link ~> regs.mstore(Z, STEP + 2, tmp3_col) link ~> regs.mstore(W, STEP + 3, tmp4_col){ }
col witness X_b1;
col witness X_b2;
col witness X_b3;
col witness X_b4;
link => byte.check(X_b1);
link => byte.check(X_b2);
link => byte.check(X_b3);
link => byte.check(X_b4);
col witness wrap_bit;
wrap_bit * (1 - wrap_bit) = 0;
// Sign extends the value in register X and stores it in register Y.
// Input is a 32 bit unsigned number. We check bit 7 and set all higher bits to that value.
instr sign_extend_byte X, Y
link ~> tmp1_col = regs.mload(X, STEP)
link ~> regs.mstore(Y, STEP + 3, tmp3_col)
{
// wrap_bit is used as sign_bit here.
tmp1_col = Y_7bit + wrap_bit * 0x80 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000,
tmp3_col = Y_7bit + wrap_bit * 0xffffff80
}
col witness Y_7bit;
link => bit7.check(Y_7bit);
// Sign extends the value in register X and stores it in register Y.
// Input is a 32 bit unsigned number. We check bit 15 and set all higher bits to that value.
instr sign_extend_16_bits X, Y
link ~> tmp1_col = regs.mload(X, STEP)
link ~> regs.mstore(Y, STEP + 3, tmp3_col)
{
Y_15bit = X_b1 + Y_7bit * 0x100,
// wrap_bit is used as sign_bit here.
tmp1_col = Y_15bit + wrap_bit * 0x8000 + X_b3 * 0x10000 + X_b4 * 0x1000000,
tmp3_col = Y_15bit + wrap_bit * 0xffff8000
}
col witness Y_15bit;
// Converts the value in register X to a signed number and stores it in register Y.
// Input is a 32 bit unsigned number (0 <= val(X) < 2**32) interpreted as a two's complement numbers.
// Returns a signed number (-2**31 <= val(Y) < 2**31).
instr to_signed X, Y
link ~> tmp1_col = regs.mload(X, STEP)
link ~> regs.mstore(Y, STEP + 1, tmp3_col)
{
// wrap_bit is used as sign_bit here.
tmp1_col = X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + Y_7bit * 0x1000000 + wrap_bit * 0x80000000,
tmp3_col = tmp1_col - wrap_bit * 0x100000000
}
// ======================= assertions =========================
instr fail { 1 = 0 }
// Wraps V = val(X) * Y and stores it in register Z,
// where X is a register and Y is a constant factor.
// Removes up to 16 bits beyond 32
// TODO is this really safe?
instr wrap16 X, Y, Z
link ~> tmp1_col = regs.mload(X, STEP)
link ~> regs.mstore(Z, STEP + 3, tmp3_col)
{
(tmp1_col * Y) = Y_b5 * 2**32 + Y_b6 * 2**40 + tmp3_col,
tmp3_col = X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000
}
col witness Y_b5;
col witness Y_b6;
col witness Y_b7;
col witness Y_b8;
link => byte.check(Y_b5);
link => byte.check(Y_b6);
link => byte.check(Y_b7);
link => byte.check(Y_b8);
col witness REM_b1;
col witness REM_b2;
col witness REM_b3;
col witness REM_b4;
link => byte.check(REM_b1);
link => byte.check(REM_b2);
link => byte.check(REM_b3);
link => byte.check(REM_b4);
// Computes Q = val(Y) / val(X) and R = val(Y) % val(X) and stores them in registers Z and W.
instr divremu Y, X, Z, W
link ~> tmp1_col = regs.mload(Y, STEP)
link ~> tmp2_col = regs.mload(X, STEP + 1)
link ~> regs.mstore(Z, STEP + 2, tmp3_col)
link ~> regs.mstore(W, STEP + 3, tmp4_col)
{
XXIsZero = 1 - XX * XX_inv,
XX = tmp2_col,
// if X is zero, remainder is set to dividend, as per RISC-V specification:
tmp2_col * tmp3_col + tmp4_col = tmp1_col,
// remainder >= 0:
tmp4_col = REM_b1 + REM_b2 * 0x100 + REM_b3 * 0x10000 + REM_b4 * 0x1000000,
// remainder < divisor, conditioned to val(X) not being 0:
(1 - XXIsZero) * (tmp2_col - tmp4_col - 1 - Y_b5 - Y_b6 * 0x100 - Y_b7 * 0x10000 - Y_b8 * 0x1000000) = 0,
// in case X is zero, we set quotient according to RISC-V specification
XXIsZero * (tmp3_col - 0xffffffff) = 0,
// quotient is 32 bits:
tmp3_col = X_b1 + X_b2 * 0x100 + X_b3 * 0x10000 + X_b4 * 0x1000000
}
// Computes V = val(X) * val(Y) and
// stores the lower 32 bits in register Z and the upper 32 bits in register W.
instr mul X, Y, Z, W
link ~> tmp1_col = regs.mload(X, STEP)
link ~> tmp2_col = regs.mload(Y, STEP + 1)
link ~> (tmp3_col, tmp4_col) = split_gl.split(tmp1_col * tmp2_col)
link ~> regs.mstore(Z, STEP + 2, tmp3_col)
link ~> regs.mstore(W, STEP + 3, tmp4_col);
let initial_memory: (fe, fe)[] = [
];
function main {
.debug file 1 "/home/leo/devel/powdr2/riscv/tests/riscv_data/trivial/src" "main.rs";
.debug file 2 "/home/leo/devel/powdr2/riscv-runtime/src" "lib.rs";
.debug file 3 "/home/leo/devel/powdr2/riscv-runtime/src" "allocator.rs";
.debug file 4 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/fmt" "mod.rs";
.debug file 5 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/char" "methods.rs";
.debug file 6 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src" "option.rs";
.debug file 7 "/home/leo/devel/powdr2/riscv-runtime/src" "fmt.rs";
.debug file 8 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/ptr" "non_null.rs";
.debug file 9 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/slice/iter" "macros.rs";
.debug file 10 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/iter/adapters" "copied.rs";
.debug file 11 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/str" "iter.rs";
.debug file 12 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/ptr" "mod.rs";
.debug file 13 "/home/leo/devel/powdr2/riscv-runtime/src" "arith.rs";
.debug file 14 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src" "result.rs";
.debug file 15 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num" "mod.rs";
.debug file 16 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src" "intrinsics.rs";
.debug file 17 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/array" "mod.rs";
.debug file 18 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/convert" "mod.rs";
.debug file 19 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num" "uint_macros.rs";
.debug file 20 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/slice" "mod.rs";
.debug file 21 "/home/leo/devel/powdr2/riscv-runtime/src" "ec.rs";
.debug file 22 "/home/leo/devel/powdr2/riscv-runtime/src" "hash.rs";
.debug file 23 "/home/leo/devel/powdr2/riscv-runtime/src" "io.rs";
.debug file 24 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/iter/adapters" "enumerate.rs";
.debug file 25 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src" "cell.rs";
.debug file 26 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/mem" "mod.rs";
.debug file 27 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/alloc" "global.rs";
.debug file 28 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src" "cmp.rs";
.debug file 29 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/alloc" "layout.rs";
.debug file 30 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/ptr" "alignment.rs";
.debug file 31 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num/flt2dec/strategy" "dragon.rs";
.debug file 32 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num/flt2dec/strategy" "grisu.rs";
.debug file 33 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/fmt" "num.rs";
.debug file 34 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/fmt" "rt.rs";
.debug file 35 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num/dec2flt" "table.rs";
.debug file 36 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/unicode" "unicode_data.rs";
.debug file 37 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/ptr" "mod.rs";
.debug file 38 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/ops" "function.rs";
.debug file 39 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num" "f32.rs";
.debug file 40 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/fmt" "mod.rs";
.debug file 41 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src" "panic.rs";
.debug file 42 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num" "f64.rs";
.debug file 43 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num/dec2flt" "decimal.rs";
.debug file 44 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/iter" "range.rs";
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.debug file 173 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/int" "mul.rs";
.debug file 174 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/int" "sdiv.rs";
.debug file 175 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/int" "udiv.rs";
.debug file 176 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/int" "shift.rs";
.debug file 177 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num" "f64.rs";
.debug file 178 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/../libm/src/math" "fmin.rs";
.debug file 179 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src" "math.rs";
.debug file 180 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/num" "f32.rs";
.debug file 181 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/../libm/src/math" "fminf.rs";
.debug file 182 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/../libm/src/math" "fmax.rs";
.debug file 183 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/../libm/src/math" "fmaxf.rs";
.debug file 184 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/../libm/src/math" "fmod.rs";
.debug file 185 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/../libm/src/math" "fmodf.rs";
.debug file 186 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/mem" "impls.rs";
.debug file 187 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/ptr" "mut_ptr.rs";
.debug file 188 "/home/leo/.rustup/toolchains/nightly-2024-02-01-x86_64-unknown-linux-gnu/lib/rustlib/src/rust/library/core/src/ptr" "const_ptr.rs";
.debug file 189 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src/mem" "mod.rs";
.debug file 190 "/home/leo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/compiler_builtins-0.1.105/src" "riscv.rs";
and 0, 0, 0, 0;
shl 0, 0, 0, 0;
split_gl 0, 0, 0;
jump __data_init, 1;
set_reg 0, 0;
jump __runtime_start, 1;
return;
__runtime_start:
set_reg 3, 268437784;
set_reg 2, 268435456;
jump main, 32;
main:
jump_dyn 1, 32;
// This is the data initialization routine.
__data_init:
set_reg 33, 0x464c457f;
set_reg 32, 0x10000000;
mstore 32, 0, 0, 33;
set_reg 33, 0x10101;
set_reg 32, 0x10000004;
mstore 32, 0, 0, 33;
set_reg 33, 0xf30002;
set_reg 32, 0x10000010;
mstore 32, 0, 0, 33;
set_reg 33, 0x1;
set_reg 32, 0x10000014;
mstore 32, 0, 0, 33;
set_reg 33, 0x10000118;
set_reg 32, 0x10000018;
mstore 32, 0, 0, 33;
set_reg 33, 0x34;
set_reg 32, 0x1000001c;
mstore 32, 0, 0, 33;
set_reg 33, 0x449cf0;
set_reg 32, 0x10000020;
mstore 32, 0, 0, 33;
set_reg 33, 0x1;
set_reg 32, 0x10000024;
mstore 32, 0, 0, 33;
set_reg 33, 0x200034;
set_reg 32, 0x10000028;
mstore 32, 0, 0, 33;
set_reg 33, 0x280005;
set_reg 32, 0x1000002c;
mstore 32, 0, 0, 33;
set_reg 33, 0x170019;
set_reg 32, 0x10000030;
mstore 32, 0, 0, 33;
set_reg 33, 0x6;
set_reg 32, 0x10000034;
mstore 32, 0, 0, 33;
set_reg 33, 0x34;
set_reg 32, 0x10000038;
mstore 32, 0, 0, 33;
set_reg 33, 0x10000034;
set_reg 32, 0x1000003c;
mstore 32, 0, 0, 33;
set_reg 33, 0x10000034;
set_reg 32, 0x10000040;
mstore 32, 0, 0, 33;
set_reg 33, 0xa0;
set_reg 32, 0x10000044;
mstore 32, 0, 0, 33;
set_reg 33, 0xa0;
set_reg 32, 0x10000048;
mstore 32, 0, 0, 33;
set_reg 33, 0x4;
set_reg 32, 0x1000004c;
mstore 32, 0, 0, 33;
set_reg 33, 0x4;
set_reg 32, 0x10000050;
mstore 32, 0, 0, 33;
set_reg 33, 0x1;
set_reg 32, 0x10000054;
mstore 32, 0, 0, 33;
set_reg 33, 0x10000000;
set_reg 32, 0x1000005c;
mstore 32, 0, 0, 33;
set_reg 33, 0x10000000;
set_reg 32, 0x10000060;
mstore 32, 0, 0, 33;
set_reg 33, 0x118;
set_reg 32, 0x10000064;
mstore 32, 0, 0, 33;
set_reg 33, 0x118;
set_reg 32, 0x10000068;
mstore 32, 0, 0, 33;
set_reg 33, 0x4;
set_reg 32, 0x1000006c;
mstore 32, 0, 0, 33;
set_reg 33, 0x1000;
set_reg 32, 0x10000070;
mstore 32, 0, 0, 33;
set_reg 33, 0x1;
set_reg 32, 0x10000074;
mstore 32, 0, 0, 33;
set_reg 33, 0x118;
set_reg 32, 0x10000078;
mstore 32, 0, 0, 33;
set_reg 33, 0x10000118;
set_reg 32, 0x1000007c;
mstore 32, 0, 0, 33;
set_reg 33, 0x10000118;
set_reg 32, 0x10000080;
mstore 32, 0, 0, 33;
set_reg 33, 0x1a;
set_reg 32, 0x10000084;
mstore 32, 0, 0, 33;
set_reg 33, 0x1a;
set_reg 32, 0x10000088;
mstore 32, 0, 0, 33;
set_reg 33, 0x5;
set_reg 32, 0x1000008c;
mstore 32, 0, 0, 33;
set_reg 33, 0x1000;
set_reg 32, 0x10000090;
mstore 32, 0, 0, 33;
set_reg 33, 0x6474e551;
set_reg 32, 0x10000094;
mstore 32, 0, 0, 33;
set_reg 33, 0x6;
set_reg 32, 0x100000ac;
mstore 32, 0, 0, 33;
set_reg 33, 0x70000003;
set_reg 32, 0x100000b4;
mstore 32, 0, 0, 33;
set_reg 33, 0x17e754;
set_reg 32, 0x100000b8;
mstore 32, 0, 0, 33;
set_reg 33, 0x2b;
set_reg 32, 0x100000c4;
mstore 32, 0, 0, 33;
set_reg 33, 0x2b;
set_reg 32, 0x100000c8;
mstore 32, 0, 0, 33;
set_reg 33, 0x4;
set_reg 32, 0x100000cc;
mstore 32, 0, 0, 33;
set_reg 33, 0x1;
set_reg 32, 0x100000d0;
mstore 32, 0, 0, 33;
set_reg 33, 0x10;
set_reg 32, 0x10000100;
mstore 32, 0, 0, 33;
set_reg 33, 0x527a01;
set_reg 32, 0x10000108;
mstore 32, 0, 0, 33;
set_reg 33, 0x1017c01;
set_reg 32, 0x1000010c;
mstore 32, 0, 0, 33;
set_reg 33, 0x20c1b;
set_reg 32, 0x10000110;
mstore 32, 0, 0, 33;
// This is the end of the data initialization routine.
jump_dyn 1, 32;
// ecall handler
__ecall_handler:
branch_if_diff_equal 5, 0, 0, __ecall_handler_input;
branch_if_diff_equal 5, 0, 1, __ecall_handler_data_identifier;
branch_if_diff_equal 5, 0, 2, __ecall_handler_output;
__invalid_syscall:
fail;
__ecall_handler_input:
query_arg_1 <== get_reg(10);
set_reg 10, ${ std::prover::Query::Input(std::convert::int(std::prover::eval(query_arg_1))) };
jump_dyn 1, 32;
__ecall_handler_data_identifier:
query_arg_1 <== get_reg(10);
query_arg_2 <== get_reg(11);
set_reg 10, ${ std::prover::Query::DataIdentifier(std::convert::int(std::prover::eval(query_arg_2)), std::convert::int(std::prover::eval(query_arg_1))) };
jump_dyn 1, 32;
__ecall_handler_output:
query_arg_1 <== get_reg(10);
query_arg_2 <== get_reg(11);
set_reg 0, ${ std::prover::Query::Output(std::convert::int(std::prover::eval(query_arg_1)), std::convert::int(std::prover::eval(query_arg_2))) };
jump_dyn 1, 32;
// end of ecall handler
}
}
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