Rust pattern matching with enum equals nice FSM

fsm.example.rs

match (self.state, level, diff_len) {
            (INIT, HIGH, ZERO) => {  
                if DBG_PRINT {println!("    First LEFT part of '1' outbit");}
                self.state = HIGH_LEVEL(ZERO, LEFT); // maybe should be ZERO from diff_len?
            }
            (INIT, HIGH, SINGLE) => {
                if DBG_PRINT {println!("    Second RIGHT part of '0' outbit");}
                self.add_bit_to_response(0);
                self.state = HIGH_LEVEL(SINGLE, RIGHT);
            }
            (HIGH_LEVEL(ZERO | SINGLE, LEFT), LOW, SINGLE) => { 
                if DBG_PRINT {println!("    Second RIGHT part of '1' outbit");}
                self.add_bit_to_response(1);
                self.state = LOW_LEVEL(SINGLE, RIGHT);
            }
            (LOW_LEVEL(SINGLE | DOUBLE, RIGHT), HIGH, SINGLE) => {
                if DBG_PRINT {println!("    First LEFT part of '1' out bit, continuing from previous 1 outbit");}
                self.state = HIGH_LEVEL(SINGLE, LEFT);
            }
            (LOW_LEVEL(SINGLE | DOUBLE, RIGHT), HIGH, DOUBLE) => {
                if DBG_PRINT {println!("    Second RIGHT part of '0' out bit, switching from previous 1 outbit");}
                self.add_bit_to_response(0);
                self.state = HIGH_LEVEL(DOUBLE, RIGHT);
            }
            (HIGH_LEVEL(DOUBLE | SINGLE, RIGHT), LOW, SINGLE) => {
                if DBG_PRINT {println!("    First LEFT part of '0' out bit, switching from previous 1 outbit or continuing from previous 0 outbit");}
                self.state = LOW_LEVEL(SINGLE, LEFT);
            }
            (LOW_LEVEL(SINGLE, LEFT), HIGH, SINGLE) => {
                if DBG_PRINT {println!("    First LEFT part of '0' out bit, continuing from previous 0 outbit");}
                self.add_bit_to_response(0);
                self.state = HIGH_LEVEL(SINGLE, RIGHT)
            }
            (HIGH_LEVEL(SINGLE | DOUBLE, RIGHT), LOW, DOUBLE) => {
                if DBG_PRINT {println!("    Second RIGHT part of '1' out bit, switching from previous 0 outbit");}
                self.add_bit_to_response(1);
                self.state = LOW_LEVEL(DOUBLE, RIGHT); // replace with SINGLE ? 
            }

            // (HIGH_LEVEL(_, _), HIGH, _) => unimplemented!(),
            // (LOW_LEVEL(_, _),  LOW,  _) => unimplemented!(),
            // (_, _, ZERO) => unimplemented!(),
            // (INIT, _, _) => unimplemented!(),

            // trying to cover impossible cases adviesd from rustc:
            // (HIGH_LEVEL(ZERO, _), _, _) => unimplemented!(),


            // @TODO: implement FAILED state
            _ => todo!("Line change state is not implemented: {:?}, {:?}, {:?}, {:?} {:?}", self.state, level, diff_len, diff, time),
        }