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lptr / rules.txt
Created March 2, 2026 13:26 — forked from darkxst/rules.txt
KiCad DRC rules for JLCPCB, 2 & 4-layer PCB
(version 1)
#Kicad 7
# 2-layer, 1oz copper
(rule "Minimum Trace Width (outer layer)"
(constraint track_width (min 5mil))
(layer outer)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (outer layer)"
diff --git a/build.gradle b/build.gradle
index 000d73a..72a2730 100644
--- a/build.gradle
+++ b/build.gradle
@@ -35,7 +35,7 @@ def schemaDir = "$buildDir/schema"
def rootBuild = "${rootProject.projectDir}/build"
def finalSandboxDir = "${rootBuild}/cabal-sandbox"
def rawSandboxDir = "${rootBuild}/raw-cabal-sandbox"
-def sandboxConfig = "${rootBuild}/cabal.sandbox.config"
+def sandboxConfig = "${projectDir}/cabal.sandbox.config"