https://github.com/tgingold/ghdl
https://ghdl.readthedocs.io/en/latest/index.html
sudo apt-get gnat gtkwave
cd ~/other
git clone https://github.com/tgingold/ghdl.git
mkdir build_ghdl
cd build_ghdl
../ghdl/configure --prefix=$HOME/other/install
make
make install
Is it possible to run a compile vhdl executable interactively, single step it and send dynamically defined input vectors?
How hard would it be to add that sort of feature if it doesn't yet exist- does it require a deep dive into the ada code or relatively shallow adjustment of the way the code loads a test vector?
One way to add it externally (though perhaps with sub-par speed) would be to write a program that would translat external input into a test bench file, compile it, and run it, the translate the results out into the desired format (e.g. a live wave form viewer, perhaps a ros pub). Previous state (like the contents of ram) would have to be saved from the previous step) then included with the newly generated test bench.
What would it take to parse some subset of vhdl in C++ from scratch?
https://www.fpgarelated.com/showarticle/20.php
Has some answers for verilog -> verilator Source available? Yes: https://www.veripool.org/projects/verilator/wiki/Installing http://git.veripool.org/git/verilator (license?)
6502
https://opencores.org/project,lattice6502
Tons of 6502 vhdl projects, no one main one.
Ought to make a ghdl only one.
http://www.visual6502.org/
Only the javascript sim is available?
Where is the netlist?
"We'll soon post source code packages and images for our chip simulations: the MOS 6502 and Atari 10444D 'TIA'. Source code will be for Python 2.6 and JavaScript. We plan to develop simulations in C++ and CUDA."
How long ago was that written?
https://github.com/mist64/perfect6502
"perfect6502 is a MOS 6502 CPU emulator that performs a simulation of the original NMOS 6502 netlist that was extracted by the visual6502.org project."