Input 1 | Input 2 | AND Logic Gate | Output |
---|---|---|---|
0 | 0 | =>AND-> |
0 |
0 | 1 | =>AND-> |
0 |
1 | 0 | =>AND-> |
0 |
1 | 1 | =>AND-> |
1 |
Last active
August 17, 2019 19:10
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