A Verilog implementation of a finite state machine to determine the modulus of any number by three, in realtime. The number can be input in most significant bit (MSB) first or least significant bit (LSB) first order. The msb_modulus and lsb_modulus modules return the modulus of the number as the number is entered. Uses only and, or, not, xor, a…

modulo3.v

/*
    A Verilog implementation of a finite state machine to determine the 
    modulus of any number by three, in realtime.

    The number can be input in most significant bit (MSB) first or least 
    significant bit (LSB) first order. The msb_modulus and lsb_modulus 
    modules return the modulus of the number as the number is entered.

    Uses only and, or, not, xor, and nand gates. Also uses a clock to 
    coordinate the modules.
    
 */

module jk (clk, reset, j, k, q, qbar);

    input clk, reset, j, k;
    output q, qbar;
    reg q, qbar, next;

    initial
        q=0;

    always @ (posedge clk) begin

        if (reset)
            next = 0;
        else if (j == 0 && k == 0)
            next = q;
        else if (j == 0 && k == 1'b1)
            next = 0;
        else if (j == 1 && k == 0)
            next = 1;
        else
            next = ~q;

        assign q = next;
        assign qbar = ~q;

        //$display ("time=%g clk=%b reset=%b j=%b k=%b q=%b qbar=%b", $time, clk, reset, j, k, q, qbar);

    end

endmodule

module msb_modulus(clk, x, z1, z0);

    input clk, x;
    output z1, z0;
    reg z1, z0;

    // FLIP FLOP 1
    reg reset1, j1, k1;
    wire q1, qbar1;
    jk FF1 (
        .clk (clk),
        .reset (reset1),
        .j (j1),
        .k (k1),
        .q ( q1 ),
        .qbar (qbar1)
    );
    initial begin
        reset1 = 0;
        j1 = 0;
        k1 = 0;
    end

    // FLIP FLOP 0
    reg reset0, j0, k0;
    wire q0, qbar0;
    jk FF0 (
        .clk (clk),
        .reset (reset0),
        .j (j0),
        .k (k0),
        .q ( q0 ),
        .qbar (qbar0)
    );
    initial begin
        reset0 = 0;
        j0 = 0;
        k0 = 0;
    end

    always @ (posedge clk) begin

        j1 = q0 && !x;
        k1 = !x;
        j0 = (!q1 && x) || (q1 && !x);
        k0 = 1;

        z0 = (!q1 && !q0 && x) || (q1 && !q0 && !x);
        #1 z1 = (!q1 && q0 && !x) || (q1 && !q0 && x);

        //#0 $display ("%d, x=%b, q=%b%b, z=%b%b", $time, x, q1, q0, z1, z0);
    end

endmodule


module lsb_modulus(clk, x, z1, z0);

    input clk, x;
    output z1, z0;
    reg z1, z0;

    // FLIP FLOP 2
    reg reset2, j2, k2;
    wire q2, qbar2;
    jk FF2 (
        .clk (clk),
        .reset (reset2),
        .j (j2),
        .k (k2),
        .q ( q2 ),
        .qbar (qbar2)
    );
    initial begin
        reset2 = 0;
        j2 = 0;
        k2 = 0;
    end

    // FLIP FLOP 1
    reg reset1, j1, k1;
    wire q1, qbar1;
    jk FF1 (
        .clk (clk),
        .reset (reset1),
        .j (j1),
        .k (k1),
        .q ( q1 ),
        .qbar (qbar1)
    );
    initial begin
        reset1 = 0;
        j1 = 0;
        k1 = 0;
    end

    // FLIP FLOP 0
    reg reset0, j0, k0;
    wire q0, qbar0;
    jk FF0 (
        .clk (clk),
        .reset (reset0),
        .j (j0),
        .k (k0),
        .q ( q0 ),
        .qbar (qbar0)
    );
    initial begin
        reset0 = 0;
        j0 = 0;
        k0 = 0;
    end

    always @ (posedge clk) begin

        //j2 = (!q2 && !x) || (!q2 && q1);
        j2 = !x || q1;
        //k2 = (q2 && !q1 && !q0) || (q2 && !x);
        k2 = (!q2 && !q0) || (!x);
        j1 = q2 && x;
        k1 = x;
        //j0 = (!q2 && !q1 && x) || (!q2 && !q1 && x);
        j0 = (!q2 && !q1 && x) || (q2 && q1 && x);
        k0 = x;

        #1 z1 = (q1 && !x) || (q2 && !q1 && x);
        #1 z0 = (!q2 && !q1 && !q0 && x) || (q2 && q1 && x) || (q0 & !x);

        //#0 $display ("%g, x=%b, q=%b%b%b, z=%b%b", $time, x, q2, q1, q0, z1, z0);
    end

endmodule

// a test bench to display the 
module lsb_testbench;

    reg clk, xA, xB, xC;
    wire zA1, zA0, zB1, zB0, zC1, zC0;

    initial begin
        clk = 0;
        xA = 0;
        xB = 0;
        xC = 0;
    end
    // 10011010011
    msb_modulus binaryA (
        .clk ( clk ),
        .x ( xA ),
        .z1 ( zA1 ),
        .z0 ( zA0 )
    );
    // 00111100100
    msb_modulus binaryB (
        .clk ( clk ),
        .x ( xB ),
        .z1 ( zB1 ),
        .z0 ( zB0 )
    );
    // 11010101110
    msb_modulus binaryC (
        .clk ( clk ),
        .x ( xC ),
        .z1 ( zC1 ),
        .z0 ( zC0 )
    );
    initial begin

        #05 assign xA = 1;
        #10 assign xA = 0;
        #10 assign xA = 0;
        #10 assign xA = 1;
        #10 assign xA = 1;
        #10 assign xA = 0;
        #10 assign xA = 1;
        #10 assign xA = 0;
        #10 assign xA = 0;
        #10 assign xA = 1;
        #10 assign xA = 1;

        #01 $display ("MSB: The modulus using input sequence 10011010011 is: %b", zA1, zA0);

        $finish;
    end


    initial begin

        #05 assign xB = 0;
        #10 assign xB = 0;
        #10 assign xB = 1;
        #10 assign xB = 1;
        #10 assign xB = 1;
        #10 assign xB = 1;
        #10 assign xB = 0;
        #10 assign xB = 0;
        #10 assign xB = 1;
        #10 assign xB = 0;
        #10 assign xB = 0;

        #01 $display ("MSB: The modulus using input sequence 00111100100 is: %b", zB1, zB0);

        $finish;
    end

    initial begin

        #05 assign xC = 1;
        #10 assign xC = 1;
        #10 assign xC = 0;
        #10 assign xC = 1;
        #10 assign xC = 0;
        #10 assign xC = 1;
        #10 assign xC = 0;
        #10 assign xC = 1;
        #10 assign xC = 1;
        #10 assign xC = 1;
        #10 assign xC = 0;

        #01 $display ("MSB: The modulus using input sequence 11010101110 is: %b", zC1, zC0);

        $finish;
    end

    always #5 clk = !clk;


endmodule


module msb_testbench;

    reg clk, xA, xB, xC;
    wire zA1, zA0, zB1, zB0, zC1, zC0;

    initial begin
        clk = 0;
        xA = 0;
        xB = 0;
        xC = 0;
    end

    // 10011010011
    lsb_modulus binaryA (
        .clk ( clk ),
        .x ( xA ),
        .z1 ( zA1 ),
        .z0 ( zA0 )
    );
    // 00111100100
    lsb_modulus binaryB (
        .clk ( clk ),
        .x ( xB ),
        .z1 ( zB1 ),
        .z0 ( zB0 )
    );
    // 11010101110
    lsb_modulus binaryC (
        .clk ( clk ),
        .x ( xC ),
        .z1 ( zC1 ),
        .z0 ( zC0 )
    );

    initial begin

        #05 assign xA = 1;
        #10 assign xA = 0;
        #10 assign xA = 0;
        #10 assign xA = 1;
        #10 assign xA = 1;
        #10 assign xA = 0;
        #10 assign xA = 1;
        #10 assign xA = 0;
        #10 assign xA = 0;
        #10 assign xA = 1;
        #10 assign xA = 1;

        #01 $display ("LSB: The modulus using input sequence 10011010011 is: %b", zA1, zA0);

        $finish;
    end


    initial begin

        #05 assign xB = 0;
        #10 assign xB = 0;
        #10 assign xB = 1;
        #10 assign xB = 1;
        #10 assign xB = 1;
        #10 assign xB = 1;
        #10 assign xB = 0;
        #10 assign xB = 0;
        #10 assign xB = 1;
        #10 assign xB = 0;
        #10 assign xB = 0;

        #01 $display ("LSB: The modulus using input sequence 00111100100 is: %b", zB1, zB0);

        $finish;
    end


    initial begin

        #05 assign xC = 1;
        #10 assign xC = 1;
        #10 assign xC = 0;
        #10 assign xC = 1;
        #10 assign xC = 0;
        #10 assign xC = 1;
        #10 assign xC = 0;
        #10 assign xC = 1;
        #10 assign xC = 1;
        #10 assign xC = 1;
        #10 assign xC = 0;

        #01 $display ("LSB: The modulus using input sequence 11010101110 is: %b", zC1, zC0);

        $finish;
    end

    always #5 clk = !clk;


endmodule