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lwerdna/compilable_arm_il.cpp

Created August 21, 2019 04:32
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compilable low level il (LLIL) from Binary Ninja
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compilable_arm_il.cpp
// tests.o: ELF 32-bit LSB relocatable, ARM, EABI5 version 1 (SYSV), with debug_info, not stripped
#include <stdint.h>
#include <string>
#include <vector>
#include <map>
using namespace std;
#include "runtime.h"
extern map<REGTYPE,REGTYPE> vm_mem;
/* int32_t multiply(int32_t arg1, int32_t arg2) */
void multiply(void)
{
loc_0:
SET_REG("sp", SUB(REG("sp"), 4));
STORE(REG("sp"), REG("r11"));
SET_REG("r11", REG("sp"));
SET_REG("sp", SUB(REG("sp"), 12));
STORE(SUB(REG("r11"), 8), REG("r0"));
STORE(SUB(REG("r11"), 12), REG("r1"));
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r2", LOAD(SUB(REG("r11"), 12)));
SET_REG("r3", MUL(REG("r2"), REG("r3")));
SET_REG("r0", REG("r3"));
SET_REG("sp", REG("r11"));
SET_REG("r11", LOAD(REG("sp")));
SET_REG("sp", ADD(REG("sp"), 4));
// jump(lr)
return;
}
/* int32_t multiply_loop(int32_t arg1, int32_t arg2) */
void multiply_loop(void)
{
loc_0:
SET_REG("sp", SUB(REG("sp"), 4));
STORE(REG("sp"), REG("r11"));
SET_REG("r11", REG("sp"));
SET_REG("sp", SUB(REG("sp"), 20));
STORE(SUB(REG("r11"), 16), REG("r0"));
STORE(SUB(REG("r11"), 20), REG("r1"));
SET_REG("r3", 0);
STORE(SUB(REG("r11"), 8), REG("r3"));
SET_REG("r3", 0);
STORE(SUB(REG("r11"), 12), REG("r3"));
goto loc_11;
loc_11:
SET_REG("r2", LOAD(SUB(REG("r11"), 12)));
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
if(CMP_SLT(REG("r2"), REG("r3")))
goto loc_14;
else
goto loc_22;
loc_14:
SET_REG("r2", LOAD(SUB(REG("r11"), 8)));
SET_REG("r3", LOAD(SUB(REG("r11"), 16)));
SET_REG("r3", ADD(REG("r2"), REG("r3")));
STORE(SUB(REG("r11"), 8), REG("r3"));
SET_REG("r3", LOAD(SUB(REG("r11"), 12)));
SET_REG("r3", ADD(REG("r3"), 1));
STORE(SUB(REG("r11"), 12), REG("r3"));
goto loc_11;
loc_22:
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
if(CMP_SGE(REG("r3"), 0))
goto loc_24;
else
goto loc_30;
loc_24:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r0", REG("r3"));
SET_REG("sp", REG("r11"));
SET_REG("r11", LOAD(REG("sp")));
SET_REG("sp", ADD(REG("sp"), 4));
// jump(lr)
return;
loc_30:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r3", SUB(0, REG("r3")));
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_24;
}
/* int32_t exp(int32_t arg1, int32_t arg2) */
void exp(void)
{
loc_0:
SET_REG("sp", SUB(REG("sp"), 4));
STORE(REG("sp"), REG("r11"));
SET_REG("r11", REG("sp"));
SET_REG("sp", SUB(REG("sp"), 20));
STORE(SUB(REG("r11"), 16), REG("r0"));
STORE(SUB(REG("r11"), 20), REG("r1"));
SET_REG("r3", 1);
STORE(SUB(REG("r11"), 8), REG("r3"));
SET_REG("r3", 0);
STORE(SUB(REG("r11"), 12), REG("r3"));
goto loc_11;
loc_11:
SET_REG("r2", LOAD(SUB(REG("r11"), 12)));
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
if(CMP_SLT(REG("r2"), REG("r3")))
goto loc_14;
else
goto loc_22;
loc_14:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r2", LOAD(SUB(REG("r11"), 16)));
SET_REG("r3", MUL(REG("r2"), REG("r3")));
STORE(SUB(REG("r11"), 8), REG("r3"));
SET_REG("r3", LOAD(SUB(REG("r11"), 12)));
SET_REG("r3", ADD(REG("r3"), 1));
STORE(SUB(REG("r11"), 12), REG("r3"));
goto loc_11;
loc_22:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r0", REG("r3"));
SET_REG("sp", REG("r11"));
SET_REG("r11", LOAD(REG("sp")));
SET_REG("sp", ADD(REG("sp"), 4));
// jump(lr)
return;
}
/* int32_t expmod(int32_t arg1, int32_t arg2, int32_t arg3) */
void expmod(void)
{
loc_0:
PUSH(REG("lr"));
PUSH(REG("r11"));
SET_REG("r11", ADD(REG("sp"), 4));
SET_REG("sp", SUB(REG("sp"), 24));
STORE(SUB(REG("r11"), 16), REG("r0"));
STORE(SUB(REG("r11"), 20), REG("r1"));
STORE(SUB(REG("r11"), 24), REG("r2"));
SET_REG("r3", 1);
STORE(SUB(REG("r11"), 8), REG("r3"));
SET_REG("r3", LOAD(SUB(REG("r11"), 16)));
STORE(SUB(REG("r11"), 12), REG("r3"));
goto loc_12;
loc_12:
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
if(CMP_NE(REG("r3"), 0))
goto loc_14;
else
goto loc_17;
loc_14:
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
SET_REG("r3", AND(REG("r3"), 1));
if(CMP_E(REG("r3"), 0))
goto loc_22;
else
goto loc_34;
loc_17:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r0", REG("r3"));
SET_REG("sp", SUB(REG("r11"), 4));
SET_REG("r11", POP());
// jump(pop)
return;
loc_22:
SET_REG("r3", LOAD(SUB(REG("r11"), 12)));
SET_REG("r2", LOAD(SUB(REG("r11"), 12)));
SET_REG("r3", MUL(REG("r2"), REG("r3")));
SET_REG("r0", REG("r3"));
SET_REG("r1", LOAD(SUB(REG("r11"), 24)));
// call(0x380)
__aeabi_idivmod();
SET_REG("r3", REG("r1"));
STORE(SUB(REG("r11"), 12), REG("r3"));
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
SET_REG("r3", ASR(REG("r3"), 1));
STORE(SUB(REG("r11"), 20), REG("r3"));
goto loc_12;
loc_34:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r2", LOAD(SUB(REG("r11"), 12)));
SET_REG("r3", MUL(REG("r2"), REG("r3")));
SET_REG("r0", REG("r3"));
SET_REG("r1", LOAD(SUB(REG("r11"), 24)));
// call(0x380)
__aeabi_idivmod();
SET_REG("r3", REG("r1"));
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_22;
}
/* int32_t gcd(int32_t arg1, int32_t arg2) */
void gcd(void)
{
loc_0:
PUSH(REG("lr"));
PUSH(REG("r11"));
SET_REG("r11", ADD(REG("sp"), 4));
SET_REG("sp", SUB(REG("sp"), 16));
STORE(SUB(REG("r11"), 16), REG("r0"));
STORE(SUB(REG("r11"), 20), REG("r1"));
goto loc_7;
loc_7:
SET_REG("r3", LOAD(SUB(REG("r11"), 16)));
if(CMP_NE(REG("r3"), 0))
goto loc_9;
else
goto loc_11;
loc_9:
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
if(CMP_NE(REG("r3"), 0))
goto loc_14;
else
goto loc_17;
loc_11:
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_20;
loc_14:
SET_REG("r2", LOAD(SUB(REG("r11"), 16)));
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
if(CMP_SLE(REG("r2"), REG("r3")))
goto loc_25;
else
goto loc_32;
loc_17:
SET_REG("r3", LOAD(SUB(REG("r11"), 16)));
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_20;
loc_20:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r0", REG("r3"));
SET_REG("sp", SUB(REG("r11"), 4));
SET_REG("r11", POP());
// jump(pop)
return;
loc_25:
SET_REG("r3", LOAD(SUB(REG("r11"), 20)));
SET_REG("r0", REG("r3"));
SET_REG("r1", LOAD(SUB(REG("r11"), 16)));
// call(0x380)
__aeabi_idivmod();
SET_REG("r3", REG("r1"));
STORE(SUB(REG("r11"), 20), REG("r3"));
goto loc_39;
loc_32:
SET_REG("r3", LOAD(SUB(REG("r11"), 16)));
SET_REG("r0", REG("r3"));
SET_REG("r1", LOAD(SUB(REG("r11"), 20)));
// call(0x380)
__aeabi_idivmod();
SET_REG("r3", REG("r1"));
STORE(SUB(REG("r11"), 16), REG("r3"));
goto loc_39;
loc_39:
goto loc_7;
}
/* int32_t switch_doubler(int32_t arg1) */
void switch_doubler(void)
{
loc_0:
SET_REG("sp", SUB(REG("sp"), 4));
STORE(REG("sp"), REG("r11"));
SET_REG("r11", REG("sp"));
SET_REG("sp", SUB(REG("sp"), 20));
STORE(SUB(REG("r11"), 16), REG("r0"));
SET_REG("r3", LOAD(SUB(REG("r11"), 16)));
if(CMP_ULE(REG("r3"), 10))
goto loc_7;
else
goto loc_8;
loc_7:
// jump(0x278 + (r3 << 2) => 9 @ 0x274, 10 @ 0x278, 11 @ 0x27c, 12 @ 0x280, 13 @ 0x284, 14 @ 0x288, 15 @ 0x28c, 16 @ 0x290, 17 @ 0x294, 18 @ 0x298, 19 @ 0x29c, 20 @ 0x2a0)
switch(ADD(0x278, LSL(REG("r3"), 2)))
{
case 0x274: goto loc_9;
case 0x278: goto loc_10;
case 0x27C: goto loc_11;
case 0x280: goto loc_12;
case 0x284: goto loc_13;
case 0x288: goto loc_14;
case 0x28C: goto loc_15;
case 0x290: goto loc_16;
case 0x294: goto loc_17;
case 0x298: goto loc_18;
case 0x29C: goto loc_19;
case 0x2A0: goto loc_20;
default: printf("switch fucked\n"); while(1);
}
loc_8:
goto loc_9;
loc_9:
goto loc_21;
loc_10:
goto loc_24;
loc_11:
goto loc_27;
loc_12:
goto loc_30;
loc_13:
goto loc_33;
loc_14:
goto loc_36;
loc_15:
goto loc_39;
loc_16:
goto loc_42;
loc_17:
goto loc_45;
loc_18:
goto loc_48;
loc_19:
goto loc_51;
loc_20:
goto loc_54;
loc_21:
SET_REG("r3", NOT(0));
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_24:
SET_REG("r3", 0);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_27:
SET_REG("r3", 2);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_30:
SET_REG("r3", 4);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_33:
SET_REG("r3", 6);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_36:
SET_REG("r3", 8);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_39:
SET_REG("r3", 10);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_42:
SET_REG("r3", 12);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_45:
SET_REG("r3", 14);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_48:
SET_REG("r3", 16);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_51:
SET_REG("r3", 18);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_54:
SET_REG("r3", 20);
STORE(SUB(REG("r11"), 8), REG("r3"));
goto loc_57;
loc_57:
SET_REG("r3", LOAD(SUB(REG("r11"), 8)));
SET_REG("r0", REG("r3"));
SET_REG("sp", REG("r11"));
SET_REG("r11", LOAD(REG("sp")));
SET_REG("sp", ADD(REG("sp"), 4));
// jump(lr)
return;
}
void initialize_memory()
{
}
map<string,struct RegisterInfo> regInfos = {
{"r0", {0, "r0", 0, 4, 0}}, /* <reg: size 4, offset 0 in r0> */
{"r1", {1, "r1", 0, 4, 0}}, /* <reg: size 4, offset 0 in r1> */
{"r2", {2, "r2", 0, 4, 0}}, /* <reg: size 4, offset 0 in r2> */
{"r3", {3, "r3", 0, 4, 0}}, /* <reg: size 4, offset 0 in r3> */
{"r4", {4, "r4", 0, 4, 0}}, /* <reg: size 4, offset 0 in r4> */
{"r5", {5, "r5", 0, 4, 0}}, /* <reg: size 4, offset 0 in r5> */
{"r6", {6, "r6", 0, 4, 0}}, /* <reg: size 4, offset 0 in r6> */
{"r7", {7, "r7", 0, 4, 0}}, /* <reg: size 4, offset 0 in r7> */
{"r8", {8, "r8", 0, 4, 0}}, /* <reg: size 4, offset 0 in r8> */
{"r9", {9, "r9", 0, 4, 0}}, /* <reg: size 4, offset 0 in r9> */
{"r10", {10, "r10", 0, 4, 0}}, /* <reg: size 4, offset 0 in r10> */
{"r11", {11, "r11", 0, 4, 0}}, /* <reg: size 4, offset 0 in r11> */
{"r12", {12, "r12", 0, 4, 0}}, /* <reg: size 4, offset 0 in r12> */
{"sp", {13, "sp", 0, 4, 0}}, /* <reg: size 4, offset 0 in sp> */
{"lr", {14, "lr", 0, 4, 0}}, /* <reg: size 4, offset 0 in lr> */
{"pc", {15, "pc", 0, 4, 0}}, /* <reg: size 4, offset 0 in pc> */
{"s0", {16, "q0", 0, 4, 0}}, /* <reg: size 4, offset 0 in q0> */
{"s1", {17, "q0", 4, 4, 0}}, /* <reg: size 4, offset 4 in q0> */
{"s2", {18, "q0", 8, 4, 0}}, /* <reg: size 4, offset 8 in q0> */
{"s3", {19, "q0", 12, 4, 0}}, /* <reg: size 4, offset 12 in q0> */
{"s4", {20, "q1", 0, 4, 0}}, /* <reg: size 4, offset 0 in q1> */
{"s5", {21, "q1", 4, 4, 0}}, /* <reg: size 4, offset 4 in q1> */
{"s6", {22, "q1", 8, 4, 0}}, /* <reg: size 4, offset 8 in q1> */
{"s7", {23, "q1", 12, 4, 0}}, /* <reg: size 4, offset 12 in q1> */
{"s8", {24, "q2", 0, 4, 0}}, /* <reg: size 4, offset 0 in q2> */
{"s9", {25, "q2", 4, 4, 0}}, /* <reg: size 4, offset 4 in q2> */
{"s10", {26, "q2", 8, 4, 0}}, /* <reg: size 4, offset 8 in q2> */
{"s11", {27, "q2", 12, 4, 0}}, /* <reg: size 4, offset 12 in q2> */
{"s12", {28, "q3", 0, 4, 0}}, /* <reg: size 4, offset 0 in q3> */
{"s13", {29, "q3", 4, 4, 0}}, /* <reg: size 4, offset 4 in q3> */
{"s14", {30, "q3", 8, 4, 0}}, /* <reg: size 4, offset 8 in q3> */
{"s15", {31, "q3", 12, 4, 0}}, /* <reg: size 4, offset 12 in q3> */
{"s16", {32, "q4", 0, 4, 0}}, /* <reg: size 4, offset 0 in q4> */
{"s17", {33, "q4", 4, 4, 0}}, /* <reg: size 4, offset 4 in q4> */
{"s18", {34, "q4", 8, 4, 0}}, /* <reg: size 4, offset 8 in q4> */
{"s19", {35, "q4", 12, 4, 0}}, /* <reg: size 4, offset 12 in q4> */
{"s20", {36, "q5", 0, 4, 0}}, /* <reg: size 4, offset 0 in q5> */
{"s21", {37, "q5", 4, 4, 0}}, /* <reg: size 4, offset 4 in q5> */
{"s22", {38, "q5", 8, 4, 0}}, /* <reg: size 4, offset 8 in q5> */
{"s23", {39, "q5", 12, 4, 0}}, /* <reg: size 4, offset 12 in q5> */
{"s24", {40, "q6", 0, 4, 0}}, /* <reg: size 4, offset 0 in q6> */
{"s25", {41, "q6", 4, 4, 0}}, /* <reg: size 4, offset 4 in q6> */
{"s26", {42, "q6", 8, 4, 0}}, /* <reg: size 4, offset 8 in q6> */
{"s27", {43, "q6", 12, 4, 0}}, /* <reg: size 4, offset 12 in q6> */
{"s28", {44, "q7", 0, 4, 0}}, /* <reg: size 4, offset 0 in q7> */
{"s29", {45, "q7", 4, 4, 0}}, /* <reg: size 4, offset 4 in q7> */
{"s30", {46, "q7", 8, 4, 0}}, /* <reg: size 4, offset 8 in q7> */
{"s31", {47, "q7", 12, 4, 0}}, /* <reg: size 4, offset 12 in q7> */
{"d0", {48, "q0", 0, 8, 0}}, /* <reg: size 8, offset 0 in q0> */
{"d1", {49, "q0", 8, 8, 0}}, /* <reg: size 8, offset 8 in q0> */
{"d2", {50, "q1", 0, 8, 0}}, /* <reg: size 8, offset 0 in q1> */
{"d3", {51, "q1", 8, 8, 0}}, /* <reg: size 8, offset 8 in q1> */
{"d4", {52, "q2", 0, 8, 0}}, /* <reg: size 8, offset 0 in q2> */
{"d5", {53, "q2", 8, 8, 0}}, /* <reg: size 8, offset 8 in q2> */
{"d6", {54, "q3", 0, 8, 0}}, /* <reg: size 8, offset 0 in q3> */
{"d7", {55, "q3", 8, 8, 0}}, /* <reg: size 8, offset 8 in q3> */
{"d8", {56, "q4", 0, 8, 0}}, /* <reg: size 8, offset 0 in q4> */
{"d9", {57, "q4", 8, 8, 0}}, /* <reg: size 8, offset 8 in q4> */
{"d10", {58, "q5", 0, 8, 0}}, /* <reg: size 8, offset 0 in q5> */
{"d11", {59, "q5", 8, 8, 0}}, /* <reg: size 8, offset 8 in q5> */
{"d12", {60, "q6", 0, 8, 0}}, /* <reg: size 8, offset 0 in q6> */
{"d13", {61, "q6", 8, 8, 0}}, /* <reg: size 8, offset 8 in q6> */
{"d14", {62, "q7", 0, 8, 0}}, /* <reg: size 8, offset 0 in q7> */
{"d15", {63, "q7", 8, 8, 0}}, /* <reg: size 8, offset 8 in q7> */
{"d16", {64, "q8", 0, 8, 0}}, /* <reg: size 8, offset 0 in q8> */
{"d17", {65, "q8", 8, 8, 0}}, /* <reg: size 8, offset 8 in q8> */
{"d18", {66, "q9", 0, 8, 0}}, /* <reg: size 8, offset 0 in q9> */
{"d19", {67, "q9", 8, 8, 0}}, /* <reg: size 8, offset 8 in q9> */
{"d20", {68, "q10", 0, 8, 0}}, /* <reg: size 8, offset 0 in q10> */
{"d21", {69, "q10", 8, 8, 0}}, /* <reg: size 8, offset 8 in q10> */
{"d22", {70, "q11", 0, 8, 0}}, /* <reg: size 8, offset 0 in q11> */
{"d23", {71, "q11", 8, 8, 0}}, /* <reg: size 8, offset 8 in q11> */
{"d24", {72, "q12", 0, 8, 0}}, /* <reg: size 8, offset 0 in q12> */
{"d25", {73, "q12", 8, 8, 0}}, /* <reg: size 8, offset 8 in q12> */
{"d26", {74, "q13", 0, 8, 0}}, /* <reg: size 8, offset 0 in q13> */
{"d27", {75, "q13", 8, 8, 0}}, /* <reg: size 8, offset 8 in q13> */
{"d28", {76, "q14", 0, 8, 0}}, /* <reg: size 8, offset 0 in q14> */
{"d29", {77, "q14", 8, 8, 0}}, /* <reg: size 8, offset 8 in q14> */
{"d30", {78, "q15", 0, 8, 0}}, /* <reg: size 8, offset 0 in q15> */
{"d31", {79, "q15", 8, 8, 0}}, /* <reg: size 8, offset 8 in q15> */
{"q0", {80, "q0", 0, 16, 0}}, /* <reg: size 16, offset 0 in q0> */
{"q1", {81, "q1", 0, 16, 0}}, /* <reg: size 16, offset 0 in q1> */
{"q2", {82, "q2", 0, 16, 0}}, /* <reg: size 16, offset 0 in q2> */
{"q3", {83, "q3", 0, 16, 0}}, /* <reg: size 16, offset 0 in q3> */
{"q4", {84, "q4", 0, 16, 0}}, /* <reg: size 16, offset 0 in q4> */
{"q5", {85, "q5", 0, 16, 0}}, /* <reg: size 16, offset 0 in q5> */
{"q6", {86, "q6", 0, 16, 0}}, /* <reg: size 16, offset 0 in q6> */
{"q7", {87, "q7", 0, 16, 0}}, /* <reg: size 16, offset 0 in q7> */
{"q8", {88, "q8", 0, 16, 0}}, /* <reg: size 16, offset 0 in q8> */
{"q9", {89, "q9", 0, 16, 0}}, /* <reg: size 16, offset 0 in q9> */
{"q10", {90, "q10", 0, 16, 0}}, /* <reg: size 16, offset 0 in q10> */
{"q11", {91, "q11", 0, 16, 0}}, /* <reg: size 16, offset 0 in q11> */
{"q12", {92, "q12", 0, 16, 0}}, /* <reg: size 16, offset 0 in q12> */
{"q13", {93, "q13", 0, 16, 0}}, /* <reg: size 16, offset 0 in q13> */
{"q14", {94, "q14", 0, 16, 0}}, /* <reg: size 16, offset 0 in q14> */
{"q15", {95, "q15", 0, 16, 0}}, /* <reg: size 16, offset 0 in q15> */
};
string stackRegName = "sp";
Raw
compilable_x64_il.cpp
// tests.o: Mach-O 64-bit object x86_64
#include <stdint.h>
#include <string>
#include <vector>
#include <map>
using namespace std;
#include "runtime.h"
extern map<REGTYPE,REGTYPE> vm_mem;
/* uint64_t multiply(int32_t arg1, int32_t arg2) */
void multiply(void)
{
loc_0:
PUSH(REG("rbp"));
SET_REG("rbp", REG("rsp"));
STORE(ADD(REG("rbp"), -4), REG("edi"));
STORE(ADD(REG("rbp"), -8), REG("esi"));
SET_REG("esi", LOAD(ADD(REG("rbp"), -4)));
SET_REG("esi", MUL(REG("esi"), LOAD(ADD(REG("rbp"), -8))));
SET_REG("eax", REG("esi"));
SET_REG("rbp", POP());
RET(POP());
return;
}
/* uint64_t multiply_loop(int32_t arg1, int32_t arg2) */
void multiply_loop(void)
{
loc_0:
PUSH(REG("rbp"));
SET_REG("rbp", REG("rsp"));
STORE(ADD(REG("rbp"), -4), REG("edi"));
STORE(ADD(REG("rbp"), -8), REG("esi"));
STORE(ADD(REG("rbp"), -12), 0);
STORE(ADD(REG("rbp"), -16), 0);
goto loc_7;
loc_7:
SET_REG("eax", LOAD(ADD(REG("rbp"), -16)));
if(CMP_SGE(REG("eax"), LOAD(ADD(REG("rbp"), -8))))
goto loc_9;
else
goto loc_10;
loc_9:
if(CMP_SGE(LOAD(ADD(REG("rbp"), -8)), 0))
goto loc_17;
else
goto loc_20;
loc_10:
SET_REG("eax", LOAD(ADD(REG("rbp"), -12)));
SET_REG("eax", ADD(REG("eax"), LOAD(ADD(REG("rbp"), -4))));
STORE(ADD(REG("rbp"), -12), REG("eax"));
SET_REG("eax", LOAD(ADD(REG("rbp"), -16)));
SET_REG("eax", ADD(REG("eax"), 1));
STORE(ADD(REG("rbp"), -16), REG("eax"));
goto loc_7;
loc_17:
SET_REG("eax", LOAD(ADD(REG("rbp"), -12)));
SET_REG("rbp", POP());
RET(POP());
return;
loc_20:
SET_REG("eax", MUL(LOAD(ADD(REG("rbp"), -12)), -1));
STORE(ADD(REG("rbp"), -12), REG("eax"));
goto loc_17;
}
/* uint64_t exp(int32_t arg1, int32_t arg2) */
void exp(void)
{
loc_0:
PUSH(REG("rbp"));
SET_REG("rbp", REG("rsp"));
STORE(ADD(REG("rbp"), -4), REG("edi"));
STORE(ADD(REG("rbp"), -8), REG("esi"));
STORE(ADD(REG("rbp"), -12), 1);
STORE(ADD(REG("rbp"), -16), 0);
goto loc_7;
loc_7:
SET_REG("eax", LOAD(ADD(REG("rbp"), -16)));
if(CMP_SGE(REG("eax"), LOAD(ADD(REG("rbp"), -8))))
goto loc_9;
else
goto loc_12;
loc_9:
SET_REG("eax", LOAD(ADD(REG("rbp"), -12)));
SET_REG("rbp", POP());
RET(POP());
return;
loc_12:
SET_REG("eax", LOAD(ADD(REG("rbp"), -12)));
SET_REG("eax", MUL(REG("eax"), LOAD(ADD(REG("rbp"), -4))));
STORE(ADD(REG("rbp"), -12), REG("eax"));
SET_REG("eax", LOAD(ADD(REG("rbp"), -16)));
SET_REG("eax", ADD(REG("eax"), 1));
STORE(ADD(REG("rbp"), -16), REG("eax"));
goto loc_7;
}
/* uint64_t expmod(int32_t arg1, int32_t arg2, int32_t arg3) */
void expmod(void)
{
loc_0:
PUSH(REG("rbp"));
SET_REG("rbp", REG("rsp"));
STORE(ADD(REG("rbp"), -4), REG("edi"));
STORE(ADD(REG("rbp"), -8), REG("esi"));
STORE(ADD(REG("rbp"), -12), REG("edx"));
STORE(ADD(REG("rbp"), -16), 1);
SET_REG("edx", LOAD(ADD(REG("rbp"), -4)));
STORE(ADD(REG("rbp"), -20), REG("edx"));
goto loc_9;
loc_9:
if(CMP_E(LOAD(ADD(REG("rbp"), -8)), 0))
goto loc_10;
else
goto loc_13;
loc_10:
SET_REG("eax", LOAD(ADD(REG("rbp"), -16)));
SET_REG("rbp", POP());
RET(POP());
return;
loc_13:
SET_REG("eax", LOAD(ADD(REG("rbp"), -8)));
SET_REG("eax", AND(REG("eax"), 1));
if(CMP_E(REG("eax"), 0))
goto loc_16;
else
goto loc_34;
loc_16:
SET_REG("eax", LOAD(ADD(REG("rbp"), -20)));
SET_REG("eax", MUL(REG("eax"), LOAD(ADD(REG("rbp"), -20))));
SET_REG_SPLIT("temp2", "temp3", SX(REG("eax")));
SET_REG("edx", REG("temp2"));
SET_REG("eax", REG("temp3"));
SET_REG("temp4", REG("edx"));
SET_REG("temp5", REG("eax"));
SET_REG("temp0", DIVS_DP(REG_SPLIT("temp4", "temp5"), LOAD(ADD(REG("rbp"), -12))));
SET_REG("temp6", REG("edx"));
SET_REG("temp7", REG("eax"));
SET_REG("temp1", MODS_DP(REG_SPLIT("temp6", "temp7"), LOAD(ADD(REG("rbp"), -12))));
SET_REG("eax", REG("temp0"));
SET_REG("edx", REG("temp1"));
STORE(ADD(REG("rbp"), -20), REG("edx"));
SET_REG("edx", LOAD(ADD(REG("rbp"), -8)));
SET_REG("edx", ASR(REG("edx"), 1));
STORE(ADD(REG("rbp"), -8), REG("edx"));
goto loc_9;
loc_34:
SET_REG("eax", LOAD(ADD(REG("rbp"), -16)));
SET_REG("eax", MUL(REG("eax"), LOAD(ADD(REG("rbp"), -20))));
SET_REG_SPLIT("temp8", "temp9", SX(REG("eax")));
SET_REG("edx", REG("temp8"));
SET_REG("eax", REG("temp9"));
SET_REG("temp10", REG("edx"));
SET_REG("temp11", REG("eax"));
SET_REG("temp0", DIVS_DP(REG_SPLIT("temp10", "temp11"), LOAD(ADD(REG("rbp"), -12))));
SET_REG("temp12", REG("edx"));
SET_REG("temp13", REG("eax"));
SET_REG("temp1", MODS_DP(REG_SPLIT("temp12", "temp13"), LOAD(ADD(REG("rbp"), -12))));
SET_REG("eax", REG("temp0"));
SET_REG("edx", REG("temp1"));
STORE(ADD(REG("rbp"), -16), REG("edx"));
goto loc_16;
}
/* uint64_t gcd(int32_t arg1, int32_t arg2) */
void gcd(void)
{
loc_0:
PUSH(REG("rbp"));
SET_REG("rbp", REG("rsp"));
STORE(ADD(REG("rbp"), -4), REG("edi"));
STORE(ADD(REG("rbp"), -8), REG("esi"));
goto loc_5;
loc_5:
if(CMP_NE(LOAD(ADD(REG("rbp"), -4)), 0))
goto loc_6;
else
goto loc_7;
loc_6:
if(CMP_NE(LOAD(ADD(REG("rbp"), -8)), 0))
goto loc_10;
else
goto loc_12;
loc_7:
SET_REG("eax", LOAD(ADD(REG("rbp"), -8)));
STORE(ADD(REG("rbp"), -12), REG("eax"));
goto loc_15;
loc_10:
SET_REG("eax", LOAD(ADD(REG("rbp"), -4)));
if(CMP_SLE(REG("eax"), LOAD(ADD(REG("rbp"), -8))))
goto loc_18;
else
goto loc_32;
loc_12:
SET_REG("eax", LOAD(ADD(REG("rbp"), -4)));
STORE(ADD(REG("rbp"), -12), REG("eax"));
goto loc_15;
loc_15:
SET_REG("eax", LOAD(ADD(REG("rbp"), -12)));
SET_REG("rbp", POP());
RET(POP());
return;
loc_18:
SET_REG("eax", LOAD(ADD(REG("rbp"), -8)));
SET_REG_SPLIT("temp2", "temp3", SX(REG("eax")));
SET_REG("edx", REG("temp2"));
SET_REG("eax", REG("temp3"));
SET_REG("temp4", REG("edx"));
SET_REG("temp5", REG("eax"));
SET_REG("temp0", DIVS_DP(REG_SPLIT("temp4", "temp5"), LOAD(ADD(REG("rbp"), -4))));
SET_REG("temp6", REG("edx"));
SET_REG("temp7", REG("eax"));
SET_REG("temp1", MODS_DP(REG_SPLIT("temp6", "temp7"), LOAD(ADD(REG("rbp"), -4))));
SET_REG("eax", REG("temp0"));
SET_REG("edx", REG("temp1"));
STORE(ADD(REG("rbp"), -8), REG("edx"));
goto loc_46;
loc_32:
SET_REG("eax", LOAD(ADD(REG("rbp"), -4)));
SET_REG_SPLIT("temp8", "temp9", SX(REG("eax")));
SET_REG("edx", REG("temp8"));
SET_REG("eax", REG("temp9"));
SET_REG("temp10", REG("edx"));
SET_REG("temp11", REG("eax"));
SET_REG("temp0", DIVS_DP(REG_SPLIT("temp10", "temp11"), LOAD(ADD(REG("rbp"), -8))));
SET_REG("temp12", REG("edx"));
SET_REG("temp13", REG("eax"));
SET_REG("temp1", MODS_DP(REG_SPLIT("temp12", "temp13"), LOAD(ADD(REG("rbp"), -8))));
SET_REG("eax", REG("temp0"));
SET_REG("edx", REG("temp1"));
STORE(ADD(REG("rbp"), -4), REG("edx"));
goto loc_46;
loc_46:
goto loc_5;
}
/* uint64_t switch_doubler(int32_t arg1) */
void switch_doubler(void)
{
loc_0:
PUSH(REG("rbp"));
SET_REG("rbp", REG("rsp"));
STORE(ADD(REG("rbp"), -4), REG("edi"));
SET_REG("edi", LOAD(ADD(REG("rbp"), -4)));
SET_REG("eax", REG("edi"));
SET_REG("rcx", REG("rax"));
SET_REG("temp0", REG("rcx"));
SET_REG("rcx", SUB(REG("rcx"), 10));
SET_FLAG("cond:0", CMP_UGT(REG("temp0"), 10));
STORE(ADD(REG("rbp"), -16), REG("rax"));
STORE(ADD(REG("rbp"), -24), REG("rcx"));
if(FLAG("cond:0"))
goto loc_12;
else
goto loc_14;
loc_12:
STORE(ADD(REG("rbp"), -8), -1);
goto loc_19;
loc_14:
SET_REG("rax", 0x278);
SET_REG("rcx", LOAD(ADD(REG("rbp"), -16)));
SET_REG("rdx", SX(LOAD(ADD(REG("rax"), LSL(REG("rcx"), 2)))));
SET_REG("rdx", ADD(REG("rdx"), REG("rax")));
// jump(rdx => 22 @ 0x1e5, 24 @ 0x1f1, 26 @ 0x1fd, 28 @ 0x209, 30 @ 0x215, 32 @ 0x221, 34 @ 0x22d, 36 @ 0x239, 38 @ 0x245, 40 @ 0x251, 42 @ 0x25d)
switch(REG("rdx"))
{
case 0x1E5: goto loc_22;
case 0x1F1: goto loc_24;
case 0x1FD: goto loc_26;
case 0x209: goto loc_28;
case 0x215: goto loc_30;
case 0x221: goto loc_32;
case 0x22D: goto loc_34;
case 0x239: goto loc_36;
case 0x245: goto loc_38;
case 0x251: goto loc_40;
case 0x25D: goto loc_42;
default: printf("switch fucked\n"); while(1);
}
loc_19:
SET_REG("eax", LOAD(ADD(REG("rbp"), -8)));
SET_REG("rbp", POP());
RET(POP());
return;
loc_22:
STORE(ADD(REG("rbp"), -8), 0);
goto loc_19;
loc_24:
STORE(ADD(REG("rbp"), -8), 2);
goto loc_19;
loc_26:
STORE(ADD(REG("rbp"), -8), 4);
goto loc_19;
loc_28:
STORE(ADD(REG("rbp"), -8), 6);
goto loc_19;
loc_30:
STORE(ADD(REG("rbp"), -8), 8);
goto loc_19;
loc_32:
STORE(ADD(REG("rbp"), -8), 10);
goto loc_19;
loc_34:
STORE(ADD(REG("rbp"), -8), 12);
goto loc_19;
loc_36:
STORE(ADD(REG("rbp"), -8), 14);
goto loc_19;
loc_38:
STORE(ADD(REG("rbp"), -8), 16);
goto loc_19;
loc_40:
STORE(ADD(REG("rbp"), -8), 18);
goto loc_19;
loc_42:
STORE(ADD(REG("rbp"), -8), 20);
goto loc_19;
}
void initialize_memory()
{
// <SymbolType.DataSymbol: "jump_table_278" @ 0x278>
vm_mem[0x278] = 0xFFFFFF6D;
vm_mem[0x27C] = 0xFFFFFF79;
vm_mem[0x280] = 0xFFFFFF85;
vm_mem[0x284] = 0xFFFFFF91;
vm_mem[0x288] = 0xFFFFFF9D;
vm_mem[0x28C] = 0xFFFFFFA9;
vm_mem[0x290] = 0xFFFFFFB5;
vm_mem[0x294] = 0xFFFFFFC1;
vm_mem[0x298] = 0xFFFFFFCD;
vm_mem[0x29C] = 0xFFFFFFD9;
vm_mem[0x2A0] = 0xFFFFFFE5;
}
map<string,struct RegisterInfo> regInfos = {
{"ah", {98, "rax", 1, 1, 0}}, /* <reg: size 1, offset 1 in rax> */
{"ch", {99, "rcx", 1, 1, 0}}, /* <reg: size 1, offset 1 in rcx> */
{"dh", {100, "rdx", 1, 1, 0}}, /* <reg: size 1, offset 1 in rdx> */
{"bh", {101, "rbx", 1, 1, 0}}, /* <reg: size 1, offset 1 in rbx> */
{"al", {82, "rax", 0, 1, 0}}, /* <reg: size 1, offset 0 in rax> */
{"cl", {83, "rcx", 0, 1, 0}}, /* <reg: size 1, offset 0 in rcx> */
{"dl", {84, "rdx", 0, 1, 0}}, /* <reg: size 1, offset 0 in rdx> */
{"bl", {85, "rbx", 0, 1, 0}}, /* <reg: size 1, offset 0 in rbx> */
{"spl", {86, "rsp", 0, 1, 0}}, /* <reg: size 1, offset 0 in rsp> */
{"bpl", {87, "rbp", 0, 1, 0}}, /* <reg: size 1, offset 0 in rbp> */
{"sil", {88, "rsi", 0, 1, 0}}, /* <reg: size 1, offset 0 in rsi> */
{"dil", {89, "rdi", 0, 1, 0}}, /* <reg: size 1, offset 0 in rdi> */
{"r8b", {90, "r8", 0, 1, 0}}, /* <reg: size 1, offset 0 in r8> */
{"r9b", {91, "r9", 0, 1, 0}}, /* <reg: size 1, offset 0 in r9> */
{"r10b", {92, "r10", 0, 1, 0}}, /* <reg: size 1, offset 0 in r10> */
{"r11b", {93, "r11", 0, 1, 0}}, /* <reg: size 1, offset 0 in r11> */
{"r12b", {94, "r12", 0, 1, 0}}, /* <reg: size 1, offset 0 in r12> */
{"r13b", {95, "r13", 0, 1, 0}}, /* <reg: size 1, offset 0 in r13> */
{"r14b", {96, "r14", 0, 1, 0}}, /* <reg: size 1, offset 0 in r14> */
{"r15b", {97, "r15", 0, 1, 0}}, /* <reg: size 1, offset 0 in r15> */
{"ip", {105, "rip", 0, 2, 0}}, /* <reg: size 2, offset 0 in rip> */
{"cs", {147, "cs", 0, 2, 0}}, /* <reg: size 2, offset 0 in cs> */
{"ds", {148, "ds", 0, 2, 0}}, /* <reg: size 2, offset 0 in ds> */
{"es", {149, "es", 0, 2, 0}}, /* <reg: size 2, offset 0 in es> */
{"ss", {150, "ss", 0, 2, 0}}, /* <reg: size 2, offset 0 in ss> */
{"fs", {151, "fs", 0, 2, 0}}, /* <reg: size 2, offset 0 in fs> */
{"gs", {152, "gs", 0, 2, 0}}, /* <reg: size 2, offset 0 in gs> */
{"fsbase", {134, "fsbase", 0, 2, 0}}, /* <reg: size 2, offset 0 in fsbase> */
{"gsbase", {135, "gsbase", 0, 2, 0}}, /* <reg: size 2, offset 0 in gsbase> */
{"sp", {38, "rsp", 0, 2, 0}}, /* <reg: size 2, offset 0 in rsp> */
{"bp", {39, "rbp", 0, 2, 0}}, /* <reg: size 2, offset 0 in rbp> */
{"si", {40, "rsi", 0, 2, 0}}, /* <reg: size 2, offset 0 in rsi> */
{"di", {41, "rdi", 0, 2, 0}}, /* <reg: size 2, offset 0 in rdi> */
{"flags", {31, "rflags", 0, 2, 0}}, /* <reg: size 2, offset 0 in rflags> */
{"top", {4104, "top", 0, 2, 0}}, /* <reg: size 2, offset 0 in top> */
{"ax", {34, "rax", 0, 2, 0}}, /* <reg: size 2, offset 0 in rax> */
{"cx", {35, "rcx", 0, 2, 0}}, /* <reg: size 2, offset 0 in rcx> */
{"dx", {36, "rdx", 0, 2, 0}}, /* <reg: size 2, offset 0 in rdx> */
{"bx", {37, "rbx", 0, 2, 0}}, /* <reg: size 2, offset 0 in rbx> */
{"r8w", {42, "r8", 0, 2, 0}}, /* <reg: size 2, offset 0 in r8> */
{"r9w", {43, "r9", 0, 2, 0}}, /* <reg: size 2, offset 0 in r9> */
{"r10w", {44, "r10", 0, 2, 0}}, /* <reg: size 2, offset 0 in r10> */
{"r11w", {45, "r11", 0, 2, 0}}, /* <reg: size 2, offset 0 in r11> */
{"r12w", {46, "r12", 0, 2, 0}}, /* <reg: size 2, offset 0 in r12> */
{"r13w", {47, "r13", 0, 2, 0}}, /* <reg: size 2, offset 0 in r13> */
{"r14w", {48, "r14", 0, 2, 0}}, /* <reg: size 2, offset 0 in r14> */
{"r15w", {49, "r15", 0, 2, 0}}, /* <reg: size 2, offset 0 in r15> */
{"eip", {104, "rip", 0, 4, 0}}, /* <reg: size 4, offset 0 in rip> */
{"esp", {54, "rsp", 0, 4, 1}}, /* <reg: size 4, offset 0 in rsp, zero extend> */
{"ebp", {55, "rbp", 0, 4, 1}}, /* <reg: size 4, offset 0 in rbp, zero extend> */
{"esi", {56, "rsi", 0, 4, 1}}, /* <reg: size 4, offset 0 in rsi, zero extend> */
{"edi", {57, "rdi", 0, 4, 1}}, /* <reg: size 4, offset 0 in rdi, zero extend> */
{"eflags", {32, "rflags", 0, 4, 1}}, /* <reg: size 4, offset 0 in rflags, zero extend> */
{"eax", {50, "rax", 0, 4, 1}}, /* <reg: size 4, offset 0 in rax, zero extend> */
{"ecx", {51, "rcx", 0, 4, 1}}, /* <reg: size 4, offset 0 in rcx, zero extend> */
{"edx", {52, "rdx", 0, 4, 1}}, /* <reg: size 4, offset 0 in rdx, zero extend> */
{"ebx", {53, "rbx", 0, 4, 1}}, /* <reg: size 4, offset 0 in rbx, zero extend> */
{"r8d", {58, "r8", 0, 4, 1}}, /* <reg: size 4, offset 0 in r8, zero extend> */
{"r9d", {59, "r9", 0, 4, 1}}, /* <reg: size 4, offset 0 in r9, zero extend> */
{"r10d", {60, "r10", 0, 4, 1}}, /* <reg: size 4, offset 0 in r10, zero extend> */
{"r11d", {61, "r11", 0, 4, 1}}, /* <reg: size 4, offset 0 in r11, zero extend> */
{"r12d", {62, "r12", 0, 4, 1}}, /* <reg: size 4, offset 0 in r12, zero extend> */
{"r13d", {63, "r13", 0, 4, 1}}, /* <reg: size 4, offset 0 in r13, zero extend> */
{"r14d", {64, "r14", 0, 4, 1}}, /* <reg: size 4, offset 0 in r14, zero extend> */
{"r15d", {65, "r15", 0, 4, 1}}, /* <reg: size 4, offset 0 in r15, zero extend> */
{"gdtr", {127, "gdtr", 0, 6, 0}}, /* <reg: size 6, offset 0 in gdtr> */
{"ldtr", {128, "ldtr", 0, 6, 0}}, /* <reg: size 6, offset 0 in ldtr> */
{"idtr", {129, "idtr", 0, 6, 0}}, /* <reg: size 6, offset 0 in idtr> */
{"tr", {130, "tr", 0, 8, 0}}, /* <reg: size 8, offset 0 in tr> */
{"tsc", {131, "tsc", 0, 8, 0}}, /* <reg: size 8, offset 0 in tsc> */
{"tscaux", {132, "tscaux", 0, 8, 0}}, /* <reg: size 8, offset 0 in tscaux> */
{"mmx0", {114, "st0", 0, 8, 0}}, /* <reg: size 8, offset 0 in st0> */
{"mmx1", {115, "st1", 0, 8, 0}}, /* <reg: size 8, offset 0 in st1> */
{"mmx2", {116, "st2", 0, 8, 0}}, /* <reg: size 8, offset 0 in st2> */
{"mmx3", {117, "st3", 0, 8, 0}}, /* <reg: size 8, offset 0 in st3> */
{"mmx4", {118, "st4", 0, 8, 0}}, /* <reg: size 8, offset 0 in st4> */
{"mmx5", {119, "st5", 0, 8, 0}}, /* <reg: size 8, offset 0 in st5> */
{"mmx6", {120, "st6", 0, 8, 0}}, /* <reg: size 8, offset 0 in st6> */
{"mmx7", {121, "st7", 0, 8, 0}}, /* <reg: size 8, offset 0 in st7> */
{"rip", {103, "rip", 0, 8, 0}}, /* <reg: size 8, offset 0 in rip> */
{"rsp", {70, "rsp", 0, 8, 0}}, /* <reg: size 8, offset 0 in rsp> */
{"rbp", {71, "rbp", 0, 8, 0}}, /* <reg: size 8, offset 0 in rbp> */
{"rsi", {72, "rsi", 0, 8, 0}}, /* <reg: size 8, offset 0 in rsi> */
{"rdi", {73, "rdi", 0, 8, 0}}, /* <reg: size 8, offset 0 in rdi> */
{"rflags", {33, "rflags", 0, 8, 0}}, /* <reg: size 8, offset 0 in rflags> */
{"mxcsr", {124, "mxcsr", 0, 8, 0}}, /* <reg: size 8, offset 0 in mxcsr> */
{"xcr0", {177, "xcr0", 0, 8, 0}}, /* <reg: size 8, offset 0 in xcr0> */
{"ssp", {122, "ssp", 0, 8, 0}}, /* <reg: size 8, offset 0 in ssp> */
{"rax", {66, "rax", 0, 8, 0}}, /* <reg: size 8, offset 0 in rax> */
{"rcx", {67, "rcx", 0, 8, 0}}, /* <reg: size 8, offset 0 in rcx> */
{"rdx", {68, "rdx", 0, 8, 0}}, /* <reg: size 8, offset 0 in rdx> */
{"rbx", {69, "rbx", 0, 8, 0}}, /* <reg: size 8, offset 0 in rbx> */
{"r8", {74, "r8", 0, 8, 0}}, /* <reg: size 8, offset 0 in r8> */
{"r9", {75, "r9", 0, 8, 0}}, /* <reg: size 8, offset 0 in r9> */
{"r10", {76, "r10", 0, 8, 0}}, /* <reg: size 8, offset 0 in r10> */
{"r11", {77, "r11", 0, 8, 0}}, /* <reg: size 8, offset 0 in r11> */
{"r12", {78, "r12", 0, 8, 0}}, /* <reg: size 8, offset 0 in r12> */
{"r13", {79, "r13", 0, 8, 0}}, /* <reg: size 8, offset 0 in r13> */
{"r14", {80, "r14", 0, 8, 0}}, /* <reg: size 8, offset 0 in r14> */
{"r15", {81, "r15", 0, 8, 0}}, /* <reg: size 8, offset 0 in r15> */
{"bndcfgu", {1, "bndcfgu", 0, 8, 0}}, /* <reg: size 8, offset 0 in bndcfgu> */
{"bndstatus", {2, "bndstatus", 0, 8, 0}}, /* <reg: size 8, offset 0 in bndstatus> */
{"k0", {106, "k0", 0, 8, 0}}, /* <reg: size 8, offset 0 in k0> */
{"k1", {107, "k1", 0, 8, 0}}, /* <reg: size 8, offset 0 in k1> */
{"k2", {108, "k2", 0, 8, 0}}, /* <reg: size 8, offset 0 in k2> */
{"k3", {109, "k3", 0, 8, 0}}, /* <reg: size 8, offset 0 in k3> */
{"k4", {110, "k4", 0, 8, 0}}, /* <reg: size 8, offset 0 in k4> */
{"k5", {111, "k5", 0, 8, 0}}, /* <reg: size 8, offset 0 in k5> */
{"k6", {112, "k6", 0, 8, 0}}, /* <reg: size 8, offset 0 in k6> */
{"k7", {113, "k7", 0, 8, 0}}, /* <reg: size 8, offset 0 in k7> */
{"cr0", {7, "cr0", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr0> */
{"cr1", {8, "cr1", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr1> */
{"cr2", {9, "cr2", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr2> */
{"cr3", {10, "cr3", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr3> */
{"cr4", {11, "cr4", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr4> */
{"cr5", {12, "cr5", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr5> */
{"cr6", {13, "cr6", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr6> */
{"cr7", {14, "cr7", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr7> */
{"cr8", {15, "cr8", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr8> */
{"cr9", {16, "cr9", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr9> */
{"cr10", {17, "cr10", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr10> */
{"cr11", {18, "cr11", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr11> */
{"cr12", {19, "cr12", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr12> */
{"cr13", {20, "cr13", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr13> */
{"cr14", {21, "cr14", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr14> */
{"cr15", {22, "cr15", 0, 8, 0}}, /* <reg: size 8, offset 0 in cr15> */
{"dr0", {23, "dr0", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr0> */
{"dr1", {24, "dr1", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr1> */
{"dr2", {25, "dr2", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr2> */
{"dr3", {26, "dr3", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr3> */
{"dr4", {27, "dr4", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr4> */
{"dr5", {28, "dr5", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr5> */
{"dr6", {29, "dr6", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr6> */
{"dr7", {30, "dr7", 0, 8, 0}}, /* <reg: size 8, offset 0 in dr7> */
{"st0", {169, "st0", 0, 10, 0}}, /* <reg: size 10, offset 0 in st0> */
{"st1", {170, "st1", 0, 10, 0}}, /* <reg: size 10, offset 0 in st1> */
{"st2", {171, "st2", 0, 10, 0}}, /* <reg: size 10, offset 0 in st2> */
{"st3", {172, "st3", 0, 10, 0}}, /* <reg: size 10, offset 0 in st3> */
{"st4", {173, "st4", 0, 10, 0}}, /* <reg: size 10, offset 0 in st4> */
{"st5", {174, "st5", 0, 10, 0}}, /* <reg: size 10, offset 0 in st5> */
{"st6", {175, "st6", 0, 10, 0}}, /* <reg: size 10, offset 0 in st6> */
{"st7", {176, "st7", 0, 10, 0}}, /* <reg: size 10, offset 0 in st7> */
{"x87_r0", {4096, "x87_r0", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r0> */
{"x87_r1", {4097, "x87_r1", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r1> */
{"x87_r2", {4098, "x87_r2", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r2> */
{"x87_r3", {4099, "x87_r3", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r3> */
{"x87_r4", {4100, "x87_r4", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r4> */
{"x87_r5", {4101, "x87_r5", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r5> */
{"x87_r6", {4102, "x87_r6", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r6> */
{"x87_r7", {4103, "x87_r7", 0, 10, 0}}, /* <reg: size 10, offset 0 in x87_r7> */
{"xmm0", {178, "zmm0", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm0> */
{"xmm1", {179, "zmm1", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm1> */
{"xmm2", {180, "zmm2", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm2> */
{"xmm3", {181, "zmm3", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm3> */
{"xmm4", {182, "zmm4", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm4> */
{"xmm5", {183, "zmm5", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm5> */
{"xmm6", {184, "zmm6", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm6> */
{"xmm7", {185, "zmm7", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm7> */
{"xmm8", {186, "zmm8", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm8> */
{"xmm9", {187, "zmm9", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm9> */
{"xmm10", {188, "zmm10", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm10> */
{"xmm11", {189, "zmm11", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm11> */
{"xmm12", {190, "zmm12", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm12> */
{"xmm13", {191, "zmm13", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm13> */
{"xmm14", {192, "zmm14", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm14> */
{"xmm15", {193, "zmm15", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm15> */
{"xmm16", {194, "zmm16", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm16> */
{"xmm17", {195, "zmm17", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm17> */
{"xmm18", {196, "zmm18", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm18> */
{"xmm19", {197, "zmm19", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm19> */
{"xmm20", {198, "zmm20", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm20> */
{"xmm21", {199, "zmm21", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm21> */
{"xmm22", {200, "zmm22", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm22> */
{"xmm23", {201, "zmm23", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm23> */
{"xmm24", {202, "zmm24", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm24> */
{"xmm25", {203, "zmm25", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm25> */
{"xmm26", {204, "zmm26", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm26> */
{"xmm27", {205, "zmm27", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm27> */
{"xmm28", {206, "zmm28", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm28> */
{"xmm29", {207, "zmm29", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm29> */
{"xmm30", {208, "zmm30", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm30> */
{"xmm31", {209, "zmm31", 0, 16, 0}}, /* <reg: size 16, offset 0 in zmm31> */
{"bnd0", {3, "bnd0", 0, 16, 0}}, /* <reg: size 16, offset 0 in bnd0> */
{"bnd1", {4, "bnd1", 0, 16, 0}}, /* <reg: size 16, offset 0 in bnd1> */
{"bnd2", {5, "bnd2", 0, 16, 0}}, /* <reg: size 16, offset 0 in bnd2> */
{"bnd3", {6, "bnd3", 0, 16, 0}}, /* <reg: size 16, offset 0 in bnd3> */
{"ymm0", {210, "zmm0", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm0> */
{"ymm1", {211, "zmm1", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm1> */
{"ymm2", {212, "zmm2", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm2> */
{"ymm3", {213, "zmm3", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm3> */
{"ymm4", {214, "zmm4", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm4> */
{"ymm5", {215, "zmm5", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm5> */
{"ymm6", {216, "zmm6", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm6> */
{"ymm7", {217, "zmm7", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm7> */
{"ymm8", {218, "zmm8", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm8> */
{"ymm9", {219, "zmm9", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm9> */
{"ymm10", {220, "zmm10", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm10> */
{"ymm11", {221, "zmm11", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm11> */
{"ymm12", {222, "zmm12", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm12> */
{"ymm13", {223, "zmm13", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm13> */
{"ymm14", {224, "zmm14", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm14> */
{"ymm15", {225, "zmm15", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm15> */
{"ymm16", {226, "zmm16", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm16> */
{"ymm17", {227, "zmm17", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm17> */
{"ymm18", {228, "zmm18", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm18> */
{"ymm19", {229, "zmm19", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm19> */
{"ymm20", {230, "zmm20", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm20> */
{"ymm21", {231, "zmm21", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm21> */
{"ymm22", {232, "zmm22", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm22> */
{"ymm23", {233, "zmm23", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm23> */
{"ymm24", {234, "zmm24", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm24> */
{"ymm25", {235, "zmm25", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm25> */
{"ymm26", {236, "zmm26", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm26> */
{"ymm27", {237, "zmm27", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm27> */
{"ymm28", {238, "zmm28", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm28> */
{"ymm29", {239, "zmm29", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm29> */
{"ymm30", {240, "zmm30", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm30> */
{"ymm31", {241, "zmm31", 0, 32, 0}}, /* <reg: size 32, offset 0 in zmm31> */
{"zmm0", {242, "zmm0", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm0> */
{"zmm1", {243, "zmm1", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm1> */
{"zmm2", {244, "zmm2", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm2> */
{"zmm3", {245, "zmm3", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm3> */
{"zmm4", {246, "zmm4", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm4> */
{"zmm5", {247, "zmm5", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm5> */
{"zmm6", {248, "zmm6", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm6> */
{"zmm7", {249, "zmm7", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm7> */
{"zmm8", {250, "zmm8", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm8> */
{"zmm9", {251, "zmm9", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm9> */
{"zmm10", {252, "zmm10", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm10> */
{"zmm11", {253, "zmm11", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm11> */
{"zmm12", {254, "zmm12", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm12> */
{"zmm13", {255, "zmm13", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm13> */
{"zmm14", {256, "zmm14", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm14> */
{"zmm15", {257, "zmm15", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm15> */
{"zmm16", {258, "zmm16", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm16> */
{"zmm17", {259, "zmm17", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm17> */
{"zmm18", {260, "zmm18", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm18> */
{"zmm19", {261, "zmm19", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm19> */
{"zmm20", {262, "zmm20", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm20> */
{"zmm21", {263, "zmm21", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm21> */
{"zmm22", {264, "zmm22", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm22> */
{"zmm23", {265, "zmm23", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm23> */
{"zmm24", {266, "zmm24", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm24> */
{"zmm25", {267, "zmm25", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm25> */
{"zmm26", {268, "zmm26", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm26> */
{"zmm27", {269, "zmm27", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm27> */
{"zmm28", {270, "zmm28", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm28> */
{"zmm29", {271, "zmm29", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm29> */
{"zmm30", {272, "zmm30", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm30> */
{"zmm31", {273, "zmm31", 0, 64, 0}}, /* <reg: size 64, offset 0 in zmm31> */
};
string stackRegName = "rsp";
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