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@macromorgan
macromorgan / .config
Created February 18, 2021 15:42
Coreboot Config for T420
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
@macromorgan
macromorgan / Installation Instructions
Created November 20, 2020 16:47
Pocket CHIP Mainline Kernel Mainline U-Boot
copy rootfs.ubi and boot.img to the root of a FAT32 formatted USB flash drive, and plug it into CHIP
boot CHIP into FEL mode
from FEL mode do:
sunxi-fel spl sunxi-spl.bin
sunxi-fel write 0x4a000000 u-boot-dtb.bin
sunxi-fel write 0x43000000 spl-400000-4000-500.bin
sunxi-fel exe 0x4a000000
from a serial console booted into u-boot do:
@macromorgan
macromorgan / .config
Created September 4, 2020 00:31
Config for 5.9 Upstream-ish Kernel for Odroid Go Advance
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.9.0-rc3 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 9.3.0-10ubuntu1) 9.3.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=90300
CONFIG_LD_VERSION=234000000
CONFIG_CLANG_VERSION=0
CONFIG_CC_CAN_LINK=y
@macromorgan
macromorgan / .config
Created July 10, 2020 02:38
Coreboot T420 Config for Tag 4.12
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
@macromorgan
macromorgan / dmesg
Created March 10, 2020 03:42
dmesg log of CF-EW72
[ 0.000000] Linux version 4.19.108 (cmorgan@macrobox) (gcc version 8.3.0 (OpenWrt GCC 8.3.0 r12463-a508ab1ac8)) #0 Mon Mar 9 23:35:35 2020
[ 0.000000] bootconsole [early0] enabled
[ 0.000000] CPU0 revision is: 00019374 (MIPS 24Kc)
[ 0.000000] MIPS: machine is COMFAST CF-EW72
[ 0.000000] SoC: Qualcomm Atheros QCA9533 ver 2 rev 0
[ 0.000000] Determined physical RAM map:
[ 0.000000] memory: 08000000 @ 00000000 (usable)
[ 0.000000] Initrd not found or empty - disabling initrd
[ 0.000000] Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
@macromorgan
macromorgan / dsdt_coreboot.dsl
Created February 18, 2020 16:05
DSDT Comparison Between Stock T440P w/ dGPU and Coreboot
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180105 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of dsdt.dat, Wed Feb 12 10:49:16 2020
*
* Original Table Header:
@macromorgan
macromorgan / cbmem.dump
Created February 5, 2020 15:55
Coreboot on T440P with dGPU (dGPU Not Working)
coreboot-4.11-1077-g99035650aa-dirty Sat Feb 1 18:31:08 UTC 2020 bootblock starting (log level: 5)...
FMAP: Found "FLASH" version 1.1 at 0xa50000.
FMAP: base = 0xff400000 size = 0xc00000 #areas = 5
FMAP: area COREBOOT found @ a50200 (1768960 bytes)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 5d44
BS: bootblock times (exec / console): total (unknown) / 0 ms
coreboot-4.11-1077-g99035650aa-dirty Sat Feb 1 18:31:08 UTC 2020 romstage starting (log level: 5)...
@macromorgan
macromorgan / pmh7.dump
Created January 31, 2020 18:14
Dump of pmh7tool for T440P (with backlight and dGPU)
0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0010: 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03
0020: 8d 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0040: 00 09 02 00 02 00 00 00 03 00 00 0b 00 00 00 00
0050: f8 02 fc 00 00 00 00 00 00 00 80 00 80 80 80 80
0060: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0080: cc db 13 77 7f 00 37 00 00 00 00 00 00 00 00 00
0090: 02 02 02 02 90 90 90 90 08 12 19 19 00 00 00 00
@macromorgan
macromorgan / ectool dump
Last active January 28, 2020 17:25
ECTOOL Dump
00: a6 05 a8 c0 00 86 00 00 00 09 47 00 00 01 80 00 (01 changes to 41 and 81 for keyboard backlight half/full bright)
10: 00 00 ff ff c0 3c 00 01 7b ff 00 00 ff ff 9d 00
20: 00 00 00 00 00 00 00 e8 00 00 00 00 00 00 00 80
30: 00 00 00 00 70 04 00 00 00 00 30 10 00 50 00 00
40: 00 00 00 00 00 00 14 42 52 14 00 00 00 00 00 00 (52 changes to 53 for the headphone insertion)
50: 00 80 02 0c 00 01 02 03 04 05 06 07 6f b7 a9 e2
60: 4f df e2 01 02 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 08 00 00 00 2a 00 00 00 00 00 00 00
80: 00 00 05 06 00 00 03 00 00 00 00 00 00 00 2b 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@macromorgan
macromorgan / gist:c5828b93cef0156051e78b499e8d251f
Last active January 27, 2020 15:25
make savedefconfig for t440p
CONFIG_CCACHE=y
CONFIG_USE_OPTION_TABLE=y
CONFIG_USE_BLOBS=y
CONFIG_NO_STAGE_CACHE=y
CONFIG_VENDOR_LENOVO=y
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_VGA_BIOS=y
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
CONFIG_VGA_BIOS_FILE="optionroms/vga_8086_0406.bin"