macromorgan

From 37912cc137743229bc616765c5f518a827b96c41 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <[email protected]>
Date: Fri, 15 Nov 2024 11:20:40 -0500
Subject: [PATCH 1/8] dt-bindings: display: vop2: Add VP clock resets

Add the documentation for VOP2 video ports reset clocks.
One reset can be set per video port.

Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Detlev Casanova <[email protected]>

macromorgan

From be013dbf05d747340f97d0bc23254306726cc699 Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Thu, 15 May 2025 10:38:44 -0500
Subject: [PATCH 0/6] Allwinner H616 PWM

Add support for the Allwinner H616 PWM controller. This is based on
the v12 patches submitted upstream for the D1 PWM controller.

Aleksandr Shubin (3):
  dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM

macromorgan

[79]HELLO! BOOT0 is starting!
[82]BOOT0 commit : 749c1f9a-dirty
[85]set pll start
[87]periph0 has been enabled
[90]set pll end
[92][pmu]: bus read error
[95][pmu]: bus read error
[97]PMU: AXP2202
[105]vaild para:8  select dram para0
[109]board init ok

macromorgan

[121]HELLO! BOOT0 is starting!
[124]BOOT0 commit : 749c1f9a-dirty
[128]set pll start
[130]periph0 has been enabled
[134]set pll end
[135][pmu]: bus read error
[138][pmu]: bus read error
[141]PMU: AXP2202
[144]dram return write ok
[146]board init ok

macromorgan

[105]HELLO! BOOT0 is starting!
[108]BOOT0 commit : 749c1f9a-dirty
[111]set pll start
[114]periph0 has been enabled
[117]set pll end
[119][pmu]: bus read error
[122][pmu]: bus read error
[124]PMU: AXP2202
[133]vaild para:8  select dram para0
[136]board init ok

macromorgan

From b6b53dc73e3eee903cf1de745266138d7a3327d8 Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Thu, 31 Oct 2024 09:00:12 -0500
Subject: [PATCH 00/10] Misc Fixes for RGxx3

This is a series of misc fixes for the RGxx3, mostly aimed at reducing
power consumption.

Chris Morgan (10):
  arm64: dts: rockchip: Add idle-states for rk356x

macromorgan

From 21af290030161a3f8c8d6576dba1c5c3da3aca02 Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Fri, 6 Sep 2024 15:11:57 -0500
Subject: [PATCH 0/3] Anbernic RGxx3 Bootloader Fixes

Update the Anbernic RGxx3 "device" to use upstream device-trees,
add logic to detect a different vdd_cpu regulator, and implement a
fix to allow the panel auto-detection to run when using mainline
A-TF.

macromorgan

/dts-v1/;

/memreserve/	0x0000000048000000 0x0000000001000000;
/ {
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "sun50iw9";
	compatible = "allwinner,h616\0arm,sun50iw9p1";

macromorgan

[37]HELLO! BOOT0 is starting!
[40]BOOT0 commit : 749c1f9a-dirty
[43]set pll start
[45]periph0 has been enabled
[48]set pll end
[50][pmu]: bus read error
[53][pmu]: bus read error
[55]PMU: AXP2202
[63]vaild para:8  select dram para0
[67]board init ok

macromorgan

From 1340ad97d35cf4ea7b82be650530ac48bdd0ac1b Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Fri, 10 May 2024 10:43:01 -0500
Subject: [PATCH 1/4] dt-bindings: pwm: Add binding for Allwinner
 D1/T113-S3/R329/H616 PWM

Allwinner's D1, T113-S3, R329, and H616 SoCs have a new pwm
controller witch is different from the previous pwm-sun4i.

The D1 and T113 are identical in terms of peripherals,