macromorgan

From b6b53dc73e3eee903cf1de745266138d7a3327d8 Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Thu, 31 Oct 2024 09:00:12 -0500
Subject: [PATCH 00/10] Misc Fixes for RGxx3

This is a series of misc fixes for the RGxx3, mostly aimed at reducing
power consumption.

Chris Morgan (10):
  arm64: dts: rockchip: Add idle-states for rk356x

macromorgan

From 21af290030161a3f8c8d6576dba1c5c3da3aca02 Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Fri, 6 Sep 2024 15:11:57 -0500
Subject: [PATCH 0/3] Anbernic RGxx3 Bootloader Fixes

Update the Anbernic RGxx3 "device" to use upstream device-trees,
add logic to detect a different vdd_cpu regulator, and implement a
fix to allow the panel auto-detection to run when using mainline
A-TF.

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/dts-v1/;

/memreserve/	0x0000000048000000 0x0000000001000000;
/ {
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "sun50iw9";
	compatible = "allwinner,h616\0arm,sun50iw9p1";

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[37]HELLO! BOOT0 is starting!
[40]BOOT0 commit : 749c1f9a-dirty
[43]set pll start
[45]periph0 has been enabled
[48]set pll end
[50][pmu]: bus read error
[53][pmu]: bus read error
[55]PMU: AXP2202
[63]vaild para:8  select dram para0
[67]board init ok

macromorgan

From 1340ad97d35cf4ea7b82be650530ac48bdd0ac1b Mon Sep 17 00:00:00 2001
From: Chris Morgan <[email protected]>
Date: Fri, 10 May 2024 10:43:01 -0500
Subject: [PATCH 1/4] dt-bindings: pwm: Add binding for Allwinner
 D1/T113-S3/R329/H616 PWM

Allwinner's D1, T113-S3, R329, and H616 SoCs have a new pwm
controller witch is different from the previous pwm-sun4i.

The D1 and T113 are identical in terms of peripherals,

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   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 pcf8563-clkout                           0            0       32768          0 0
 pll_periph0div25m                        0            0    25000000          0 0
    ephy_25m                              0            0    25000000          0 0
 hoscdiv32k                               0            0       32768          0 0
    hosc32k                               0            0       32768          0 0
       losc_out                           0            0       32768          0 0
 osc48m                                   0            0    48000000          0 0
    osc48md4                              0            0    12000000          0 0

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/dts-v1/;

/memreserve/	0x0000000048000000 0x0000000001000000;
/ {
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "sun50iw9";
	compatible = "allwinner,h616\0arm,sun50iw9p1";

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UUUUUUIS
URS
NPK
RBS
ddr init start!!!

ddr target freq:1866 MHz

ddr init pass!!!

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load("//build/bazel_common_rules/dist:dist.bzl", "copy_to_dist_dir")
load("//build/kernel/kleaf:kernel.bzl", "kernel_build", "kernel_images", "kernel_modules_install")
load("//common:modules.bzl", "get_gki_modules_list")
load("//build/kernel/kleaf:common_kernels.bzl", "define_common_kernels")

_RGXX3_MODULE_OUTS = [
    "sound/soc/generic/snd-soc-simple-card-utils.ko",
    "drivers/input/misc/pwm-vibra.ko",
    "drivers/gpu/drm/panel/panel-newvision-nv3051d.ko",
    "drivers/char/hw_random/optee-rng.ko",

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--- SUNXI_DRAM_COM_BASE_BSP     2024-03-13 16:13:03.269292635 -0500
+++ SUNXI_DRAM_COM_BASE_MAIN    2024-03-13 16:19:14.279221980 -0500
@@ -53,10 +53,10 @@
 047fa340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 047fa350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 047fa360: 0d 06 00 08 00 03 00 02 04 00 00 00 00 00 00 00
-047fa370: 09 00 00 01 80 00 64 00 04 00 00 00 00 00 00 00
+047fa370: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00
 047fa380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 047fa390: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00