Build FPGALink on Raspberry Pi, and use it to load and readback the 16MiB SDRAM on the Aessent aes220

gistfile1.txt

Building the readback VHDL on Linux:

mkdir $HOME/20131026
cd $HOME/20131026
wget -qO- http://www.swaton.ukfsn.org/bin/makestuff-lindar-20130829.tar.gz | tar zxf -
cd makestuff/
scripts/msget.sh makestuff/hdlmake/20131026
cd hdlmake/apps
../bin/hdlmake.py -g makestuff/readback
cd makestuff/readback/vhdl/
../../../../bin/hdlmake.py -t ../templates/fx2all-ex/vhdl -b aes220
ls -l top_level.bin


Building the readback VHDL on Windows:

1) Download http://www.swaton.ukfsn.org/bin/makestuff-windows-20130829.tar.gz
2) Run setup.exe and select Xilinx ISE and Python 2.7
3) Launch the desktop shortcut
4) Continue:
cd $HOME
scripts/msget.sh makestuff/hdlmake/20131026
cd hdlmake/apps
../bin/hdlmake.py -g makestuff/readback
cd makestuff/readback/vhdl/
../../../../bin/hdlmake.py -t ../templates/fx2all-ex/vhdl -b aes220
ls -l top_level.bin


Building & testing FPGALink+aes220 on RPi:

sudo apt-get install -y libusb-1.0-0-dev libreadline6-dev
wget -qO- http://www.swaton.ukfsn.org/bin/makestuff-lindar-20130829.tar.gz | tar zxf -
cd makestuff/apps/
../scripts/msget.sh makestuff/flcli/20131026
cd flcli/
time make deps  # this takes about half an hour, so grab a coffee and come back later!

cp <location of top_level.bin copied from PC>/top_level.bin .
dd if=/dev/urandom of=random.dat bs=1024 count=16384
sudo rmmod usbtest  # needed every time, unless you have 04b4:8613 blacklisted
sudo lin.armhf/rel/flcli -i 04b4:8613 -v 1d50:602b:0002 -p XS:D0D5D1D6A7[D3?,B1+,B5+,B3+]:top_level.bin
sudo lin.armhf/rel/flcli -v 1d50:602b:0002 -a 'w0 0000000080800000;w0 "random.dat"' -b
sudo lin.armhf/rel/flcli -v 1d50:602b:0002 -a 'w0 0000000040800000;r0 1000000 "out.dat"' -b
diff random.dat out.dat