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November 22, 2015 19:33
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Build FPGALink and the cksum VHDL example, and use flcli to write data to a Basys2 board, and then read data back from it.
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Building FPGALink & the cksum example VHDL for Digilent Basys2 on Linux: | |
# Install prerequisites: | |
sudo apt-get install build-essential libreadline-dev libusb-1.0-0-dev python-yaml gcc-avr avr-libc dfu-programmer | |
mkdir $HOME/20150315 | |
cd $HOME/20150315 | |
wget -qO- http://tiny.cc/msbil | tar zxf - | |
# Fetch and build flcli: | |
cd makestuff/apps | |
../scripts/msget.sh makestuff/flcli/20150315 | |
cd flcli | |
make deps | |
# Build the AVR firmware | |
cd ../../libs/libfpgalink/firmware/avr | |
cd boards | |
cp minimus.h basys2.h | |
vi basys2.h # fix BSP (I think just #define XTAL 8000000) | |
cd .. | |
make BSP=basys2 | |
make BSP=basys2 dfu | |
# Fetch and build the VHDL version of the cksum example: | |
cd ../../../.. | |
scripts/msget.sh makestuff/hdlmake | |
cd hdlmake/apps | |
../bin/hdlmake.py -g makestuff/swled | |
cd makestuff/swled/templates/epp/boards | |
cp -rp nexys2-1200 basys2 | |
rm basys2/board-fx2lp.ucf | |
vi basys2/board.cfg # | |
vi basys2/board.ucf # configure correctly for Basys2's FPGA | |
vi basys2/board.xst # | |
cd ../../../cksum/vhdl | |
../../../../../bin/hdlmake.py -t ../../templates/epp/vhdl -b basys2 -p fpga | |
# Power up the FPGA | |
../../../../../../apps/flcli/lin.x64/rel/flcli -v 1d50:602b:0001 -d C2+ | |
# Program the FPGA: | |
../../../../../../apps/flcli/lin.x64/rel/flcli -v 1d50:602b:0001 -p J:D0D2D3D4:fpga.xsvf | |
# Write 64KiB of random data to the board: | |
dd if=/dev/urandom of=random.dat bs=1024 count=64 | |
../../../../../../apps/flcli/lin.x64/rel/flcli -v 1d50:602b:0001 -a 'w0 "random.dat";r1;r2' -b | |
# And now read 64KiB (0x10000 bytes) back from the board and save it as "out.dat": | |
../../../../../../apps/flcli/lin.x64/rel/flcli -v 1d50:602b:0001 -a 'r0 10000 "out.dat"' |
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