Build FPGALink and the cksum Verilog example, and use flcli to write data to a Digilent S3BOARD using the sync-serial conduit, and then read data back.

s3board-minimus-ss.txt

Building FPGALink & the Verilog version of the cksum example for Digilent S3BOARD on Linux:

# Physical connections (see https://i.imgur.com/TxuNx3N.jpg)

Minimus   | S3BOARD
----------+-----------------
(PD2) RXD | serData_out (E7)
(PD3) TXD | serData_in  (D6)
(PD5) XCK | serClk_in   (D5)

# Install prerequisites:
sudo apt-get install build-essential libreadline-dev libusb-1.0-0-dev python-yaml
mkdir -p $HOME/20170708
cd $HOME/20170708
wget -qO- http://tiny.cc/msbil | tar zxf -

# Fetch and build flcli:
cd makestuff/apps
../scripts/msget.sh makestuff/flcli/20170708
cd flcli
make deps
cd ../../

# Fetch and prepare to build the cksum example:
scripts/msget.sh makestuff/hdlmake
cd hdlmake/apps
../bin/hdlmake.py -g makestuff/swled
cd makestuff/swled/cksum/verilog

# Edit pin constraints in ../../templates/ss/boards/s3board/board.ucf

NET "serClk_in"       LOC="D5"   | IOSTANDARD=LVTTL | PULLUP;
NET "serData_in"      LOC="D6"   | IOSTANDARD=LVTTL | PULLUP;
NET "serData_out"     LOC="E7"   | IOSTANDARD=LVTTL;

# Run the build
../../../../../bin/hdlmake.py -t ../../templates/ss/verilog -b s3board -p fpga

# Program the FPGA:
../../../../../../apps/flcli/lin.x64/rel/flcli -v 1D50:602B -p J:B3B2B0B1:fpga.xsvf

# Write 4KiB of random data to the board:
dd if=/dev/urandom of=random.dat bs=1024 count=4
../../../../../../apps/flcli/lin.x64/rel/flcli -v 1D50:602B -c 2 -a 'w0 "random.dat";r1;r2' -b

# And now read 4KiB (0x1000 bytes) back from the board and save it as "out.dat":
../../../../../../apps/flcli/lin.x64/rel/flcli -v 1D50:602B -c 2 -a 'r0 1000 "out.dat"'