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makslevental/X86GenRegisterInfo.inc

Created April 25, 2025 20:24
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X86GenRegisterInfo.inc
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register Enum Values *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
namespace llvm {
class MCRegisterClass;
extern const MCRegisterClass X86MCRegisterClasses[];
namespace X86 {
enum : unsigned {
NoRegister,
AH = 1,
AL = 2,
AX = 3,
BH = 4,
BL = 5,
BP = 6,
BPH = 7,
BPL = 8,
BX = 9,
CH = 10,
CL = 11,
CS = 12,
CX = 13,
DF = 14,
DH = 15,
DI = 16,
DIH = 17,
DIL = 18,
DL = 19,
DS = 20,
DX = 21,
EAX = 22,
EBP = 23,
EBX = 24,
ECX = 25,
EDI = 26,
EDX = 27,
EFLAGS = 28,
EIP = 29,
EIZ = 30,
ES = 31,
ESI = 32,
ESP = 33,
FPCW = 34,
FPSW = 35,
FS = 36,
FS_BASE = 37,
GS = 38,
GS_BASE = 39,
HAX = 40,
HBP = 41,
HBX = 42,
HCX = 43,
HDI = 44,
HDX = 45,
HIP = 46,
HSI = 47,
HSP = 48,
IP = 49,
MXCSR = 50,
RAX = 51,
RBP = 52,
RBX = 53,
RCX = 54,
RDI = 55,
RDX = 56,
RFLAGS = 57,
RIP = 58,
RIZ = 59,
RSI = 60,
RSP = 61,
SI = 62,
SIH = 63,
SIL = 64,
SP = 65,
SPH = 66,
SPL = 67,
SS = 68,
SSP = 69,
_EFLAGS = 70,
CR0 = 71,
CR1 = 72,
CR2 = 73,
CR3 = 74,
CR4 = 75,
CR5 = 76,
CR6 = 77,
CR7 = 78,
CR8 = 79,
CR9 = 80,
CR10 = 81,
CR11 = 82,
CR12 = 83,
CR13 = 84,
CR14 = 85,
CR15 = 86,
DR0 = 87,
DR1 = 88,
DR2 = 89,
DR3 = 90,
DR4 = 91,
DR5 = 92,
DR6 = 93,
DR7 = 94,
DR8 = 95,
DR9 = 96,
DR10 = 97,
DR11 = 98,
DR12 = 99,
DR13 = 100,
DR14 = 101,
DR15 = 102,
FP0 = 103,
FP1 = 104,
FP2 = 105,
FP3 = 106,
FP4 = 107,
FP5 = 108,
FP6 = 109,
FP7 = 110,
MM0 = 111,
MM1 = 112,
MM2 = 113,
MM3 = 114,
MM4 = 115,
MM5 = 116,
MM6 = 117,
MM7 = 118,
R8 = 119,
R9 = 120,
R10 = 121,
R11 = 122,
R12 = 123,
R13 = 124,
R14 = 125,
R15 = 126,
ST0 = 127,
ST1 = 128,
ST2 = 129,
ST3 = 130,
ST4 = 131,
ST5 = 132,
ST6 = 133,
ST7 = 134,
XMM0 = 135,
XMM1 = 136,
XMM2 = 137,
XMM3 = 138,
XMM4 = 139,
XMM5 = 140,
XMM6 = 141,
XMM7 = 142,
XMM8 = 143,
XMM9 = 144,
XMM10 = 145,
XMM11 = 146,
XMM12 = 147,
XMM13 = 148,
XMM14 = 149,
XMM15 = 150,
R8B = 151,
R9B = 152,
R10B = 153,
R11B = 154,
R12B = 155,
R13B = 156,
R14B = 157,
R15B = 158,
R8BH = 159,
R9BH = 160,
R10BH = 161,
R11BH = 162,
R12BH = 163,
R13BH = 164,
R14BH = 165,
R15BH = 166,
R8D = 167,
R9D = 168,
R10D = 169,
R11D = 170,
R12D = 171,
R13D = 172,
R14D = 173,
R15D = 174,
R8W = 175,
R9W = 176,
R10W = 177,
R11W = 178,
R12W = 179,
R13W = 180,
R14W = 181,
R15W = 182,
R8WH = 183,
R9WH = 184,
R10WH = 185,
R11WH = 186,
R12WH = 187,
R13WH = 188,
R14WH = 189,
R15WH = 190,
YMM0 = 191,
YMM1 = 192,
YMM2 = 193,
YMM3 = 194,
YMM4 = 195,
YMM5 = 196,
YMM6 = 197,
YMM7 = 198,
YMM8 = 199,
YMM9 = 200,
YMM10 = 201,
YMM11 = 202,
YMM12 = 203,
YMM13 = 204,
YMM14 = 205,
YMM15 = 206,
K0 = 207,
K1 = 208,
K2 = 209,
K3 = 210,
K4 = 211,
K5 = 212,
K6 = 213,
K7 = 214,
XMM16 = 215,
XMM17 = 216,
XMM18 = 217,
XMM19 = 218,
XMM20 = 219,
XMM21 = 220,
XMM22 = 221,
XMM23 = 222,
XMM24 = 223,
XMM25 = 224,
XMM26 = 225,
XMM27 = 226,
XMM28 = 227,
XMM29 = 228,
XMM30 = 229,
XMM31 = 230,
YMM16 = 231,
YMM17 = 232,
YMM18 = 233,
YMM19 = 234,
YMM20 = 235,
YMM21 = 236,
YMM22 = 237,
YMM23 = 238,
YMM24 = 239,
YMM25 = 240,
YMM26 = 241,
YMM27 = 242,
YMM28 = 243,
YMM29 = 244,
YMM30 = 245,
YMM31 = 246,
ZMM0 = 247,
ZMM1 = 248,
ZMM2 = 249,
ZMM3 = 250,
ZMM4 = 251,
ZMM5 = 252,
ZMM6 = 253,
ZMM7 = 254,
ZMM8 = 255,
ZMM9 = 256,
ZMM10 = 257,
ZMM11 = 258,
ZMM12 = 259,
ZMM13 = 260,
ZMM14 = 261,
ZMM15 = 262,
ZMM16 = 263,
ZMM17 = 264,
ZMM18 = 265,
ZMM19 = 266,
ZMM20 = 267,
ZMM21 = 268,
ZMM22 = 269,
ZMM23 = 270,
ZMM24 = 271,
ZMM25 = 272,
ZMM26 = 273,
ZMM27 = 274,
ZMM28 = 275,
ZMM29 = 276,
ZMM30 = 277,
ZMM31 = 278,
K0_K1 = 279,
K2_K3 = 280,
K4_K5 = 281,
K6_K7 = 282,
TMMCFG = 283,
TMM0 = 284,
TMM1 = 285,
TMM2 = 286,
TMM3 = 287,
TMM4 = 288,
TMM5 = 289,
TMM6 = 290,
TMM7 = 291,
TMM0_TMM1 = 292,
TMM2_TMM3 = 293,
TMM4_TMM5 = 294,
TMM6_TMM7 = 295,
R16 = 296,
R17 = 297,
R18 = 298,
R19 = 299,
R20 = 300,
R21 = 301,
R22 = 302,
R23 = 303,
R24 = 304,
R25 = 305,
R26 = 306,
R27 = 307,
R28 = 308,
R29 = 309,
R30 = 310,
R31 = 311,
R16B = 312,
R17B = 313,
R18B = 314,
R19B = 315,
R20B = 316,
R21B = 317,
R22B = 318,
R23B = 319,
R24B = 320,
R25B = 321,
R26B = 322,
R27B = 323,
R28B = 324,
R29B = 325,
R30B = 326,
R31B = 327,
R16BH = 328,
R17BH = 329,
R18BH = 330,
R19BH = 331,
R20BH = 332,
R21BH = 333,
R22BH = 334,
R23BH = 335,
R24BH = 336,
R25BH = 337,
R26BH = 338,
R27BH = 339,
R28BH = 340,
R29BH = 341,
R30BH = 342,
R31BH = 343,
R16D = 344,
R17D = 345,
R18D = 346,
R19D = 347,
R20D = 348,
R21D = 349,
R22D = 350,
R23D = 351,
R24D = 352,
R25D = 353,
R26D = 354,
R27D = 355,
R28D = 356,
R29D = 357,
R30D = 358,
R31D = 359,
R16W = 360,
R17W = 361,
R18W = 362,
R19W = 363,
R20W = 364,
R21W = 365,
R22W = 366,
R23W = 367,
R24W = 368,
R25W = 369,
R26W = 370,
R27W = 371,
R28W = 372,
R29W = 373,
R30W = 374,
R31W = 375,
R16WH = 376,
R17WH = 377,
R18WH = 378,
R19WH = 379,
R20WH = 380,
R21WH = 381,
R22WH = 382,
R23WH = 383,
R24WH = 384,
R25WH = 385,
R26WH = 386,
R27WH = 387,
R28WH = 388,
R29WH = 389,
R30WH = 390,
R31WH = 391,
NUM_TARGET_REGS // 392
};
} // end namespace X86
// Register classes
namespace X86 {
enum {
GR8RegClassID = 0,
GRH8RegClassID = 1,
GR8_NOREX2RegClassID = 2,
GR8_NOREXRegClassID = 3,
GR8_ABCD_HRegClassID = 4,
GR8_ABCD_LRegClassID = 5,
GRH16RegClassID = 6,
GR16RegClassID = 7,
GR16_NOREX2RegClassID = 8,
GR16_NOREXRegClassID = 9,
VK1RegClassID = 10,
VK16RegClassID = 11,
VK2RegClassID = 12,
VK4RegClassID = 13,
VK8RegClassID = 14,
VK16WMRegClassID = 15,
VK1WMRegClassID = 16,
VK2WMRegClassID = 17,
VK4WMRegClassID = 18,
VK8WMRegClassID = 19,
SEGMENT_REGRegClassID = 20,
GR16_ABCDRegClassID = 21,
FPCCRRegClassID = 22,
FR16XRegClassID = 23,
FR16RegClassID = 24,
VK16PAIRRegClassID = 25,
VK1PAIRRegClassID = 26,
VK2PAIRRegClassID = 27,
VK4PAIRRegClassID = 28,
VK8PAIRRegClassID = 29,
VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID = 30,
LOW32_ADDR_ACCESS_RBPRegClassID = 31,
LOW32_ADDR_ACCESSRegClassID = 32,
LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 33,
FR32XRegClassID = 34,
GR32RegClassID = 35,
GR32_NOSPRegClassID = 36,
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID = 37,
DEBUG_REGRegClassID = 38,
FR32RegClassID = 39,
GR32_NOREX2RegClassID = 40,
GR32_NOREX2_NOSPRegClassID = 41,
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 42,
GR32_NOREXRegClassID = 43,
VK32RegClassID = 44,
GR32_NOREX_NOSPRegClassID = 45,
RFP32RegClassID = 46,
VK32WMRegClassID = 47,
GR32_ABCDRegClassID = 48,
GR32_TCRegClassID = 49,
GR32_ABCD_and_GR32_TCRegClassID = 50,
GR32_ADRegClassID = 51,
GR32_ArgRefRegClassID = 52,
GR32_BPSPRegClassID = 53,
GR32_BSIRegClassID = 54,
GR32_CBRegClassID = 55,
GR32_DCRegClassID = 56,
GR32_DIBPRegClassID = 57,
GR32_SIDIRegClassID = 58,
LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 59,
CCRRegClassID = 60,
DFCCRRegClassID = 61,
GR32_ABCD_and_GR32_BSIRegClassID = 62,
GR32_AD_and_GR32_ArgRefRegClassID = 63,
GR32_ArgRef_and_GR32_CBRegClassID = 64,
GR32_BPSP_and_GR32_DIBPRegClassID = 65,
GR32_BPSP_and_GR32_TCRegClassID = 66,
GR32_BSI_and_GR32_SIDIRegClassID = 67,
GR32_DIBP_and_GR32_SIDIRegClassID = 68,
LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 69,
LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 70,
RFP64RegClassID = 71,
GR64RegClassID = 72,
FR64XRegClassID = 73,
GR64_with_sub_8bitRegClassID = 74,
GR64_NOSPRegClassID = 75,
GR64_NOREX2RegClassID = 76,
CONTROL_REGRegClassID = 77,
FR64RegClassID = 78,
GR64_with_sub_16bit_in_GR16_NOREX2RegClassID = 79,
GR64_NOREX2_NOSPRegClassID = 80,
GR64PLTSafeRegClassID = 81,
GR64_TCRegClassID = 82,
GR64_NOREXRegClassID = 83,
GR64_TCW64RegClassID = 84,
GR64_TC_with_sub_8bitRegClassID = 85,
GR64_NOREX2_NOSP_and_GR64_TCRegClassID = 86,
GR64_TCW64_with_sub_8bitRegClassID = 87,
GR64_TC_and_GR64_TCW64RegClassID = 88,
GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 89,
VK64RegClassID = 90,
VR64RegClassID = 91,
GR64PLTSafe_and_GR64_TCRegClassID = 92,
GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID = 93,
GR64_NOREX_NOSPRegClassID = 94,
GR64_NOREX_and_GR64_TCRegClassID = 95,
GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 96,
VK64WMRegClassID = 97,
GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID = 98,
GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 99,
GR64PLTSafe_and_GR64_TCW64RegClassID = 100,
GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID = 101,
GR64_NOREX_and_GR64_TCW64RegClassID = 102,
GR64_ABCDRegClassID = 103,
GR64_with_sub_32bit_in_GR32_TCRegClassID = 104,
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 105,
GR64_ADRegClassID = 106,
GR64_ArgRefRegClassID = 107,
GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 108,
GR64_with_sub_32bit_in_GR32_ArgRefRegClassID = 109,
GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 110,
GR64_with_sub_32bit_in_GR32_BSIRegClassID = 111,
GR64_with_sub_32bit_in_GR32_CBRegClassID = 112,
GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 113,
GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 114,
GR64_ArgRef_and_GR64_TCRegClassID = 115,
GR64_and_LOW32_ADDR_ACCESSRegClassID = 116,
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 117,
GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID = 118,
GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID = 119,
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 120,
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 121,
GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 122,
GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 123,
RSTRegClassID = 124,
RFP80RegClassID = 125,
RFP80_7RegClassID = 126,
VR128XRegClassID = 127,
VR128RegClassID = 128,
VR256XRegClassID = 129,
VR256RegClassID = 130,
VR512RegClassID = 131,
VR512_0_15RegClassID = 132,
TILERegClassID = 133,
TILEPAIRRegClassID = 134,
};
} // end namespace X86
// Subregister indices
namespace X86 {
enum : uint16_t {
NoSubRegister,
sub_8bit, // 1
sub_8bit_hi, // 2
sub_8bit_hi_phony, // 3
sub_16bit, // 4
sub_16bit_hi, // 5
sub_32bit, // 6
sub_mask_0, // 7
sub_mask_1, // 8
sub_t0, // 9
sub_t1, // 10
sub_xmm, // 11
sub_ymm, // 12
NUM_TARGET_SUBREGS
};
} // end namespace X86
// Register pressure sets enum.
namespace X86 {
enum RegisterPressureSets {
SEGMENT_REG = 0,
GR32_BPSP = 1,
LOW32_ADDR_ACCESS_with_sub_32bit = 2,
GR32_BSI = 3,
GR32_SIDI = 4,
GR32_DIBP_with_GR32_SIDI = 5,
GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit = 6,
RFP32 = 7,
GR8_ABCD_H_with_GR32_BSI = 8,
GR8_ABCD_L_with_GR32_BSI = 9,
VK1 = 10,
VR64 = 11,
TILE = 12,
GR8_NOREX = 13,
GR32_TC = 14,
GR32_BPSP_with_GR32_TC = 15,
FR16 = 16,
DEBUG_REG = 17,
CONTROL_REG = 18,
GR64_NOREX = 19,
GR64_TCW64 = 20,
GR32_BPSP_with_GR64_TCW64 = 21,
GR64_TC_with_GR64_TCW64 = 22,
GR64_TC = 23,
FR16X = 24,
GR64PLTSafe_with_GR64_TC = 25,
GR8 = 26,
GR8_with_GR32_DIBP = 27,
GR8_with_GR32_BSI = 28,
GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit = 29,
GR8_with_GR64_NOREX = 30,
GR8_with_GR64_TCW64 = 31,
GR8_with_GR64_TC = 32,
GR8_with_GR64PLTSafe = 33,
GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 = 34,
GR16 = 35,
};
} // end namespace X86
} // end namespace llvm
#endif // GET_REGINFO_ENUM
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* MC Register Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
namespace llvm {
extern const int16_t X86RegDiffLists[] = {
/* 0 */ -56, -56, 0,
/* 3 */ -32, -48, 0,
/* 6 */ 32, -16, -48, 0,
/* 10 */ 48, -16, -48, 0,
/* 14 */ 16, -8, -48, 0,
/* 18 */ 24, -8, -48, 0,
/* 22 */ -28, 32, 2, -1, -18, 0,
/* 28 */ -32, -16, 0,
/* 31 */ -28, 30, 2, -1, -16, 0,
/* 37 */ -2, -4, 0,
/* 40 */ -29, 20, -3, 0,
/* 44 */ -4, -1, 0,
/* 47 */ -2, -1, 0,
/* 50 */ -1, -1, 0,
/* 53 */ 2, -1, 0,
/* 56 */ -72, 1, 0,
/* 59 */ -71, 1, 0,
/* 62 */ -70, 1, 0,
/* 65 */ -69, 1, 0,
/* 68 */ -8, 1, 0,
/* 71 */ -7, 1, 0,
/* 74 */ -6, 1, 0,
/* 77 */ -5, 1, 0,
/* 80 */ 1, 1, 0,
/* 83 */ 3, 0,
/* 85 */ 4, 0,
/* 87 */ 5, 0,
/* 89 */ 6, 0,
/* 91 */ 1, 7, 0,
/* 94 */ 3, 7, 0,
/* 97 */ -24, 8, 0,
/* 100 */ 1, 11, 0,
/* 103 */ 1, 14, 0,
/* 106 */ -48, 16, 0,
/* 109 */ 48, 8, -24, 8, 24, 0,
/* 115 */ -29, -10, 2, -1, 27, 0,
/* 121 */ -2, -32, 28, 0,
/* 125 */ -1, -32, 28, 0,
/* 129 */ -2, -30, 28, 0,
/* 133 */ -1, -30, 28, 0,
/* 137 */ -15, 28, 0,
/* 140 */ -20, 29, 0,
/* 143 */ -18, 29, 0,
/* 146 */ -17, 29, 0,
/* 149 */ 2, 6, 29, 0,
/* 153 */ 6, 6, 29, 0,
/* 157 */ -2, 10, 29, 0,
/* 161 */ -1, 10, 29, 0,
/* 165 */ 2, 12, 29, 0,
/* 169 */ 3, 12, 29, 0,
/* 173 */ 4, 15, 29, 0,
/* 177 */ 5, 15, 29, 0,
/* 181 */ -2, 17, 29, 0,
/* 185 */ -1, 17, 29, 0,
/* 189 */ 1, 19, 29, 0,
/* 193 */ 2, 19, 29, 0,
/* 197 */ -29, -6, -2, -4, 30, 0,
/* 203 */ 16, 32, 0,
/* 206 */ -29, -12, -2, -1, 33, 0,
/* 212 */ -29, -17, 2, -1, 34, 0,
/* 218 */ -29, -15, -4, -1, 38, 0,
/* 224 */ -29, -19, -1, -1, 39, 0,
/* 230 */ 48, 16, -48, 16, 48, 0,
/* 236 */ 56, 56, 0,
/* 239 */ 68, 0,
/* 241 */ 69, 0,
/* 243 */ 70, 0,
/* 245 */ 71, 0,
/* 247 */ 72, 0,
};
extern const LaneBitmask X86LaneMaskLists[] = {
/* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
/* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004),
/* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008),
/* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
/* 10 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008),
/* 12 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
/* 14 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080),
/* 16 */ LaneBitmask(0x0000000000000100),
/* 17 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
};
extern const uint16_t X86SubRegIdxLists[] = {
/* 0 */ 1, 2,
/* 2 */ 1, 3,
/* 4 */ 6, 4, 1, 2, 5,
/* 9 */ 6, 4, 1, 3, 5,
/* 14 */ 6, 4, 5,
/* 17 */ 7, 8,
/* 19 */ 9, 10,
/* 21 */ 12, 11,
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char X86RegStrings[] = {
/* 0 */ "XMM10\000"
/* 6 */ "YMM10\000"
/* 12 */ "ZMM10\000"
/* 18 */ "CR10\000"
/* 23 */ "DR10\000"
/* 28 */ "XMM20\000"
/* 34 */ "YMM20\000"
/* 40 */ "ZMM20\000"
/* 46 */ "R20\000"
/* 50 */ "XMM30\000"
/* 56 */ "YMM30\000"
/* 62 */ "ZMM30\000"
/* 68 */ "R30\000"
/* 72 */ "K0\000"
/* 75 */ "TMM0\000"
/* 80 */ "XMM0\000"
/* 85 */ "YMM0\000"
/* 90 */ "ZMM0\000"
/* 95 */ "FP0\000"
/* 99 */ "CR0\000"
/* 103 */ "DR0\000"
/* 107 */ "ST0\000"
/* 111 */ "XMM11\000"
/* 117 */ "YMM11\000"
/* 123 */ "ZMM11\000"
/* 129 */ "CR11\000"
/* 134 */ "DR11\000"
/* 139 */ "XMM21\000"
/* 145 */ "YMM21\000"
/* 151 */ "ZMM21\000"
/* 157 */ "R21\000"
/* 161 */ "XMM31\000"
/* 167 */ "YMM31\000"
/* 173 */ "ZMM31\000"
/* 179 */ "R31\000"
/* 183 */ "K0_K1\000"
/* 189 */ "TMM0_TMM1\000"
/* 199 */ "XMM1\000"
/* 204 */ "YMM1\000"
/* 209 */ "ZMM1\000"
/* 214 */ "FP1\000"
/* 218 */ "CR1\000"
/* 222 */ "DR1\000"
/* 226 */ "ST1\000"
/* 230 */ "XMM12\000"
/* 236 */ "YMM12\000"
/* 242 */ "ZMM12\000"
/* 248 */ "CR12\000"
/* 253 */ "DR12\000"
/* 258 */ "XMM22\000"
/* 264 */ "YMM22\000"
/* 270 */ "ZMM22\000"
/* 276 */ "R22\000"
/* 280 */ "K2\000"
/* 283 */ "TMM2\000"
/* 288 */ "XMM2\000"
/* 293 */ "YMM2\000"
/* 298 */ "ZMM2\000"
/* 303 */ "FP2\000"
/* 307 */ "CR2\000"
/* 311 */ "DR2\000"
/* 315 */ "ST2\000"
/* 319 */ "XMM13\000"
/* 325 */ "YMM13\000"
/* 331 */ "ZMM13\000"
/* 337 */ "CR13\000"
/* 342 */ "DR13\000"
/* 347 */ "XMM23\000"
/* 353 */ "YMM23\000"
/* 359 */ "ZMM23\000"
/* 365 */ "R23\000"
/* 369 */ "K2_K3\000"
/* 375 */ "TMM2_TMM3\000"
/* 385 */ "XMM3\000"
/* 390 */ "YMM3\000"
/* 395 */ "ZMM3\000"
/* 400 */ "FP3\000"
/* 404 */ "CR3\000"
/* 408 */ "DR3\000"
/* 412 */ "ST3\000"
/* 416 */ "XMM14\000"
/* 422 */ "YMM14\000"
/* 428 */ "ZMM14\000"
/* 434 */ "CR14\000"
/* 439 */ "DR14\000"
/* 444 */ "XMM24\000"
/* 450 */ "YMM24\000"
/* 456 */ "ZMM24\000"
/* 462 */ "R24\000"
/* 466 */ "K4\000"
/* 469 */ "TMM4\000"
/* 474 */ "XMM4\000"
/* 479 */ "YMM4\000"
/* 484 */ "ZMM4\000"
/* 489 */ "FP4\000"
/* 493 */ "CR4\000"
/* 497 */ "DR4\000"
/* 501 */ "ST4\000"
/* 505 */ "XMM15\000"
/* 511 */ "YMM15\000"
/* 517 */ "ZMM15\000"
/* 523 */ "CR15\000"
/* 528 */ "DR15\000"
/* 533 */ "XMM25\000"
/* 539 */ "YMM25\000"
/* 545 */ "ZMM25\000"
/* 551 */ "R25\000"
/* 555 */ "K4_K5\000"
/* 561 */ "TMM4_TMM5\000"
/* 571 */ "XMM5\000"
/* 576 */ "YMM5\000"
/* 581 */ "ZMM5\000"
/* 586 */ "FP5\000"
/* 590 */ "CR5\000"
/* 594 */ "DR5\000"
/* 598 */ "ST5\000"
/* 602 */ "XMM16\000"
/* 608 */ "YMM16\000"
/* 614 */ "ZMM16\000"
/* 620 */ "R16\000"
/* 624 */ "XMM26\000"
/* 630 */ "YMM26\000"
/* 636 */ "ZMM26\000"
/* 642 */ "R26\000"
/* 646 */ "K6\000"
/* 649 */ "TMM6\000"
/* 654 */ "XMM6\000"
/* 659 */ "YMM6\000"
/* 664 */ "ZMM6\000"
/* 669 */ "FP6\000"
/* 673 */ "CR6\000"
/* 677 */ "DR6\000"
/* 681 */ "ST6\000"
/* 685 */ "XMM17\000"
/* 691 */ "YMM17\000"
/* 697 */ "ZMM17\000"
/* 703 */ "R17\000"
/* 707 */ "XMM27\000"
/* 713 */ "YMM27\000"
/* 719 */ "ZMM27\000"
/* 725 */ "R27\000"
/* 729 */ "K6_K7\000"
/* 735 */ "TMM6_TMM7\000"
/* 745 */ "XMM7\000"
/* 750 */ "YMM7\000"
/* 755 */ "ZMM7\000"
/* 760 */ "FP7\000"
/* 764 */ "CR7\000"
/* 768 */ "DR7\000"
/* 772 */ "ST7\000"
/* 776 */ "XMM18\000"
/* 782 */ "YMM18\000"
/* 788 */ "ZMM18\000"
/* 794 */ "R18\000"
/* 798 */ "XMM28\000"
/* 804 */ "YMM28\000"
/* 810 */ "ZMM28\000"
/* 816 */ "R28\000"
/* 820 */ "XMM8\000"
/* 825 */ "YMM8\000"
/* 830 */ "ZMM8\000"
/* 835 */ "CR8\000"
/* 839 */ "DR8\000"
/* 843 */ "XMM19\000"
/* 849 */ "YMM19\000"
/* 855 */ "ZMM19\000"
/* 861 */ "R19\000"
/* 865 */ "XMM29\000"
/* 871 */ "YMM29\000"
/* 877 */ "ZMM29\000"
/* 883 */ "R29\000"
/* 887 */ "XMM9\000"
/* 892 */ "YMM9\000"
/* 897 */ "ZMM9\000"
/* 902 */ "CR9\000"
/* 906 */ "DR9\000"
/* 910 */ "R10B\000"
/* 915 */ "R20B\000"
/* 920 */ "R30B\000"
/* 925 */ "R11B\000"
/* 930 */ "R21B\000"
/* 935 */ "R31B\000"
/* 940 */ "R12B\000"
/* 945 */ "R22B\000"
/* 950 */ "R13B\000"
/* 955 */ "R23B\000"
/* 960 */ "R14B\000"
/* 965 */ "R24B\000"
/* 970 */ "R15B\000"
/* 975 */ "R25B\000"
/* 980 */ "R16B\000"
/* 985 */ "R26B\000"
/* 990 */ "R17B\000"
/* 995 */ "R27B\000"
/* 1000 */ "R18B\000"
/* 1005 */ "R28B\000"
/* 1010 */ "R8B\000"
/* 1014 */ "R19B\000"
/* 1019 */ "R29B\000"
/* 1024 */ "R9B\000"
/* 1028 */ "R10D\000"
/* 1033 */ "R20D\000"
/* 1038 */ "R30D\000"
/* 1043 */ "R11D\000"
/* 1048 */ "R21D\000"
/* 1053 */ "R31D\000"
/* 1058 */ "R12D\000"
/* 1063 */ "R22D\000"
/* 1068 */ "R13D\000"
/* 1073 */ "R23D\000"
/* 1078 */ "R14D\000"
/* 1083 */ "R24D\000"
/* 1088 */ "R15D\000"
/* 1093 */ "R25D\000"
/* 1098 */ "R16D\000"
/* 1103 */ "R26D\000"
/* 1108 */ "R17D\000"
/* 1113 */ "R27D\000"
/* 1118 */ "R18D\000"
/* 1123 */ "R28D\000"
/* 1128 */ "R8D\000"
/* 1132 */ "R19D\000"
/* 1137 */ "R29D\000"
/* 1142 */ "R9D\000"
/* 1146 */ "FS_BASE\000"
/* 1154 */ "GS_BASE\000"
/* 1162 */ "DF\000"
/* 1165 */ "TMMCFG\000"
/* 1172 */ "AH\000"
/* 1175 */ "R10BH\000"
/* 1181 */ "R20BH\000"
/* 1187 */ "R30BH\000"
/* 1193 */ "R11BH\000"
/* 1199 */ "R21BH\000"
/* 1205 */ "R31BH\000"
/* 1211 */ "R12BH\000"
/* 1217 */ "R22BH\000"
/* 1223 */ "R13BH\000"
/* 1229 */ "R23BH\000"
/* 1235 */ "R14BH\000"
/* 1241 */ "R24BH\000"
/* 1247 */ "R15BH\000"
/* 1253 */ "R25BH\000"
/* 1259 */ "R16BH\000"
/* 1265 */ "R26BH\000"
/* 1271 */ "R17BH\000"
/* 1277 */ "R27BH\000"
/* 1283 */ "R18BH\000"
/* 1289 */ "R28BH\000"
/* 1295 */ "R8BH\000"
/* 1300 */ "R19BH\000"
/* 1306 */ "R29BH\000"
/* 1312 */ "R9BH\000"
/* 1317 */ "CH\000"
/* 1320 */ "DH\000"
/* 1323 */ "DIH\000"
/* 1327 */ "SIH\000"
/* 1331 */ "BPH\000"
/* 1335 */ "SPH\000"
/* 1339 */ "R10WH\000"
/* 1345 */ "R20WH\000"
/* 1351 */ "R30WH\000"
/* 1357 */ "R11WH\000"
/* 1363 */ "R21WH\000"
/* 1369 */ "R31WH\000"
/* 1375 */ "R12WH\000"
/* 1381 */ "R22WH\000"
/* 1387 */ "R13WH\000"
/* 1393 */ "R23WH\000"
/* 1399 */ "R14WH\000"
/* 1405 */ "R24WH\000"
/* 1411 */ "R15WH\000"
/* 1417 */ "R25WH\000"
/* 1423 */ "R16WH\000"
/* 1429 */ "R26WH\000"
/* 1435 */ "R17WH\000"
/* 1441 */ "R27WH\000"
/* 1447 */ "R18WH\000"
/* 1453 */ "R28WH\000"
/* 1459 */ "R8WH\000"
/* 1464 */ "R19WH\000"
/* 1470 */ "R29WH\000"
/* 1476 */ "R9WH\000"
/* 1481 */ "EDI\000"
/* 1485 */ "HDI\000"
/* 1489 */ "RDI\000"
/* 1493 */ "ESI\000"
/* 1497 */ "HSI\000"
/* 1501 */ "RSI\000"
/* 1505 */ "AL\000"
/* 1508 */ "BL\000"
/* 1511 */ "CL\000"
/* 1514 */ "DL\000"
/* 1517 */ "DIL\000"
/* 1521 */ "SIL\000"
/* 1525 */ "BPL\000"
/* 1529 */ "SPL\000"
/* 1533 */ "EBP\000"
/* 1537 */ "HBP\000"
/* 1541 */ "RBP\000"
/* 1545 */ "EIP\000"
/* 1549 */ "HIP\000"
/* 1553 */ "RIP\000"
/* 1557 */ "ESP\000"
/* 1561 */ "HSP\000"
/* 1565 */ "RSP\000"
/* 1569 */ "SSP\000"
/* 1573 */ "MXCSR\000"
/* 1579 */ "CS\000"
/* 1582 */ "DS\000"
/* 1585 */ "ES\000"
/* 1588 */ "FS\000"
/* 1591 */ "_EFLAGS\000"
/* 1599 */ "RFLAGS\000"
/* 1606 */ "SS\000"
/* 1609 */ "R10W\000"
/* 1614 */ "R20W\000"
/* 1619 */ "R30W\000"
/* 1624 */ "R11W\000"
/* 1629 */ "R21W\000"
/* 1634 */ "R31W\000"
/* 1639 */ "R12W\000"
/* 1644 */ "R22W\000"
/* 1649 */ "R13W\000"
/* 1654 */ "R23W\000"
/* 1659 */ "R14W\000"
/* 1664 */ "R24W\000"
/* 1669 */ "R15W\000"
/* 1674 */ "R25W\000"
/* 1679 */ "R16W\000"
/* 1684 */ "R26W\000"
/* 1689 */ "R17W\000"
/* 1694 */ "R27W\000"
/* 1699 */ "R18W\000"
/* 1704 */ "R28W\000"
/* 1709 */ "R8W\000"
/* 1713 */ "R19W\000"
/* 1718 */ "R29W\000"
/* 1723 */ "R9W\000"
/* 1727 */ "FPCW\000"
/* 1732 */ "FPSW\000"
/* 1737 */ "EAX\000"
/* 1741 */ "HAX\000"
/* 1745 */ "RAX\000"
/* 1749 */ "EBX\000"
/* 1753 */ "HBX\000"
/* 1757 */ "RBX\000"
/* 1761 */ "ECX\000"
/* 1765 */ "HCX\000"
/* 1769 */ "RCX\000"
/* 1773 */ "EDX\000"
/* 1777 */ "HDX\000"
/* 1781 */ "RDX\000"
/* 1785 */ "EIZ\000"
/* 1789 */ "RIZ\000"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
{ 5, 0, 0, 0, 0, 0, 0, 0 },
{ 1172, 2, 193, 2, 8192, 17, 0, 0 },
{ 1505, 2, 189, 2, 8193, 17, 0, 0 },
{ 1738, 50, 190, 0, 233472, 0, 0, 0 },
{ 1178, 2, 177, 2, 8194, 17, 0, 0 },
{ 1508, 2, 173, 2, 8195, 17, 0, 0 },
{ 1534, 53, 182, 2, 233476, 2, 0, 0 },
{ 1331, 2, 185, 2, 8197, 17, 0, 1 },
{ 1525, 2, 181, 2, 8196, 17, 0, 0 },
{ 1750, 44, 174, 0, 233474, 0, 0, 0 },
{ 1317, 2, 169, 2, 8198, 17, 0, 0 },
{ 1511, 2, 165, 2, 8199, 17, 0, 0 },
{ 1579, 2, 2, 2, 8200, 17, 0, 0 },
{ 1762, 47, 166, 0, 233478, 0, 0, 0 },
{ 1162, 2, 2, 2, 8201, 17, 0, 0 },
{ 1320, 2, 153, 2, 8202, 17, 0, 0 },
{ 1482, 53, 158, 2, 233483, 2, 0, 0 },
{ 1323, 2, 161, 2, 8204, 17, 0, 1 },
{ 1517, 2, 157, 2, 8203, 17, 0, 0 },
{ 1514, 2, 149, 2, 8205, 17, 0, 0 },
{ 1582, 2, 2, 2, 8206, 17, 0, 0 },
{ 1774, 37, 150, 0, 339978, 0, 0, 0 },
{ 1737, 225, 141, 5, 421888, 4, 0, 0 },
{ 1533, 213, 141, 10, 409604, 7, 0, 0 },
{ 1749, 219, 141, 5, 421890, 4, 0, 0 },
{ 1761, 207, 141, 5, 409606, 4, 0, 0 },
{ 1481, 116, 141, 10, 372747, 7, 0, 0 },
{ 1773, 198, 141, 5, 385034, 4, 0, 0 },
{ 1592, 2, 2, 2, 8213, 17, 0, 0 },
{ 1545, 41, 141, 15, 233494, 10, 0, 0 },
{ 1785, 2, 2, 2, 8216, 17, 0, 0 },
{ 1585, 2, 2, 2, 8217, 17, 0, 0 },
{ 1493, 32, 123, 10, 327706, 7, 0, 0 },
{ 1557, 23, 123, 10, 327709, 7, 0, 0 },
{ 1727, 2, 2, 2, 8224, 17, 0, 0 },
{ 1732, 2, 2, 2, 8225, 17, 0, 0 },
{ 1588, 2, 2, 2, 8226, 17, 0, 0 },
{ 1146, 2, 2, 2, 8227, 17, 0, 0 },
{ 1596, 2, 2, 2, 8228, 17, 0, 0 },
{ 1154, 2, 2, 2, 8229, 17, 0, 0 },
{ 1741, 2, 143, 2, 8207, 17, 0, 1 },
{ 1537, 2, 143, 2, 8208, 17, 0, 1 },
{ 1753, 2, 143, 2, 8209, 17, 0, 1 },
{ 1765, 2, 143, 2, 8210, 17, 0, 1 },
{ 1485, 2, 143, 2, 8211, 17, 0, 1 },
{ 1777, 2, 143, 2, 8212, 17, 0, 1 },
{ 1549, 2, 146, 2, 8215, 17, 0, 1 },
{ 1497, 2, 137, 2, 8220, 17, 0, 1 },
{ 1561, 2, 137, 2, 8223, 17, 0, 1 },
{ 1546, 2, 140, 2, 8214, 17, 0, 0 },
{ 1573, 2, 2, 2, 8230, 17, 0, 0 },
{ 1745, 224, 2, 4, 421888, 4, 0, 0 },
{ 1541, 212, 2, 9, 409604, 7, 0, 0 },
{ 1757, 218, 2, 4, 421890, 4, 0, 0 },
{ 1769, 206, 2, 4, 409606, 4, 0, 0 },
{ 1489, 115, 2, 9, 372747, 7, 0, 0 },
{ 1781, 197, 2, 4, 385034, 4, 0, 0 },
{ 1599, 2, 2, 2, 8231, 17, 0, 0 },
{ 1553, 40, 2, 14, 233494, 10, 0, 0 },
{ 1789, 2, 2, 2, 8232, 17, 0, 0 },
{ 1501, 31, 2, 9, 327706, 7, 0, 0 },
{ 1565, 22, 2, 9, 327709, 7, 0, 0 },
{ 1494, 53, 130, 2, 233498, 2, 0, 0 },
{ 1327, 2, 133, 2, 8219, 17, 0, 1 },
{ 1521, 2, 129, 2, 8218, 17, 0, 0 },
{ 1558, 53, 122, 2, 233501, 2, 0, 0 },
{ 1335, 2, 125, 2, 8222, 17, 0, 1 },
{ 1529, 2, 121, 2, 8221, 17, 0, 0 },
{ 1606, 2, 2, 2, 8233, 17, 0, 0 },
{ 1569, 2, 2, 2, 8234, 17, 0, 0 },
{ 1591, 2, 2, 2, 8235, 17, 0, 0 },
{ 99, 2, 2, 2, 8236, 17, 0, 0 },
{ 218, 2, 2, 2, 8237, 17, 0, 0 },
{ 307, 2, 2, 2, 8238, 17, 0, 0 },
{ 404, 2, 2, 2, 8239, 17, 0, 0 },
{ 493, 2, 2, 2, 8240, 17, 0, 0 },
{ 590, 2, 2, 2, 8241, 17, 0, 0 },
{ 673, 2, 2, 2, 8242, 17, 0, 0 },
{ 764, 2, 2, 2, 8243, 17, 0, 0 },
{ 835, 2, 2, 2, 8244, 17, 0, 0 },
{ 902, 2, 2, 2, 8245, 17, 0, 0 },
{ 18, 2, 2, 2, 8246, 17, 0, 0 },
{ 129, 2, 2, 2, 8247, 17, 0, 0 },
{ 248, 2, 2, 2, 8248, 17, 0, 0 },
{ 337, 2, 2, 2, 8249, 17, 0, 0 },
{ 434, 2, 2, 2, 8250, 17, 0, 0 },
{ 523, 2, 2, 2, 8251, 17, 0, 0 },
{ 103, 2, 2, 2, 8252, 17, 0, 0 },
{ 222, 2, 2, 2, 8253, 17, 0, 0 },
{ 311, 2, 2, 2, 8254, 17, 0, 0 },
{ 408, 2, 2, 2, 8255, 17, 0, 0 },
{ 497, 2, 2, 2, 8256, 17, 0, 0 },
{ 594, 2, 2, 2, 8257, 17, 0, 0 },
{ 677, 2, 2, 2, 8258, 17, 0, 0 },
{ 768, 2, 2, 2, 8259, 17, 0, 0 },
{ 839, 2, 2, 2, 8260, 17, 0, 0 },
{ 906, 2, 2, 2, 8261, 17, 0, 0 },
{ 23, 2, 2, 2, 8262, 17, 0, 0 },
{ 134, 2, 2, 2, 8263, 17, 0, 0 },
{ 253, 2, 2, 2, 8264, 17, 0, 0 },
{ 342, 2, 2, 2, 8265, 17, 0, 0 },
{ 439, 2, 2, 2, 8266, 17, 0, 0 },
{ 528, 2, 2, 2, 8267, 17, 0, 0 },
{ 95, 2, 2, 2, 8268, 17, 0, 0 },
{ 214, 2, 2, 2, 8269, 17, 0, 0 },
{ 303, 2, 2, 2, 8270, 17, 0, 0 },
{ 400, 2, 2, 2, 8271, 17, 0, 0 },
{ 489, 2, 2, 2, 8272, 17, 0, 0 },
{ 586, 2, 2, 2, 8273, 17, 0, 0 },
{ 669, 2, 2, 2, 8274, 17, 0, 0 },
{ 760, 2, 2, 2, 8275, 17, 0, 0 },
{ 76, 2, 2, 2, 8276, 17, 0, 0 },
{ 195, 2, 2, 2, 8277, 17, 0, 0 },
{ 284, 2, 2, 2, 8278, 17, 0, 0 },
{ 381, 2, 2, 2, 8279, 17, 0, 0 },
{ 470, 2, 2, 2, 8280, 17, 0, 0 },
{ 567, 2, 2, 2, 8281, 17, 0, 0 },
{ 650, 2, 2, 2, 8282, 17, 0, 0 },
{ 741, 2, 2, 2, 8283, 17, 0, 0 },
{ 836, 109, 2, 9, 327772, 7, 0, 0 },
{ 903, 109, 2, 9, 327775, 7, 0, 0 },
{ 19, 109, 2, 9, 327778, 7, 0, 0 },
{ 130, 109, 2, 9, 327781, 7, 0, 0 },
{ 249, 109, 2, 9, 327784, 7, 0, 0 },
{ 338, 109, 2, 9, 327787, 7, 0, 0 },
{ 435, 109, 2, 9, 327790, 7, 0, 0 },
{ 524, 109, 2, 9, 327793, 7, 0, 0 },
{ 107, 2, 2, 2, 8308, 17, 0, 0 },
{ 226, 2, 2, 2, 8309, 17, 0, 0 },
{ 315, 2, 2, 2, 8310, 17, 0, 0 },
{ 412, 2, 2, 2, 8311, 17, 0, 0 },
{ 501, 2, 2, 2, 8312, 17, 0, 0 },
{ 598, 2, 2, 2, 8313, 17, 0, 0 },
{ 681, 2, 2, 2, 8314, 17, 0, 0 },
{ 772, 2, 2, 2, 8315, 17, 0, 0 },
{ 80, 2, 236, 2, 8316, 17, 0, 0 },
{ 199, 2, 236, 2, 8317, 17, 0, 0 },
{ 288, 2, 236, 2, 8318, 17, 0, 0 },
{ 385, 2, 236, 2, 8319, 17, 0, 0 },
{ 474, 2, 236, 2, 8320, 17, 0, 0 },
{ 571, 2, 236, 2, 8321, 17, 0, 0 },
{ 654, 2, 236, 2, 8322, 17, 0, 0 },
{ 745, 2, 236, 2, 8323, 17, 0, 0 },
{ 820, 2, 236, 2, 8324, 17, 0, 0 },
{ 887, 2, 236, 2, 8325, 17, 0, 0 },
{ 0, 2, 236, 2, 8326, 17, 0, 0 },
{ 111, 2, 236, 2, 8327, 17, 0, 0 },
{ 230, 2, 236, 2, 8328, 17, 0, 0 },
{ 319, 2, 236, 2, 8329, 17, 0, 0 },
{ 416, 2, 236, 2, 8330, 17, 0, 0 },
{ 505, 2, 236, 2, 8331, 17, 0, 0 },
{ 1010, 2, 18, 2, 8284, 17, 0, 0 },
{ 1024, 2, 18, 2, 8287, 17, 0, 0 },
{ 910, 2, 18, 2, 8290, 17, 0, 0 },
{ 925, 2, 18, 2, 8293, 17, 0, 0 },
{ 940, 2, 18, 2, 8296, 17, 0, 0 },
{ 950, 2, 18, 2, 8299, 17, 0, 0 },
{ 960, 2, 18, 2, 8302, 17, 0, 0 },
{ 970, 2, 18, 2, 8305, 17, 0, 0 },
{ 1295, 2, 14, 2, 8285, 17, 0, 1 },
{ 1312, 2, 14, 2, 8288, 17, 0, 1 },
{ 1175, 2, 14, 2, 8291, 17, 0, 1 },
{ 1193, 2, 14, 2, 8294, 17, 0, 1 },
{ 1211, 2, 14, 2, 8297, 17, 0, 1 },
{ 1223, 2, 14, 2, 8300, 17, 0, 1 },
{ 1235, 2, 14, 2, 8303, 17, 0, 1 },
{ 1247, 2, 14, 2, 8306, 17, 0, 1 },
{ 1128, 110, 4, 10, 327772, 7, 0, 0 },
{ 1142, 110, 4, 10, 327775, 7, 0, 0 },
{ 1028, 110, 4, 10, 327778, 7, 0, 0 },
{ 1043, 110, 4, 10, 327781, 7, 0, 0 },
{ 1058, 110, 4, 10, 327784, 7, 0, 0 },
{ 1068, 110, 4, 10, 327787, 7, 0, 0 },
{ 1078, 110, 4, 10, 327790, 7, 0, 0 },
{ 1088, 110, 4, 10, 327793, 7, 0, 0 },
{ 1709, 97, 15, 2, 233564, 2, 0, 0 },
{ 1723, 97, 15, 2, 233567, 2, 0, 0 },
{ 1609, 97, 15, 2, 233570, 2, 0, 0 },
{ 1624, 97, 15, 2, 233573, 2, 0, 0 },
{ 1639, 97, 15, 2, 233576, 2, 0, 0 },
{ 1649, 97, 15, 2, 233579, 2, 0, 0 },
{ 1659, 97, 15, 2, 233582, 2, 0, 0 },
{ 1669, 97, 15, 2, 233585, 2, 0, 0 },
{ 1459, 2, 7, 2, 8286, 17, 0, 1 },
{ 1476, 2, 7, 2, 8289, 17, 0, 1 },
{ 1339, 2, 7, 2, 8292, 17, 0, 1 },
{ 1357, 2, 7, 2, 8295, 17, 0, 1 },
{ 1375, 2, 7, 2, 8298, 17, 0, 1 },
{ 1387, 2, 7, 2, 8301, 17, 0, 1 },
{ 1399, 2, 7, 2, 8304, 17, 0, 1 },
{ 1411, 2, 7, 2, 8307, 17, 0, 1 },
{ 85, 1, 237, 22, 8316, 16, 0, 0 },
{ 204, 1, 237, 22, 8317, 16, 0, 0 },
{ 293, 1, 237, 22, 8318, 16, 0, 0 },
{ 390, 1, 237, 22, 8319, 16, 0, 0 },
{ 479, 1, 237, 22, 8320, 16, 0, 0 },
{ 576, 1, 237, 22, 8321, 16, 0, 0 },
{ 659, 1, 237, 22, 8322, 16, 0, 0 },
{ 750, 1, 237, 22, 8323, 16, 0, 0 },
{ 825, 1, 237, 22, 8324, 16, 0, 0 },
{ 892, 1, 237, 22, 8325, 16, 0, 0 },
{ 6, 1, 237, 22, 8326, 16, 0, 0 },
{ 117, 1, 237, 22, 8327, 16, 0, 0 },
{ 236, 1, 237, 22, 8328, 16, 0, 0 },
{ 325, 1, 237, 22, 8329, 16, 0, 0 },
{ 422, 1, 237, 22, 8330, 16, 0, 0 },
{ 511, 1, 237, 22, 8331, 16, 0, 0 },
{ 72, 2, 247, 2, 8332, 17, 0, 0 },
{ 186, 2, 245, 2, 8333, 17, 0, 0 },
{ 280, 2, 245, 2, 8334, 17, 0, 0 },
{ 372, 2, 243, 2, 8335, 17, 0, 0 },
{ 466, 2, 243, 2, 8336, 17, 0, 0 },
{ 558, 2, 241, 2, 8337, 17, 0, 0 },
{ 646, 2, 241, 2, 8338, 17, 0, 0 },
{ 732, 2, 239, 2, 8339, 17, 0, 0 },
{ 602, 2, 203, 2, 8340, 17, 0, 0 },
{ 685, 2, 203, 2, 8341, 17, 0, 0 },
{ 776, 2, 203, 2, 8342, 17, 0, 0 },
{ 843, 2, 203, 2, 8343, 17, 0, 0 },
{ 28, 2, 203, 2, 8344, 17, 0, 0 },
{ 139, 2, 203, 2, 8345, 17, 0, 0 },
{ 258, 2, 203, 2, 8346, 17, 0, 0 },
{ 347, 2, 203, 2, 8347, 17, 0, 0 },
{ 444, 2, 203, 2, 8348, 17, 0, 0 },
{ 533, 2, 203, 2, 8349, 17, 0, 0 },
{ 624, 2, 203, 2, 8350, 17, 0, 0 },
{ 707, 2, 203, 2, 8351, 17, 0, 0 },
{ 798, 2, 203, 2, 8352, 17, 0, 0 },
{ 865, 2, 203, 2, 8353, 17, 0, 0 },
{ 50, 2, 203, 2, 8354, 17, 0, 0 },
{ 161, 2, 203, 2, 8355, 17, 0, 0 },
{ 608, 29, 204, 22, 8340, 16, 0, 0 },
{ 691, 29, 204, 22, 8341, 16, 0, 0 },
{ 782, 29, 204, 22, 8342, 16, 0, 0 },
{ 849, 29, 204, 22, 8343, 16, 0, 0 },
{ 34, 29, 204, 22, 8344, 16, 0, 0 },
{ 145, 29, 204, 22, 8345, 16, 0, 0 },
{ 264, 29, 204, 22, 8346, 16, 0, 0 },
{ 353, 29, 204, 22, 8347, 16, 0, 0 },
{ 450, 29, 204, 22, 8348, 16, 0, 0 },
{ 539, 29, 204, 22, 8349, 16, 0, 0 },
{ 630, 29, 204, 22, 8350, 16, 0, 0 },
{ 713, 29, 204, 22, 8351, 16, 0, 0 },
{ 804, 29, 204, 22, 8352, 16, 0, 0 },
{ 871, 29, 204, 22, 8353, 16, 0, 0 },
{ 56, 29, 204, 22, 8354, 16, 0, 0 },
{ 167, 29, 204, 22, 8355, 16, 0, 0 },
{ 90, 0, 2, 21, 8316, 16, 0, 0 },
{ 209, 0, 2, 21, 8317, 16, 0, 0 },
{ 298, 0, 2, 21, 8318, 16, 0, 0 },
{ 395, 0, 2, 21, 8319, 16, 0, 0 },
{ 484, 0, 2, 21, 8320, 16, 0, 0 },
{ 581, 0, 2, 21, 8321, 16, 0, 0 },
{ 664, 0, 2, 21, 8322, 16, 0, 0 },
{ 755, 0, 2, 21, 8323, 16, 0, 0 },
{ 830, 0, 2, 21, 8324, 16, 0, 0 },
{ 897, 0, 2, 21, 8325, 16, 0, 0 },
{ 12, 0, 2, 21, 8326, 16, 0, 0 },
{ 123, 0, 2, 21, 8327, 16, 0, 0 },
{ 242, 0, 2, 21, 8328, 16, 0, 0 },
{ 331, 0, 2, 21, 8329, 16, 0, 0 },
{ 428, 0, 2, 21, 8330, 16, 0, 0 },
{ 517, 0, 2, 21, 8331, 16, 0, 0 },
{ 614, 28, 2, 21, 8340, 16, 0, 0 },
{ 697, 28, 2, 21, 8341, 16, 0, 0 },
{ 788, 28, 2, 21, 8342, 16, 0, 0 },
{ 855, 28, 2, 21, 8343, 16, 0, 0 },
{ 40, 28, 2, 21, 8344, 16, 0, 0 },
{ 151, 28, 2, 21, 8345, 16, 0, 0 },
{ 270, 28, 2, 21, 8346, 16, 0, 0 },
{ 359, 28, 2, 21, 8347, 16, 0, 0 },
{ 456, 28, 2, 21, 8348, 16, 0, 0 },
{ 545, 28, 2, 21, 8349, 16, 0, 0 },
{ 636, 28, 2, 21, 8350, 16, 0, 0 },
{ 719, 28, 2, 21, 8351, 16, 0, 0 },
{ 810, 28, 2, 21, 8352, 16, 0, 0 },
{ 877, 28, 2, 21, 8353, 16, 0, 0 },
{ 62, 28, 2, 21, 8354, 16, 0, 0 },
{ 173, 28, 2, 21, 8355, 16, 0, 0 },
{ 183, 56, 2, 17, 233612, 12, 0, 0 },
{ 369, 59, 2, 17, 233614, 12, 0, 0 },
{ 555, 62, 2, 17, 233616, 12, 0, 0 },
{ 729, 65, 2, 17, 233618, 12, 0, 0 },
{ 1165, 2, 2, 2, 8356, 17, 0, 0 },
{ 75, 2, 98, 2, 8357, 17, 0, 0 },
{ 194, 2, 92, 2, 8358, 17, 0, 0 },
{ 283, 2, 92, 2, 8359, 17, 0, 0 },
{ 380, 2, 89, 2, 8360, 17, 0, 0 },
{ 469, 2, 89, 2, 8361, 17, 0, 0 },
{ 566, 2, 87, 2, 8362, 17, 0, 0 },
{ 649, 2, 87, 2, 8363, 17, 0, 0 },
{ 740, 2, 85, 2, 8364, 17, 0, 0 },
{ 189, 68, 2, 19, 233637, 14, 0, 0 },
{ 375, 71, 2, 19, 233639, 14, 0, 0 },
{ 561, 74, 2, 19, 233641, 14, 0, 0 },
{ 735, 77, 2, 19, 233643, 14, 0, 0 },
{ 620, 230, 2, 9, 327853, 7, 0, 0 },
{ 703, 230, 2, 9, 327856, 7, 0, 0 },
{ 794, 230, 2, 9, 327859, 7, 0, 0 },
{ 861, 230, 2, 9, 327862, 7, 0, 0 },
{ 46, 230, 2, 9, 327865, 7, 0, 0 },
{ 157, 230, 2, 9, 327868, 7, 0, 0 },
{ 276, 230, 2, 9, 327871, 7, 0, 0 },
{ 365, 230, 2, 9, 327874, 7, 0, 0 },
{ 462, 230, 2, 9, 327877, 7, 0, 0 },
{ 551, 230, 2, 9, 327880, 7, 0, 0 },
{ 642, 230, 2, 9, 327883, 7, 0, 0 },
{ 725, 230, 2, 9, 327886, 7, 0, 0 },
{ 816, 230, 2, 9, 327889, 7, 0, 0 },
{ 883, 230, 2, 9, 327892, 7, 0, 0 },
{ 68, 230, 2, 9, 327895, 7, 0, 0 },
{ 179, 230, 2, 9, 327898, 7, 0, 0 },
{ 980, 2, 10, 2, 8365, 17, 0, 0 },
{ 990, 2, 10, 2, 8368, 17, 0, 0 },
{ 1000, 2, 10, 2, 8371, 17, 0, 0 },
{ 1014, 2, 10, 2, 8374, 17, 0, 0 },
{ 915, 2, 10, 2, 8377, 17, 0, 0 },
{ 930, 2, 10, 2, 8380, 17, 0, 0 },
{ 945, 2, 10, 2, 8383, 17, 0, 0 },
{ 955, 2, 10, 2, 8386, 17, 0, 0 },
{ 965, 2, 10, 2, 8389, 17, 0, 0 },
{ 975, 2, 10, 2, 8392, 17, 0, 0 },
{ 985, 2, 10, 2, 8395, 17, 0, 0 },
{ 995, 2, 10, 2, 8398, 17, 0, 0 },
{ 1005, 2, 10, 2, 8401, 17, 0, 0 },
{ 1019, 2, 10, 2, 8404, 17, 0, 0 },
{ 920, 2, 10, 2, 8407, 17, 0, 0 },
{ 935, 2, 10, 2, 8410, 17, 0, 0 },
{ 1259, 2, 6, 2, 8366, 17, 0, 1 },
{ 1271, 2, 6, 2, 8369, 17, 0, 1 },
{ 1283, 2, 6, 2, 8372, 17, 0, 1 },
{ 1300, 2, 6, 2, 8375, 17, 0, 1 },
{ 1181, 2, 6, 2, 8378, 17, 0, 1 },
{ 1199, 2, 6, 2, 8381, 17, 0, 1 },
{ 1217, 2, 6, 2, 8384, 17, 0, 1 },
{ 1229, 2, 6, 2, 8387, 17, 0, 1 },
{ 1241, 2, 6, 2, 8390, 17, 0, 1 },
{ 1253, 2, 6, 2, 8393, 17, 0, 1 },
{ 1265, 2, 6, 2, 8396, 17, 0, 1 },
{ 1277, 2, 6, 2, 8399, 17, 0, 1 },
{ 1289, 2, 6, 2, 8402, 17, 0, 1 },
{ 1306, 2, 6, 2, 8405, 17, 0, 1 },
{ 1187, 2, 6, 2, 8408, 17, 0, 1 },
{ 1205, 2, 6, 2, 8411, 17, 0, 1 },
{ 1098, 231, 4, 10, 327853, 7, 0, 0 },
{ 1108, 231, 4, 10, 327856, 7, 0, 0 },
{ 1118, 231, 4, 10, 327859, 7, 0, 0 },
{ 1132, 231, 4, 10, 327862, 7, 0, 0 },
{ 1033, 231, 4, 10, 327865, 7, 0, 0 },
{ 1048, 231, 4, 10, 327868, 7, 0, 0 },
{ 1063, 231, 4, 10, 327871, 7, 0, 0 },
{ 1073, 231, 4, 10, 327874, 7, 0, 0 },
{ 1083, 231, 4, 10, 327877, 7, 0, 0 },
{ 1093, 231, 4, 10, 327880, 7, 0, 0 },
{ 1103, 231, 4, 10, 327883, 7, 0, 0 },
{ 1113, 231, 4, 10, 327886, 7, 0, 0 },
{ 1123, 231, 4, 10, 327889, 7, 0, 0 },
{ 1137, 231, 4, 10, 327892, 7, 0, 0 },
{ 1038, 231, 4, 10, 327895, 7, 0, 0 },
{ 1053, 231, 4, 10, 327898, 7, 0, 0 },
{ 1679, 106, 7, 2, 233645, 2, 0, 0 },
{ 1689, 106, 7, 2, 233648, 2, 0, 0 },
{ 1699, 106, 7, 2, 233651, 2, 0, 0 },
{ 1713, 106, 7, 2, 233654, 2, 0, 0 },
{ 1614, 106, 7, 2, 233657, 2, 0, 0 },
{ 1629, 106, 7, 2, 233660, 2, 0, 0 },
{ 1644, 106, 7, 2, 233663, 2, 0, 0 },
{ 1654, 106, 7, 2, 233666, 2, 0, 0 },
{ 1664, 106, 7, 2, 233669, 2, 0, 0 },
{ 1674, 106, 7, 2, 233672, 2, 0, 0 },
{ 1684, 106, 7, 2, 233675, 2, 0, 0 },
{ 1694, 106, 7, 2, 233678, 2, 0, 0 },
{ 1704, 106, 7, 2, 233681, 2, 0, 0 },
{ 1718, 106, 7, 2, 233684, 2, 0, 0 },
{ 1619, 106, 7, 2, 233687, 2, 0, 0 },
{ 1634, 106, 7, 2, 233690, 2, 0, 0 },
{ 1423, 2, 3, 2, 8367, 17, 0, 1 },
{ 1435, 2, 3, 2, 8370, 17, 0, 1 },
{ 1447, 2, 3, 2, 8373, 17, 0, 1 },
{ 1464, 2, 3, 2, 8376, 17, 0, 1 },
{ 1345, 2, 3, 2, 8379, 17, 0, 1 },
{ 1363, 2, 3, 2, 8382, 17, 0, 1 },
{ 1381, 2, 3, 2, 8385, 17, 0, 1 },
{ 1393, 2, 3, 2, 8388, 17, 0, 1 },
{ 1405, 2, 3, 2, 8391, 17, 0, 1 },
{ 1417, 2, 3, 2, 8394, 17, 0, 1 },
{ 1429, 2, 3, 2, 8397, 17, 0, 1 },
{ 1441, 2, 3, 2, 8400, 17, 0, 1 },
{ 1453, 2, 3, 2, 8403, 17, 0, 1 },
{ 1470, 2, 3, 2, 8406, 17, 0, 1 },
{ 1351, 2, 3, 2, 8409, 17, 0, 1 },
{ 1369, 2, 3, 2, 8412, 17, 0, 1 },
};
extern const MCPhysReg X86RegUnitRoots[][2] = {
{ X86::AH },
{ X86::AL },
{ X86::BH },
{ X86::BL },
{ X86::BPL },
{ X86::BPH },
{ X86::CH },
{ X86::CL },
{ X86::CS },
{ X86::DF },
{ X86::DH },
{ X86::DIL },
{ X86::DIH },
{ X86::DL },
{ X86::DS },
{ X86::HAX },
{ X86::HBP },
{ X86::HBX },
{ X86::HCX },
{ X86::HDI },
{ X86::HDX },
{ X86::EFLAGS },
{ X86::IP },
{ X86::HIP },
{ X86::EIZ },
{ X86::ES },
{ X86::SIL },
{ X86::SIH },
{ X86::HSI },
{ X86::SPL },
{ X86::SPH },
{ X86::HSP },
{ X86::FPCW },
{ X86::FPSW },
{ X86::FS },
{ X86::FS_BASE },
{ X86::GS },
{ X86::GS_BASE },
{ X86::MXCSR },
{ X86::RFLAGS },
{ X86::RIZ },
{ X86::SS },
{ X86::SSP },
{ X86::_EFLAGS },
{ X86::CR0 },
{ X86::CR1 },
{ X86::CR2 },
{ X86::CR3 },
{ X86::CR4 },
{ X86::CR5 },
{ X86::CR6 },
{ X86::CR7 },
{ X86::CR8 },
{ X86::CR9 },
{ X86::CR10 },
{ X86::CR11 },
{ X86::CR12 },
{ X86::CR13 },
{ X86::CR14 },
{ X86::CR15 },
{ X86::DR0 },
{ X86::DR1 },
{ X86::DR2 },
{ X86::DR3 },
{ X86::DR4 },
{ X86::DR5 },
{ X86::DR6 },
{ X86::DR7 },
{ X86::DR8 },
{ X86::DR9 },
{ X86::DR10 },
{ X86::DR11 },
{ X86::DR12 },
{ X86::DR13 },
{ X86::DR14 },
{ X86::DR15 },
{ X86::FP0 },
{ X86::FP1 },
{ X86::FP2 },
{ X86::FP3 },
{ X86::FP4 },
{ X86::FP5 },
{ X86::FP6 },
{ X86::FP7 },
{ X86::MM0 },
{ X86::MM1 },
{ X86::MM2 },
{ X86::MM3 },
{ X86::MM4 },
{ X86::MM5 },
{ X86::MM6 },
{ X86::MM7 },
{ X86::R8B },
{ X86::R8BH },
{ X86::R8WH },
{ X86::R9B },
{ X86::R9BH },
{ X86::R9WH },
{ X86::R10B },
{ X86::R10BH },
{ X86::R10WH },
{ X86::R11B },
{ X86::R11BH },
{ X86::R11WH },
{ X86::R12B },
{ X86::R12BH },
{ X86::R12WH },
{ X86::R13B },
{ X86::R13BH },
{ X86::R13WH },
{ X86::R14B },
{ X86::R14BH },
{ X86::R14WH },
{ X86::R15B },
{ X86::R15BH },
{ X86::R15WH },
{ X86::ST0 },
{ X86::ST1 },
{ X86::ST2 },
{ X86::ST3 },
{ X86::ST4 },
{ X86::ST5 },
{ X86::ST6 },
{ X86::ST7 },
{ X86::XMM0 },
{ X86::XMM1 },
{ X86::XMM2 },
{ X86::XMM3 },
{ X86::XMM4 },
{ X86::XMM5 },
{ X86::XMM6 },
{ X86::XMM7 },
{ X86::XMM8 },
{ X86::XMM9 },
{ X86::XMM10 },
{ X86::XMM11 },
{ X86::XMM12 },
{ X86::XMM13 },
{ X86::XMM14 },
{ X86::XMM15 },
{ X86::K0 },
{ X86::K1 },
{ X86::K2 },
{ X86::K3 },
{ X86::K4 },
{ X86::K5 },
{ X86::K6 },
{ X86::K7 },
{ X86::XMM16 },
{ X86::XMM17 },
{ X86::XMM18 },
{ X86::XMM19 },
{ X86::XMM20 },
{ X86::XMM21 },
{ X86::XMM22 },
{ X86::XMM23 },
{ X86::XMM24 },
{ X86::XMM25 },
{ X86::XMM26 },
{ X86::XMM27 },
{ X86::XMM28 },
{ X86::XMM29 },
{ X86::XMM30 },
{ X86::XMM31 },
{ X86::TMMCFG },
{ X86::TMM0 },
{ X86::TMM1 },
{ X86::TMM2 },
{ X86::TMM3 },
{ X86::TMM4 },
{ X86::TMM5 },
{ X86::TMM6 },
{ X86::TMM7 },
{ X86::R16B },
{ X86::R16BH },
{ X86::R16WH },
{ X86::R17B },
{ X86::R17BH },
{ X86::R17WH },
{ X86::R18B },
{ X86::R18BH },
{ X86::R18WH },
{ X86::R19B },
{ X86::R19BH },
{ X86::R19WH },
{ X86::R20B },
{ X86::R20BH },
{ X86::R20WH },
{ X86::R21B },
{ X86::R21BH },
{ X86::R21WH },
{ X86::R22B },
{ X86::R22BH },
{ X86::R22WH },
{ X86::R23B },
{ X86::R23BH },
{ X86::R23WH },
{ X86::R24B },
{ X86::R24BH },
{ X86::R24WH },
{ X86::R25B },
{ X86::R25BH },
{ X86::R25WH },
{ X86::R26B },
{ X86::R26BH },
{ X86::R26WH },
{ X86::R27B },
{ X86::R27BH },
{ X86::R27WH },
{ X86::R28B },
{ X86::R28BH },
{ X86::R28WH },
{ X86::R29B },
{ X86::R29BH },
{ X86::R29WH },
{ X86::R30B },
{ X86::R30BH },
{ X86::R30WH },
{ X86::R31B },
{ X86::R31BH },
{ X86::R31WH },
};
namespace { // Register classes...
// GR8 Register Class...
const MCPhysReg GR8[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B,
};
// GR8 Bit set.
const uint8_t GR8Bits[] = {
0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GRH8 Register Class...
const MCPhysReg GRH8[] = {
X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, X86::R16BH, X86::R17BH, X86::R18BH, X86::R19BH, X86::R20BH, X86::R21BH, X86::R22BH, X86::R23BH, X86::R24BH, X86::R25BH, X86::R26BH, X86::R27BH, X86::R28BH, X86::R29BH, X86::R30BH, X86::R31BH,
};
// GRH8 Bit set.
const uint8_t GRH8Bits[] = {
0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR8_NOREX2 Register Class...
const MCPhysReg GR8_NOREX2[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
};
// GR8_NOREX2 Bit set.
const uint8_t GR8_NOREX2Bits[] = {
0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// GR8_NOREX Register Class...
const MCPhysReg GR8_NOREX[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
};
// GR8_NOREX Bit set.
const uint8_t GR8_NOREXBits[] = {
0x36, 0x8c, 0x08,
};
// GR8_ABCD_H Register Class...
const MCPhysReg GR8_ABCD_H[] = {
X86::AH, X86::CH, X86::DH, X86::BH,
};
// GR8_ABCD_H Bit set.
const uint8_t GR8_ABCD_HBits[] = {
0x12, 0x84,
};
// GR8_ABCD_L Register Class...
const MCPhysReg GR8_ABCD_L[] = {
X86::AL, X86::CL, X86::DL, X86::BL,
};
// GR8_ABCD_L Bit set.
const uint8_t GR8_ABCD_LBits[] = {
0x24, 0x08, 0x08,
};
// GRH16 Register Class...
const MCPhysReg GRH16[] = {
X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, X86::R16WH, X86::R17WH, X86::R18WH, X86::R19WH, X86::R20WH, X86::R21WH, X86::R22WH, X86::R23WH, X86::R24WH, X86::R25WH, X86::R26WH, X86::R27WH, X86::R28WH, X86::R29WH, X86::R30WH, X86::R31WH,
};
// GRH16 Bit set.
const uint8_t GRH16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR16 Register Class...
const MCPhysReg GR16[] = {
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R16W, X86::R17W, X86::R18W, X86::R19W, X86::R22W, X86::R23W, X86::R24W, X86::R25W, X86::R26W, X86::R27W, X86::R30W, X86::R31W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::R20W, X86::R21W, X86::R28W, X86::R29W,
};
// GR16 Bit set.
const uint8_t GR16Bits[] = {
0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR16_NOREX2 Register Class...
const MCPhysReg GR16_NOREX2[] = {
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
};
// GR16_NOREX2 Bit set.
const uint8_t GR16_NOREX2Bits[] = {
0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// GR16_NOREX Register Class...
const MCPhysReg GR16_NOREX[] = {
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
};
// GR16_NOREX Bit set.
const uint8_t GR16_NOREXBits[] = {
0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
};
// VK1 Register Class...
const MCPhysReg VK1[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK1 Bit set.
const uint8_t VK1Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// VK16 Register Class...
const MCPhysReg VK16[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK16 Bit set.
const uint8_t VK16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// VK2 Register Class...
const MCPhysReg VK2[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK2 Bit set.
const uint8_t VK2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// VK4 Register Class...
const MCPhysReg VK4[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK4 Bit set.
const uint8_t VK4Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// VK8 Register Class...
const MCPhysReg VK8[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK8 Bit set.
const uint8_t VK8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// VK16WM Register Class...
const MCPhysReg VK16WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK16WM Bit set.
const uint8_t VK16WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// VK1WM Register Class...
const MCPhysReg VK1WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK1WM Bit set.
const uint8_t VK1WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// VK2WM Register Class...
const MCPhysReg VK2WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK2WM Bit set.
const uint8_t VK2WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// VK4WM Register Class...
const MCPhysReg VK4WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK4WM Bit set.
const uint8_t VK4WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// VK8WM Register Class...
const MCPhysReg VK8WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK8WM Bit set.
const uint8_t VK8WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// SEGMENT_REG Register Class...
const MCPhysReg SEGMENT_REG[] = {
X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
};
// SEGMENT_REG Bit set.
const uint8_t SEGMENT_REGBits[] = {
0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
};
// GR16_ABCD Register Class...
const MCPhysReg GR16_ABCD[] = {
X86::AX, X86::CX, X86::DX, X86::BX,
};
// GR16_ABCD Bit set.
const uint8_t GR16_ABCDBits[] = {
0x08, 0x22, 0x20,
};
// FPCCR Register Class...
const MCPhysReg FPCCR[] = {
X86::FPSW,
};
// FPCCR Bit set.
const uint8_t FPCCRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x08,
};
// FR16X Register Class...
const MCPhysReg FR16X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR16X Bit set.
const uint8_t FR16XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// FR16 Register Class...
const MCPhysReg FR16[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR16 Bit set.
const uint8_t FR16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// VK16PAIR Register Class...
const MCPhysReg VK16PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK16PAIR Bit set.
const uint8_t VK16PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// VK1PAIR Register Class...
const MCPhysReg VK1PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK1PAIR Bit set.
const uint8_t VK1PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// VK2PAIR Register Class...
const MCPhysReg VK2PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK2PAIR Bit set.
const uint8_t VK2PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// VK4PAIR Register Class...
const MCPhysReg VK4PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK4PAIR Bit set.
const uint8_t VK4PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// VK8PAIR Register Class...
const MCPhysReg VK8PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK8PAIR Bit set.
const uint8_t VK8PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// VK1PAIR_with_sub_mask_0_in_VK1WM Register Class...
const MCPhysReg VK1PAIR_with_sub_mask_0_in_VK1WM[] = {
X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK1PAIR_with_sub_mask_0_in_VK1WM Bit set.
const uint8_t VK1PAIR_with_sub_mask_0_in_VK1WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
};
// LOW32_ADDR_ACCESS_RBP Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// LOW32_ADDR_ACCESS Register Class...
const MCPhysReg LOW32_ADDR_ACCESS[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RIP,
};
// LOW32_ADDR_ACCESS Bit set.
const uint8_t LOW32_ADDR_ACCESSBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// FR32X Register Class...
const MCPhysReg FR32X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR32X Bit set.
const uint8_t FR32XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// GR32 Register Class...
const MCPhysReg GR32[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
};
// GR32 Bit set.
const uint8_t GR32Bits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR32_NOSP Register Class...
const MCPhysReg GR32_NOSP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::R20D, X86::R21D, X86::R28D, X86::R29D,
};
// GR32_NOSP Bit set.
const uint8_t GR32_NOSPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// DEBUG_REG Register Class...
const MCPhysReg DEBUG_REG[] = {
X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
};
// DEBUG_REG Bit set.
const uint8_t DEBUG_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// FR32 Register Class...
const MCPhysReg FR32[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR32 Bit set.
const uint8_t FR32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// GR32_NOREX2 Register Class...
const MCPhysReg GR32_NOREX2[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
};
// GR32_NOREX2 Bit set.
const uint8_t GR32_NOREX2Bits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// GR32_NOREX2_NOSP Register Class...
const MCPhysReg GR32_NOREX2_NOSP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
};
// GR32_NOREX2_NOSP Bit set.
const uint8_t GR32_NOREX2_NOSPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
};
// GR32_NOREX Register Class...
const MCPhysReg GR32_NOREX[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
};
// GR32_NOREX Bit set.
const uint8_t GR32_NOREXBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03,
};
// VK32 Register Class...
const MCPhysReg VK32[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK32 Bit set.
const uint8_t VK32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// GR32_NOREX_NOSP Register Class...
const MCPhysReg GR32_NOREX_NOSP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
};
// GR32_NOREX_NOSP Bit set.
const uint8_t GR32_NOREX_NOSPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x01,
};
// RFP32 Register Class...
const MCPhysReg RFP32[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP32 Bit set.
const uint8_t RFP32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
};
// VK32WM Register Class...
const MCPhysReg VK32WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK32WM Bit set.
const uint8_t VK32WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// GR32_ABCD Register Class...
const MCPhysReg GR32_ABCD[] = {
X86::EAX, X86::ECX, X86::EDX, X86::EBX,
};
// GR32_ABCD Bit set.
const uint8_t GR32_ABCDBits[] = {
0x00, 0x00, 0x40, 0x0b,
};
// GR32_TC Register Class...
const MCPhysReg GR32_TC[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESP,
};
// GR32_TC Bit set.
const uint8_t GR32_TCBits[] = {
0x00, 0x00, 0x40, 0x0a, 0x02,
};
// GR32_ABCD_and_GR32_TC Register Class...
const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
X86::EAX, X86::ECX, X86::EDX,
};
// GR32_ABCD_and_GR32_TC Bit set.
const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
0x00, 0x00, 0x40, 0x0a,
};
// GR32_AD Register Class...
const MCPhysReg GR32_AD[] = {
X86::EAX, X86::EDX,
};
// GR32_AD Bit set.
const uint8_t GR32_ADBits[] = {
0x00, 0x00, 0x40, 0x08,
};
// GR32_ArgRef Register Class...
const MCPhysReg GR32_ArgRef[] = {
X86::ECX, X86::EDX,
};
// GR32_ArgRef Bit set.
const uint8_t GR32_ArgRefBits[] = {
0x00, 0x00, 0x00, 0x0a,
};
// GR32_BPSP Register Class...
const MCPhysReg GR32_BPSP[] = {
X86::EBP, X86::ESP,
};
// GR32_BPSP Bit set.
const uint8_t GR32_BPSPBits[] = {
0x00, 0x00, 0x80, 0x00, 0x02,
};
// GR32_BSI Register Class...
const MCPhysReg GR32_BSI[] = {
X86::EBX, X86::ESI,
};
// GR32_BSI Bit set.
const uint8_t GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x01, 0x01,
};
// GR32_CB Register Class...
const MCPhysReg GR32_CB[] = {
X86::ECX, X86::EBX,
};
// GR32_CB Bit set.
const uint8_t GR32_CBBits[] = {
0x00, 0x00, 0x00, 0x03,
};
// GR32_DC Register Class...
const MCPhysReg GR32_DC[] = {
X86::EDX, X86::ECX,
};
// GR32_DC Bit set.
const uint8_t GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x0a,
};
// GR32_DIBP Register Class...
const MCPhysReg GR32_DIBP[] = {
X86::EDI, X86::EBP,
};
// GR32_DIBP Bit set.
const uint8_t GR32_DIBPBits[] = {
0x00, 0x00, 0x80, 0x04,
};
// GR32_SIDI Register Class...
const MCPhysReg GR32_SIDI[] = {
X86::ESI, X86::EDI,
};
// GR32_SIDI Bit set.
const uint8_t GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x04, 0x01,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
X86::RIP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
};
// CCR Register Class...
const MCPhysReg CCR[] = {
X86::EFLAGS,
};
// CCR Bit set.
const uint8_t CCRBits[] = {
0x00, 0x00, 0x00, 0x10,
};
// DFCCR Register Class...
const MCPhysReg DFCCR[] = {
X86::DF,
};
// DFCCR Bit set.
const uint8_t DFCCRBits[] = {
0x00, 0x40,
};
// GR32_ABCD_and_GR32_BSI Register Class...
const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
X86::EBX,
};
// GR32_ABCD_and_GR32_BSI Bit set.
const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x01,
};
// GR32_AD_and_GR32_ArgRef Register Class...
const MCPhysReg GR32_AD_and_GR32_ArgRef[] = {
X86::EDX,
};
// GR32_AD_and_GR32_ArgRef Bit set.
const uint8_t GR32_AD_and_GR32_ArgRefBits[] = {
0x00, 0x00, 0x00, 0x08,
};
// GR32_ArgRef_and_GR32_CB Register Class...
const MCPhysReg GR32_ArgRef_and_GR32_CB[] = {
X86::ECX,
};
// GR32_ArgRef_and_GR32_CB Bit set.
const uint8_t GR32_ArgRef_and_GR32_CBBits[] = {
0x00, 0x00, 0x00, 0x02,
};
// GR32_BPSP_and_GR32_DIBP Register Class...
const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
X86::EBP,
};
// GR32_BPSP_and_GR32_DIBP Bit set.
const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
0x00, 0x00, 0x80,
};
// GR32_BPSP_and_GR32_TC Register Class...
const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
X86::ESP,
};
// GR32_BPSP_and_GR32_TC Bit set.
const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x02,
};
// GR32_BSI_and_GR32_SIDI Register Class...
const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
X86::ESI,
};
// GR32_BSI_and_GR32_SIDI Bit set.
const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x01,
};
// GR32_DIBP_and_GR32_SIDI Register Class...
const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
X86::EDI,
};
// GR32_DIBP_and_GR32_SIDI Bit set.
const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x04,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
// LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
X86::RIP,
};
// LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// RFP64 Register Class...
const MCPhysReg RFP64[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP64 Bit set.
const uint8_t RFP64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
};
// GR64 Register Class...
const MCPhysReg GR64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP, X86::RIP,
};
// GR64 Bit set.
const uint8_t GR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// FR64X Register Class...
const MCPhysReg FR64X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR64X Bit set.
const uint8_t FR64XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// GR64_with_sub_8bit Register Class...
const MCPhysReg GR64_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP, X86::RSP,
};
// GR64_with_sub_8bit Bit set.
const uint8_t GR64_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR64_NOSP Register Class...
const MCPhysReg GR64_NOSP[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::R20, X86::R21, X86::R28, X86::R29, X86::RBP,
};
// GR64_NOSP Bit set.
const uint8_t GR64_NOSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR64_NOREX2 Register Class...
const MCPhysReg GR64_NOREX2[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
};
// GR64_NOREX2 Bit set.
const uint8_t GR64_NOREX2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// CONTROL_REG Register Class...
const MCPhysReg CONTROL_REG[] = {
X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
};
// CONTROL_REG Bit set.
const uint8_t CONTROL_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// FR64 Register Class...
const MCPhysReg FR64[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR64 Bit set.
const uint8_t FR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// GR64_with_sub_16bit_in_GR16_NOREX2 Register Class...
const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX2[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
};
// GR64_with_sub_16bit_in_GR16_NOREX2 Bit set.
const uint8_t GR64_with_sub_16bit_in_GR16_NOREX2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// GR64_NOREX2_NOSP Register Class...
const MCPhysReg GR64_NOREX2_NOSP[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
};
// GR64_NOREX2_NOSP Bit set.
const uint8_t GR64_NOREX2_NOSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// GR64PLTSafe Register Class...
const MCPhysReg GR64PLTSafe[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
};
// GR64PLTSafe Bit set.
const uint8_t GR64PLTSafeBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x79,
};
// GR64_TC Register Class...
const MCPhysReg GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
};
// GR64_TC Bit set.
const uint8_t GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
};
// GR64_NOREX Register Class...
const MCPhysReg GR64_NOREX[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
};
// GR64_NOREX Bit set.
const uint8_t GR64_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
};
// GR64_TCW64 Register Class...
const MCPhysReg GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
};
// GR64_TCW64 Bit set.
const uint8_t GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// GR64_TC_with_sub_8bit Register Class...
const MCPhysReg GR64_TC_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
};
// GR64_TC_with_sub_8bit Bit set.
const uint8_t GR64_TC_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
};
// GR64_NOREX2_NOSP_and_GR64_TC Register Class...
const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
};
// GR64_NOREX2_NOSP_and_GR64_TC Bit set.
const uint8_t GR64_NOREX2_NOSP_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
};
// GR64_TCW64_with_sub_8bit Register Class...
const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
};
// GR64_TCW64_with_sub_8bit Bit set.
const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// GR64_TC_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
};
// GR64_TC_and_GR64_TCW64 Bit set.
const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
};
// GR64_with_sub_16bit_in_GR16_NOREX Register Class...
const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
};
// GR64_with_sub_16bit_in_GR16_NOREX Bit set.
const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
};
// VK64 Register Class...
const MCPhysReg VK64[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK64 Bit set.
const uint8_t VK64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// VR64 Register Class...
const MCPhysReg VR64[] = {
X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
};
// VR64 Bit set.
const uint8_t VR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// GR64PLTSafe_and_GR64_TC Register Class...
const MCPhysReg GR64PLTSafe_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
};
// GR64PLTSafe_and_GR64_TC Bit set.
const uint8_t GR64PLTSafe_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
};
// GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
};
// GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
const uint8_t GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// GR64_NOREX_NOSP Register Class...
const MCPhysReg GR64_NOREX_NOSP[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
};
// GR64_NOREX_NOSP Bit set.
const uint8_t GR64_NOREX_NOSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
};
// GR64_NOREX_and_GR64_TC Register Class...
const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
};
// GR64_NOREX_and_GR64_TC Bit set.
const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
};
// GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
};
// GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
};
// VK64WM Register Class...
const MCPhysReg VK64WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK64WM Bit set.
const uint8_t VK64WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
};
// GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
const uint8_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
};
// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
};
// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
};
// GR64PLTSafe_and_GR64_TCW64 Register Class...
const MCPhysReg GR64PLTSafe_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
};
// GR64PLTSafe_and_GR64_TCW64 Bit set.
const uint8_t GR64PLTSafe_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
};
// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Register Class...
const MCPhysReg GR64_NOREX_and_GR64PLTSafe_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
};
// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Bit set.
const uint8_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
};
// GR64_NOREX_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
};
// GR64_NOREX_and_GR64_TCW64 Bit set.
const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
};
// GR64_ABCD Register Class...
const MCPhysReg GR64_ABCD[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RBX,
};
// GR64_ABCD Bit set.
const uint8_t GR64_ABCDBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
};
// GR64_with_sub_32bit_in_GR32_TC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSP,
};
// GR64_with_sub_32bit_in_GR32_TC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
X86::RAX, X86::RCX, X86::RDX,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
};
// GR64_AD Register Class...
const MCPhysReg GR64_AD[] = {
X86::RAX, X86::RDX,
};
// GR64_AD Bit set.
const uint8_t GR64_ADBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
};
// GR64_ArgRef Register Class...
const MCPhysReg GR64_ArgRef[] = {
X86::R10, X86::R11,
};
// GR64_ArgRef Bit set.
const uint8_t GR64_ArgRefBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
};
// GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
X86::RBP, X86::RIP,
};
// GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
};
// GR64_with_sub_32bit_in_GR32_ArgRef Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef[] = {
X86::RCX, X86::RDX,
};
// GR64_with_sub_32bit_in_GR32_ArgRef Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_ArgRefBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
};
// GR64_with_sub_32bit_in_GR32_BPSP Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
X86::RBP, X86::RSP,
};
// GR64_with_sub_32bit_in_GR32_BPSP Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
};
// GR64_with_sub_32bit_in_GR32_BSI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
X86::RSI, X86::RBX,
};
// GR64_with_sub_32bit_in_GR32_BSI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
};
// GR64_with_sub_32bit_in_GR32_CB Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
X86::RCX, X86::RBX,
};
// GR64_with_sub_32bit_in_GR32_CB Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
};
// GR64_with_sub_32bit_in_GR32_DIBP Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
X86::RDI, X86::RBP,
};
// GR64_with_sub_32bit_in_GR32_DIBP Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
};
// GR64_with_sub_32bit_in_GR32_SIDI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
X86::RSI, X86::RDI,
};
// GR64_with_sub_32bit_in_GR32_SIDI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
};
// GR64_ArgRef_and_GR64_TC Register Class...
const MCPhysReg GR64_ArgRef_and_GR64_TC[] = {
X86::R11,
};
// GR64_ArgRef_and_GR64_TC Bit set.
const uint8_t GR64_ArgRef_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// GR64_and_LOW32_ADDR_ACCESS Register Class...
const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
X86::RIP,
};
// GR64_and_LOW32_ADDR_ACCESS Bit set.
const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
X86::RBX,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
};
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef[] = {
X86::RDX,
};
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
};
// GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB[] = {
X86::RCX,
};
// GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
X86::RBP,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
X86::RSP,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
};
// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
X86::RSI,
};
// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
X86::RDI,
};
// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
};
// RST Register Class...
const MCPhysReg RST[] = {
X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
};
// RST Bit set.
const uint8_t RSTBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
// RFP80 Register Class...
const MCPhysReg RFP80[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP80 Bit set.
const uint8_t RFP80Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
};
// RFP80_7 Register Class...
const MCPhysReg RFP80_7[] = {
X86::FP7,
};
// RFP80_7 Bit set.
const uint8_t RFP80_7Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
};
// VR128X Register Class...
const MCPhysReg VR128X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// VR128X Bit set.
const uint8_t VR128XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// VR128 Register Class...
const MCPhysReg VR128[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// VR128 Bit set.
const uint8_t VR128Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// VR256X Register Class...
const MCPhysReg VR256X[] = {
X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
};
// VR256X Bit set.
const uint8_t VR256XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// VR256 Register Class...
const MCPhysReg VR256[] = {
X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
};
// VR256 Bit set.
const uint8_t VR256Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// VR512 Register Class...
const MCPhysReg VR512[] = {
X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
};
// VR512 Bit set.
const uint8_t VR512Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
};
// VR512_0_15 Register Class...
const MCPhysReg VR512_0_15[] = {
X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
};
// VR512_0_15 Bit set.
const uint8_t VR512_0_15Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// TILE Register Class...
const MCPhysReg TILE[] = {
X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
};
// TILE Bit set.
const uint8_t TILEBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
};
// TILEPAIR Register Class...
const MCPhysReg TILEPAIR[] = {
X86::TMM0_TMM1, X86::TMM2_TMM3, X86::TMM4_TMM5, X86::TMM6_TMM7,
};
// TILEPAIR Bit set.
const uint8_t TILEPAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
};
} // end anonymous namespace
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char X86RegClassStrings[] = {
/* 0 */ "RFP80\000"
/* 6 */ "VK1\000"
/* 10 */ "VR512\000"
/* 16 */ "VK32\000"
/* 21 */ "RFP32\000"
/* 27 */ "FR32\000"
/* 32 */ "GR32\000"
/* 37 */ "VK2\000"
/* 41 */ "GR32_NOREX2\000"
/* 53 */ "GR64_NOREX2\000"
/* 65 */ "GR64_with_sub_16bit_in_GR16_NOREX2\000"
/* 100 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2\000"
/* 152 */ "GR8_NOREX2\000"
/* 163 */ "VK64\000"
/* 168 */ "RFP64\000"
/* 174 */ "FR64\000"
/* 179 */ "GR64\000"
/* 184 */ "VR64\000"
/* 189 */ "GR64_TC_and_GR64_TCW64\000"
/* 212 */ "GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64\000"
/* 256 */ "GR64_NOREX_and_GR64_TCW64\000"
/* 282 */ "GR64PLTSafe_and_GR64_TCW64\000"
/* 309 */ "VK4\000"
/* 313 */ "VR512_0_15\000"
/* 324 */ "GRH16\000"
/* 330 */ "VK16\000"
/* 335 */ "FR16\000"
/* 340 */ "GR16\000"
/* 345 */ "VR256\000"
/* 351 */ "RFP80_7\000"
/* 359 */ "VR128\000"
/* 365 */ "GRH8\000"
/* 370 */ "VK8\000"
/* 374 */ "GR8\000"
/* 378 */ "GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB\000"
/* 425 */ "GR64_with_sub_32bit_in_GR32_CB\000"
/* 456 */ "GR32_DC\000"
/* 464 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC\000"
/* 509 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC\000"
/* 554 */ "GR64_with_sub_32bit_in_GR32_TC\000"
/* 585 */ "GR64_NOREX2_NOSP_and_GR64_TC\000"
/* 614 */ "GR64_NOREX_and_GR64_TC\000"
/* 637 */ "GR64_NOREX_and_GR64PLTSafe_and_GR64_TC\000"
/* 676 */ "GR64_ArgRef_and_GR64_TC\000"
/* 700 */ "GR32_AD\000"
/* 708 */ "GR64_AD\000"
/* 716 */ "GR32_ABCD\000"
/* 726 */ "GR64_ABCD\000"
/* 736 */ "GR16_ABCD\000"
/* 746 */ "TILE\000"
/* 751 */ "DEBUG_REG\000"
/* 761 */ "CONTROL_REG\000"
/* 773 */ "SEGMENT_REG\000"
/* 785 */ "GR8_ABCD_H\000"
/* 796 */ "GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI\000"
/* 842 */ "GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI\000"
/* 889 */ "GR64_with_sub_32bit_in_GR32_SIDI\000"
/* 922 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI\000"
/* 968 */ "GR64_with_sub_32bit_in_GR32_BSI\000"
/* 1000 */ "GR8_ABCD_L\000"
/* 1011 */ "VK1PAIR_with_sub_mask_0_in_VK1WM\000"
/* 1044 */ "VK32WM\000"
/* 1051 */ "VK2WM\000"
/* 1057 */ "VK64WM\000"
/* 1064 */ "VK4WM\000"
/* 1070 */ "VK16WM\000"
/* 1077 */ "VK8WM\000"
/* 1083 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP\000"
/* 1130 */ "GR64_with_sub_32bit_in_GR32_DIBP\000"
/* 1163 */ "GR64_and_LOW32_ADDR_ACCESS_RBP\000"
/* 1194 */ "GR32_NOSP\000"
/* 1204 */ "GR32_NOREX2_NOSP\000"
/* 1221 */ "GR64_NOREX2_NOSP\000"
/* 1238 */ "GR64_NOSP\000"
/* 1248 */ "GR32_NOREX_NOSP\000"
/* 1264 */ "GR64_NOREX_NOSP\000"
/* 1280 */ "GR64_with_sub_32bit_in_GR32_BPSP\000"
/* 1313 */ "DFCCR\000"
/* 1319 */ "FPCCR\000"
/* 1325 */ "VK1PAIR\000"
/* 1333 */ "VK2PAIR\000"
/* 1341 */ "VK4PAIR\000"
/* 1349 */ "VK16PAIR\000"
/* 1358 */ "VK8PAIR\000"
/* 1366 */ "TILEPAIR\000"
/* 1375 */ "GR64_and_LOW32_ADDR_ACCESS\000"
/* 1402 */ "RST\000"
/* 1406 */ "FR32X\000"
/* 1412 */ "FR64X\000"
/* 1418 */ "FR16X\000"
/* 1424 */ "VR256X\000"
/* 1431 */ "VR128X\000"
/* 1438 */ "GR32_NOREX\000"
/* 1449 */ "GR64_NOREX\000"
/* 1460 */ "GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX\000"
/* 1506 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX\000"
/* 1557 */ "GR8_NOREX\000"
/* 1567 */ "GR64PLTSafe\000"
/* 1579 */ "GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef\000"
/* 1626 */ "GR64_with_sub_32bit_in_GR32_ArgRef\000"
/* 1661 */ "GR64_ArgRef\000"
/* 1673 */ "LOW32_ADDR_ACCESS_RBP_with_sub_32bit\000"
/* 1710 */ "LOW32_ADDR_ACCESS_with_sub_32bit\000"
/* 1743 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit\000"
/* 1794 */ "GR64_with_sub_8bit\000"
/* 1813 */ "GR64_TCW64_with_sub_8bit\000"
/* 1838 */ "GR64_TCW64_and_GR64_TC_with_sub_8bit\000"
/* 1875 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit\000"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const MCRegisterClass X86MCRegisterClasses[] = {
{ GR8, GR8Bits, 374, 36, sizeof(GR8Bits), X86::GR8RegClassID, 8, 1, true, false },
{ GRH8, GRH8Bits, 365, 28, sizeof(GRH8Bits), X86::GRH8RegClassID, 8, 1, false, false },
{ GR8_NOREX2, GR8_NOREX2Bits, 152, 20, sizeof(GR8_NOREX2Bits), X86::GR8_NOREX2RegClassID, 8, 1, true, false },
{ GR8_NOREX, GR8_NOREXBits, 1557, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 8, 1, true, false },
{ GR8_ABCD_H, GR8_ABCD_HBits, 785, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 8, 1, true, false },
{ GR8_ABCD_L, GR8_ABCD_LBits, 1000, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 8, 1, true, false },
{ GRH16, GRH16Bits, 324, 33, sizeof(GRH16Bits), X86::GRH16RegClassID, 16, 1, false, false },
{ GR16, GR16Bits, 340, 32, sizeof(GR16Bits), X86::GR16RegClassID, 16, 1, true, false },
{ GR16_NOREX2, GR16_NOREX2Bits, 88, 16, sizeof(GR16_NOREX2Bits), X86::GR16_NOREX2RegClassID, 16, 1, true, false },
{ GR16_NOREX, GR16_NOREXBits, 1495, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 16, 1, true, false },
{ VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 16, 1, true, false },
{ VK16, VK16Bits, 330, 8, sizeof(VK16Bits), X86::VK16RegClassID, 16, 1, true, false },
{ VK2, VK2Bits, 37, 8, sizeof(VK2Bits), X86::VK2RegClassID, 16, 1, true, false },
{ VK4, VK4Bits, 309, 8, sizeof(VK4Bits), X86::VK4RegClassID, 16, 1, true, false },
{ VK8, VK8Bits, 370, 8, sizeof(VK8Bits), X86::VK8RegClassID, 16, 1, true, false },
{ VK16WM, VK16WMBits, 1070, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 16, 1, true, false },
{ VK1WM, VK1WMBits, 1038, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 16, 1, true, false },
{ VK2WM, VK2WMBits, 1051, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 16, 1, true, false },
{ VK4WM, VK4WMBits, 1064, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 16, 1, true, false },
{ VK8WM, VK8WMBits, 1077, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 16, 1, true, false },
{ SEGMENT_REG, SEGMENT_REGBits, 773, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 16, 1, true, false },
{ GR16_ABCD, GR16_ABCDBits, 736, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 16, 1, true, false },
{ FPCCR, FPCCRBits, 1319, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, 16, -1, false, false },
{ FR16X, FR16XBits, 1418, 32, sizeof(FR16XBits), X86::FR16XRegClassID, 32, 1, true, false },
{ FR16, FR16Bits, 335, 16, sizeof(FR16Bits), X86::FR16RegClassID, 32, 1, true, false },
{ VK16PAIR, VK16PAIRBits, 1349, 4, sizeof(VK16PAIRBits), X86::VK16PAIRRegClassID, 32, 1, true, false },
{ VK1PAIR, VK1PAIRBits, 1325, 4, sizeof(VK1PAIRBits), X86::VK1PAIRRegClassID, 32, 1, true, false },
{ VK2PAIR, VK2PAIRBits, 1333, 4, sizeof(VK2PAIRBits), X86::VK2PAIRRegClassID, 32, 1, true, false },
{ VK4PAIR, VK4PAIRBits, 1341, 4, sizeof(VK4PAIRBits), X86::VK4PAIRRegClassID, 32, 1, true, false },
{ VK8PAIR, VK8PAIRBits, 1358, 4, sizeof(VK8PAIRBits), X86::VK8PAIRRegClassID, 32, 1, true, false },
{ VK1PAIR_with_sub_mask_0_in_VK1WM, VK1PAIR_with_sub_mask_0_in_VK1WMBits, 1011, 3, sizeof(VK1PAIR_with_sub_mask_0_in_VK1WMBits), X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1172, 34, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1384, 33, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1875, 33, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 32, 1, true, false },
{ FR32X, FR32XBits, 1406, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 32, 1, true, false },
{ GR32, GR32Bits, 32, 32, sizeof(GR32Bits), X86::GR32RegClassID, 32, 1, true, false },
{ GR32_NOSP, GR32_NOSPBits, 1194, 31, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits, 100, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, 32, 1, true, false },
{ DEBUG_REG, DEBUG_REGBits, 751, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 32, 1, true, false },
{ FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 32, 1, true, false },
{ GR32_NOREX2, GR32_NOREX2Bits, 41, 16, sizeof(GR32_NOREX2Bits), X86::GR32_NOREX2RegClassID, 32, 1, true, false },
{ GR32_NOREX2_NOSP, GR32_NOREX2_NOSPBits, 1204, 15, sizeof(GR32_NOREX2_NOSPBits), X86::GR32_NOREX2_NOSPRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1506, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 32, 1, true, false },
{ GR32_NOREX, GR32_NOREXBits, 1438, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 32, 1, true, false },
{ VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 32, 1, true, false },
{ GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1248, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 32, 1, true, false },
{ RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 32, 1, true, false },
{ VK32WM, VK32WMBits, 1044, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 32, 1, true, false },
{ GR32_ABCD, GR32_ABCDBits, 716, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 32, 1, true, false },
{ GR32_TC, GR32_TCBits, 501, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 32, 1, true, false },
{ GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 487, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 32, 1, true, false },
{ GR32_AD, GR32_ADBits, 700, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 32, 1, true, false },
{ GR32_ArgRef, GR32_ArgRefBits, 1614, 2, sizeof(GR32_ArgRefBits), X86::GR32_ArgRefRegClassID, 32, 1, true, false },
{ GR32_BPSP, GR32_BPSPBits, 1303, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 32, 1, true, false },
{ GR32_BSI, GR32_BSIBits, 959, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 32, 1, true, false },
{ GR32_CB, GR32_CBBits, 417, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 32, 1, true, false },
{ GR32_DC, GR32_DCBits, 456, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 32, 1, true, false },
{ GR32_DIBP, GR32_DIBPBits, 1120, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 32, 1, true, false },
{ GR32_SIDI, GR32_SIDIBits, 832, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1673, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 32, 1, true, false },
{ CCR, CCRBits, 1315, 1, sizeof(CCRBits), X86::CCRRegClassID, 32, -1, false, false },
{ DFCCR, DFCCRBits, 1313, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, 32, -1, false, false },
{ GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 945, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 32, 1, true, false },
{ GR32_AD_and_GR32_ArgRef, GR32_AD_and_GR32_ArgRefBits, 1602, 1, sizeof(GR32_AD_and_GR32_ArgRefBits), X86::GR32_AD_and_GR32_ArgRefRegClassID, 32, 1, true, false },
{ GR32_ArgRef_and_GR32_CB, GR32_ArgRef_and_GR32_CBBits, 401, 1, sizeof(GR32_ArgRef_and_GR32_CBBits), X86::GR32_ArgRef_and_GR32_CBRegClassID, 32, 1, true, false },
{ GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 1106, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 32, 1, true, false },
{ GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 532, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 32, 1, true, false },
{ GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 819, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 32, 1, true, false },
{ GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 865, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1743, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 32, 1, true, false },
{ LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1710, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 32, 1, true, false },
{ RFP64, RFP64Bits, 168, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 64, 1, true, false },
{ GR64, GR64Bits, 179, 33, sizeof(GR64Bits), X86::GR64RegClassID, 64, 1, true, false },
{ FR64X, FR64XBits, 1412, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 64, 1, true, false },
{ GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1794, 32, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 64, 1, true, false },
{ GR64_NOSP, GR64_NOSPBits, 1238, 31, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 64, 1, true, false },
{ GR64_NOREX2, GR64_NOREX2Bits, 53, 17, sizeof(GR64_NOREX2Bits), X86::GR64_NOREX2RegClassID, 64, 1, true, false },
{ CONTROL_REG, CONTROL_REGBits, 761, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 64, 1, true, false },
{ FR64, FR64Bits, 174, 16, sizeof(FR64Bits), X86::FR64RegClassID, 64, 1, true, false },
{ GR64_with_sub_16bit_in_GR16_NOREX2, GR64_with_sub_16bit_in_GR16_NOREX2Bits, 65, 16, sizeof(GR64_with_sub_16bit_in_GR16_NOREX2Bits), X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, 64, 1, true, false },
{ GR64_NOREX2_NOSP, GR64_NOREX2_NOSPBits, 1221, 15, sizeof(GR64_NOREX2_NOSPBits), X86::GR64_NOREX2_NOSPRegClassID, 64, 1, true, false },
{ GR64PLTSafe, GR64PLTSafeBits, 1567, 13, sizeof(GR64PLTSafeBits), X86::GR64PLTSafeRegClassID, 64, 1, true, false },
{ GR64_TC, GR64_TCBits, 606, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 64, 1, true, false },
{ GR64_NOREX, GR64_NOREXBits, 1449, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 64, 1, true, false },
{ GR64_TCW64, GR64_TCW64Bits, 201, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 64, 1, true, false },
{ GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1853, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 64, 1, true, false },
{ GR64_NOREX2_NOSP_and_GR64_TC, GR64_NOREX2_NOSP_and_GR64_TCBits, 585, 8, sizeof(GR64_NOREX2_NOSP_and_GR64_TCBits), X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, 64, 1, true, false },
{ GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1813, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 64, 1, true, false },
{ GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 189, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 64, 1, true, false },
{ GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1472, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true, false },
{ VK64, VK64Bits, 163, 8, sizeof(VK64Bits), X86::VK64RegClassID, 64, 1, true, false },
{ VR64, VR64Bits, 184, 8, sizeof(VR64Bits), X86::VR64RegClassID, 64, 1, true, false },
{ GR64PLTSafe_and_GR64_TC, GR64PLTSafe_and_GR64_TCBits, 652, 7, sizeof(GR64PLTSafe_and_GR64_TCBits), X86::GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true, false },
{ GR64_NOREX2_NOSP_and_GR64_TCW64, GR64_NOREX2_NOSP_and_GR64_TCW64Bits, 224, 7, sizeof(GR64_NOREX2_NOSP_and_GR64_TCW64Bits), X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, 64, 1, true, false },
{ GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1264, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 64, 1, true, false },
{ GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 614, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 64, 1, true, false },
{ GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1838, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 64, 1, true, false },
{ VK64WM, VK64WMBits, 1057, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 64, 1, true, false },
{ GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits, 212, 6, sizeof(GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, 64, 1, true, false },
{ GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1460, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true, false },
{ GR64PLTSafe_and_GR64_TCW64, GR64PLTSafe_and_GR64_TCW64Bits, 282, 5, sizeof(GR64PLTSafe_and_GR64_TCW64Bits), X86::GR64PLTSafe_and_GR64_TCW64RegClassID, 64, 1, true, false },
{ GR64_NOREX_and_GR64PLTSafe_and_GR64_TC, GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits, 637, 5, sizeof(GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits), X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true, false },
{ GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 256, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 64, 1, true, false },
{ GR64_ABCD, GR64_ABCDBits, 726, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 554, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 464, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 64, 1, true, false },
{ GR64_AD, GR64_ADBits, 708, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 64, 1, true, false },
{ GR64_ArgRef, GR64_ArgRefBits, 1661, 2, sizeof(GR64_ArgRefBits), X86::GR64_ArgRefRegClassID, 64, 1, true, false },
{ GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1163, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_ArgRef, GR64_with_sub_32bit_in_GR32_ArgRefBits, 1626, 2, sizeof(GR64_with_sub_32bit_in_GR32_ArgRefBits), X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1280, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 968, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 425, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 1130, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 889, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 64, 1, true, false },
{ GR64_ArgRef_and_GR64_TC, GR64_ArgRef_and_GR64_TCBits, 676, 1, sizeof(GR64_ArgRef_and_GR64_TCBits), X86::GR64_ArgRef_and_GR64_TCRegClassID, 64, 1, true, false },
{ GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1375, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 922, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef, GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits, 1579, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB, GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits, 378, 1, sizeof(GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 1083, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 509, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 796, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 64, 1, true, false },
{ GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 842, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 64, 1, true, false },
{ RST, RSTBits, 1402, 8, sizeof(RSTBits), X86::RSTRegClassID, 80, 1, false, false },
{ RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 80, 1, true, false },
{ RFP80_7, RFP80_7Bits, 351, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 80, 1, false, false },
{ VR128X, VR128XBits, 1431, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 128, 1, true, false },
{ VR128, VR128Bits, 359, 16, sizeof(VR128Bits), X86::VR128RegClassID, 128, 1, true, false },
{ VR256X, VR256XBits, 1424, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 256, 1, true, false },
{ VR256, VR256Bits, 345, 16, sizeof(VR256Bits), X86::VR256RegClassID, 256, 1, true, false },
{ VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 512, 1, true, false },
{ VR512_0_15, VR512_0_15Bits, 313, 16, sizeof(VR512_0_15Bits), X86::VR512_0_15RegClassID, 512, 1, true, false },
{ TILE, TILEBits, 746, 8, sizeof(TILEBits), X86::TILERegClassID, 8192, -1, true, false },
{ TILEPAIR, TILEPAIRBits, 1366, 4, sizeof(TILEPAIRBits), X86::TILEPAIRRegClassID, 16384, 1, true, false },
};
// X86 Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
{ 0U, X86::RAX },
{ 1U, X86::RDX },
{ 2U, X86::RCX },
{ 3U, X86::RBX },
{ 4U, X86::RSI },
{ 5U, X86::RDI },
{ 6U, X86::RBP },
{ 7U, X86::RSP },
{ 8U, X86::R8 },
{ 9U, X86::R9 },
{ 10U, X86::R10 },
{ 11U, X86::R11 },
{ 12U, X86::R12 },
{ 13U, X86::R13 },
{ 14U, X86::R14 },
{ 15U, X86::R15 },
{ 16U, X86::RIP },
{ 17U, X86::XMM0 },
{ 18U, X86::XMM1 },
{ 19U, X86::XMM2 },
{ 20U, X86::XMM3 },
{ 21U, X86::XMM4 },
{ 22U, X86::XMM5 },
{ 23U, X86::XMM6 },
{ 24U, X86::XMM7 },
{ 25U, X86::XMM8 },
{ 26U, X86::XMM9 },
{ 27U, X86::XMM10 },
{ 28U, X86::XMM11 },
{ 29U, X86::XMM12 },
{ 30U, X86::XMM13 },
{ 31U, X86::XMM14 },
{ 32U, X86::XMM15 },
{ 33U, X86::ST0 },
{ 34U, X86::ST1 },
{ 35U, X86::ST2 },
{ 36U, X86::ST3 },
{ 37U, X86::ST4 },
{ 38U, X86::ST5 },
{ 39U, X86::ST6 },
{ 40U, X86::ST7 },
{ 41U, X86::MM0 },
{ 42U, X86::MM1 },
{ 43U, X86::MM2 },
{ 44U, X86::MM3 },
{ 45U, X86::MM4 },
{ 46U, X86::MM5 },
{ 47U, X86::MM6 },
{ 48U, X86::MM7 },
{ 49U, X86::RFLAGS },
{ 50U, X86::ES },
{ 51U, X86::CS },
{ 52U, X86::SS },
{ 53U, X86::DS },
{ 54U, X86::FS },
{ 55U, X86::GS },
{ 58U, X86::FS_BASE },
{ 59U, X86::GS_BASE },
{ 67U, X86::XMM16 },
{ 68U, X86::XMM17 },
{ 69U, X86::XMM18 },
{ 70U, X86::XMM19 },
{ 71U, X86::XMM20 },
{ 72U, X86::XMM21 },
{ 73U, X86::XMM22 },
{ 74U, X86::XMM23 },
{ 75U, X86::XMM24 },
{ 76U, X86::XMM25 },
{ 77U, X86::XMM26 },
{ 78U, X86::XMM27 },
{ 79U, X86::XMM28 },
{ 80U, X86::XMM29 },
{ 81U, X86::XMM30 },
{ 82U, X86::XMM31 },
{ 118U, X86::K0 },
{ 119U, X86::K1 },
{ 120U, X86::K2 },
{ 121U, X86::K3 },
{ 122U, X86::K4 },
{ 123U, X86::K5 },
{ 124U, X86::K6 },
{ 125U, X86::K7 },
{ 130U, X86::R16 },
{ 131U, X86::R17 },
{ 132U, X86::R18 },
{ 133U, X86::R19 },
{ 134U, X86::R20 },
{ 135U, X86::R21 },
{ 136U, X86::R22 },
{ 137U, X86::R23 },
{ 138U, X86::R24 },
{ 139U, X86::R25 },
{ 140U, X86::R26 },
{ 141U, X86::R27 },
{ 142U, X86::R28 },
{ 143U, X86::R29 },
{ 144U, X86::R30 },
{ 145U, X86::R31 },
};
extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::EBP },
{ 5U, X86::ESP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 12U, X86::ST0 },
{ 13U, X86::ST1 },
{ 14U, X86::ST2 },
{ 15U, X86::ST3 },
{ 16U, X86::ST4 },
{ 17U, X86::ST5 },
{ 18U, X86::ST6 },
{ 19U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::ESP },
{ 5U, X86::EBP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 11U, X86::ST0 },
{ 12U, X86::ST1 },
{ 13U, X86::ST2 },
{ 14U, X86::ST3 },
{ 15U, X86::ST4 },
{ 16U, X86::ST5 },
{ 17U, X86::ST6 },
{ 18U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 40U, X86::ES },
{ 41U, X86::CS },
{ 42U, X86::SS },
{ 43U, X86::DS },
{ 44U, X86::FS },
{ 45U, X86::GS },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
{ 0U, X86::RAX },
{ 1U, X86::RDX },
{ 2U, X86::RCX },
{ 3U, X86::RBX },
{ 4U, X86::RSI },
{ 5U, X86::RDI },
{ 6U, X86::RBP },
{ 7U, X86::RSP },
{ 8U, X86::R8 },
{ 9U, X86::R9 },
{ 10U, X86::R10 },
{ 11U, X86::R11 },
{ 12U, X86::R12 },
{ 13U, X86::R13 },
{ 14U, X86::R14 },
{ 15U, X86::R15 },
{ 16U, X86::RIP },
{ 17U, X86::XMM0 },
{ 18U, X86::XMM1 },
{ 19U, X86::XMM2 },
{ 20U, X86::XMM3 },
{ 21U, X86::XMM4 },
{ 22U, X86::XMM5 },
{ 23U, X86::XMM6 },
{ 24U, X86::XMM7 },
{ 25U, X86::XMM8 },
{ 26U, X86::XMM9 },
{ 27U, X86::XMM10 },
{ 28U, X86::XMM11 },
{ 29U, X86::XMM12 },
{ 30U, X86::XMM13 },
{ 31U, X86::XMM14 },
{ 32U, X86::XMM15 },
{ 33U, X86::ST0 },
{ 34U, X86::ST1 },
{ 35U, X86::ST2 },
{ 36U, X86::ST3 },
{ 37U, X86::ST4 },
{ 38U, X86::ST5 },
{ 39U, X86::ST6 },
{ 40U, X86::ST7 },
{ 41U, X86::MM0 },
{ 42U, X86::MM1 },
{ 43U, X86::MM2 },
{ 44U, X86::MM3 },
{ 45U, X86::MM4 },
{ 46U, X86::MM5 },
{ 47U, X86::MM6 },
{ 48U, X86::MM7 },
{ 49U, X86::RFLAGS },
{ 50U, X86::ES },
{ 51U, X86::CS },
{ 52U, X86::SS },
{ 53U, X86::DS },
{ 54U, X86::FS },
{ 55U, X86::GS },
{ 58U, X86::FS_BASE },
{ 59U, X86::GS_BASE },
{ 67U, X86::XMM16 },
{ 68U, X86::XMM17 },
{ 69U, X86::XMM18 },
{ 70U, X86::XMM19 },
{ 71U, X86::XMM20 },
{ 72U, X86::XMM21 },
{ 73U, X86::XMM22 },
{ 74U, X86::XMM23 },
{ 75U, X86::XMM24 },
{ 76U, X86::XMM25 },
{ 77U, X86::XMM26 },
{ 78U, X86::XMM27 },
{ 79U, X86::XMM28 },
{ 80U, X86::XMM29 },
{ 81U, X86::XMM30 },
{ 82U, X86::XMM31 },
{ 118U, X86::K0 },
{ 119U, X86::K1 },
{ 120U, X86::K2 },
{ 121U, X86::K3 },
{ 122U, X86::K4 },
{ 123U, X86::K5 },
{ 124U, X86::K6 },
{ 125U, X86::K7 },
{ 130U, X86::R16 },
{ 131U, X86::R17 },
{ 132U, X86::R18 },
{ 133U, X86::R19 },
{ 134U, X86::R20 },
{ 135U, X86::R21 },
{ 136U, X86::R22 },
{ 137U, X86::R23 },
{ 138U, X86::R24 },
{ 139U, X86::R25 },
{ 140U, X86::R26 },
{ 141U, X86::R27 },
{ 142U, X86::R28 },
{ 143U, X86::R29 },
{ 144U, X86::R30 },
{ 145U, X86::R31 },
};
extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::EBP },
{ 5U, X86::ESP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 12U, X86::ST0 },
{ 13U, X86::ST1 },
{ 14U, X86::ST2 },
{ 15U, X86::ST3 },
{ 16U, X86::ST4 },
{ 17U, X86::ST5 },
{ 18U, X86::ST6 },
{ 19U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::ESP },
{ 5U, X86::EBP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 11U, X86::ST0 },
{ 12U, X86::ST1 },
{ 13U, X86::ST2 },
{ 14U, X86::ST3 },
{ 15U, X86::ST4 },
{ 16U, X86::ST5 },
{ 17U, X86::ST6 },
{ 18U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 40U, X86::ES },
{ 41U, X86::CS },
{ 42U, X86::SS },
{ 43U, X86::DS },
{ 44U, X86::FS },
{ 45U, X86::GS },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
{ X86::CS, 51U },
{ X86::DS, 53U },
{ X86::EAX, -2U },
{ X86::EBP, -2U },
{ X86::EBX, -2U },
{ X86::ECX, -2U },
{ X86::EDI, -2U },
{ X86::EDX, -2U },
{ X86::EFLAGS, 49U },
{ X86::EIP, -2U },
{ X86::ES, 50U },
{ X86::ESI, -2U },
{ X86::ESP, -2U },
{ X86::FS, 54U },
{ X86::FS_BASE, 58U },
{ X86::GS, 55U },
{ X86::GS_BASE, 59U },
{ X86::RAX, 0U },
{ X86::RBP, 6U },
{ X86::RBX, 3U },
{ X86::RCX, 2U },
{ X86::RDI, 5U },
{ X86::RDX, 1U },
{ X86::RFLAGS, 49U },
{ X86::RIP, 16U },
{ X86::RSI, 4U },
{ X86::RSP, 7U },
{ X86::SS, 52U },
{ X86::_EFLAGS, 49U },
{ X86::MM0, 41U },
{ X86::MM1, 42U },
{ X86::MM2, 43U },
{ X86::MM3, 44U },
{ X86::MM4, 45U },
{ X86::MM5, 46U },
{ X86::MM6, 47U },
{ X86::MM7, 48U },
{ X86::R8, 8U },
{ X86::R9, 9U },
{ X86::R10, 10U },
{ X86::R11, 11U },
{ X86::R12, 12U },
{ X86::R13, 13U },
{ X86::R14, 14U },
{ X86::R15, 15U },
{ X86::ST0, 33U },
{ X86::ST1, 34U },
{ X86::ST2, 35U },
{ X86::ST3, 36U },
{ X86::ST4, 37U },
{ X86::ST5, 38U },
{ X86::ST6, 39U },
{ X86::ST7, 40U },
{ X86::XMM0, 17U },
{ X86::XMM1, 18U },
{ X86::XMM2, 19U },
{ X86::XMM3, 20U },
{ X86::XMM4, 21U },
{ X86::XMM5, 22U },
{ X86::XMM6, 23U },
{ X86::XMM7, 24U },
{ X86::XMM8, 25U },
{ X86::XMM9, 26U },
{ X86::XMM10, 27U },
{ X86::XMM11, 28U },
{ X86::XMM12, 29U },
{ X86::XMM13, 30U },
{ X86::XMM14, 31U },
{ X86::XMM15, 32U },
{ X86::YMM0, 17U },
{ X86::YMM1, 18U },
{ X86::YMM2, 19U },
{ X86::YMM3, 20U },
{ X86::YMM4, 21U },
{ X86::YMM5, 22U },
{ X86::YMM6, 23U },
{ X86::YMM7, 24U },
{ X86::YMM8, 25U },
{ X86::YMM9, 26U },
{ X86::YMM10, 27U },
{ X86::YMM11, 28U },
{ X86::YMM12, 29U },
{ X86::YMM13, 30U },
{ X86::YMM14, 31U },
{ X86::YMM15, 32U },
{ X86::K0, 118U },
{ X86::K1, 119U },
{ X86::K2, 120U },
{ X86::K3, 121U },
{ X86::K4, 122U },
{ X86::K5, 123U },
{ X86::K6, 124U },
{ X86::K7, 125U },
{ X86::XMM16, 67U },
{ X86::XMM17, 68U },
{ X86::XMM18, 69U },
{ X86::XMM19, 70U },
{ X86::XMM20, 71U },
{ X86::XMM21, 72U },
{ X86::XMM22, 73U },
{ X86::XMM23, 74U },
{ X86::XMM24, 75U },
{ X86::XMM25, 76U },
{ X86::XMM26, 77U },
{ X86::XMM27, 78U },
{ X86::XMM28, 79U },
{ X86::XMM29, 80U },
{ X86::XMM30, 81U },
{ X86::XMM31, 82U },
{ X86::YMM16, 67U },
{ X86::YMM17, 68U },
{ X86::YMM18, 69U },
{ X86::YMM19, 70U },
{ X86::YMM20, 71U },
{ X86::YMM21, 72U },
{ X86::YMM22, 73U },
{ X86::YMM23, 74U },
{ X86::YMM24, 75U },
{ X86::YMM25, 76U },
{ X86::YMM26, 77U },
{ X86::YMM27, 78U },
{ X86::YMM28, 79U },
{ X86::YMM29, 80U },
{ X86::YMM30, 81U },
{ X86::YMM31, 82U },
{ X86::ZMM0, 17U },
{ X86::ZMM1, 18U },
{ X86::ZMM2, 19U },
{ X86::ZMM3, 20U },
{ X86::ZMM4, 21U },
{ X86::ZMM5, 22U },
{ X86::ZMM6, 23U },
{ X86::ZMM7, 24U },
{ X86::ZMM8, 25U },
{ X86::ZMM9, 26U },
{ X86::ZMM10, 27U },
{ X86::ZMM11, 28U },
{ X86::ZMM12, 29U },
{ X86::ZMM13, 30U },
{ X86::ZMM14, 31U },
{ X86::ZMM15, 32U },
{ X86::ZMM16, 67U },
{ X86::ZMM17, 68U },
{ X86::ZMM18, 69U },
{ X86::ZMM19, 70U },
{ X86::ZMM20, 71U },
{ X86::ZMM21, 72U },
{ X86::ZMM22, 73U },
{ X86::ZMM23, 74U },
{ X86::ZMM24, 75U },
{ X86::ZMM25, 76U },
{ X86::ZMM26, 77U },
{ X86::ZMM27, 78U },
{ X86::ZMM28, 79U },
{ X86::ZMM29, 80U },
{ X86::ZMM30, 81U },
{ X86::ZMM31, 82U },
{ X86::R16, 130U },
{ X86::R17, 131U },
{ X86::R18, 132U },
{ X86::R19, 133U },
{ X86::R20, 134U },
{ X86::R21, 135U },
{ X86::R22, 136U },
{ X86::R23, 137U },
{ X86::R24, 138U },
{ X86::R25, 139U },
{ X86::R26, 140U },
{ X86::R27, 141U },
{ X86::R28, 142U },
{ X86::R29, 143U },
{ X86::R30, 144U },
{ X86::R31, 145U },
};
extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
{ X86::CS, -2U },
{ X86::DS, -2U },
{ X86::EAX, 0U },
{ X86::EBP, 4U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ES, -2U },
{ X86::ESI, 6U },
{ X86::ESP, 5U },
{ X86::FS, -2U },
{ X86::FS_BASE, -2U },
{ X86::GS, -2U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::SS, -2U },
{ X86::_EFLAGS, 9U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 12U },
{ X86::ST1, 13U },
{ X86::ST2, 14U },
{ X86::ST3, 15U },
{ X86::ST4, 16U },
{ X86::ST5, 17U },
{ X86::ST6, 18U },
{ X86::ST7, 19U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
{ X86::R16, -2U },
{ X86::R17, -2U },
{ X86::R18, -2U },
{ X86::R19, -2U },
{ X86::R20, -2U },
{ X86::R21, -2U },
{ X86::R22, -2U },
{ X86::R23, -2U },
{ X86::R24, -2U },
{ X86::R25, -2U },
{ X86::R26, -2U },
{ X86::R27, -2U },
{ X86::R28, -2U },
{ X86::R29, -2U },
{ X86::R30, -2U },
{ X86::R31, -2U },
};
extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
{ X86::CS, 41U },
{ X86::DS, 43U },
{ X86::EAX, 0U },
{ X86::EBP, 5U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ES, 40U },
{ X86::ESI, 6U },
{ X86::ESP, 4U },
{ X86::FS, 44U },
{ X86::FS_BASE, -2U },
{ X86::GS, 45U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::SS, 42U },
{ X86::_EFLAGS, 9U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 11U },
{ X86::ST1, 12U },
{ X86::ST2, 13U },
{ X86::ST3, 14U },
{ X86::ST4, 15U },
{ X86::ST5, 16U },
{ X86::ST6, 17U },
{ X86::ST7, 18U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
{ X86::R16, -2U },
{ X86::R17, -2U },
{ X86::R18, -2U },
{ X86::R19, -2U },
{ X86::R20, -2U },
{ X86::R21, -2U },
{ X86::R22, -2U },
{ X86::R23, -2U },
{ X86::R24, -2U },
{ X86::R25, -2U },
{ X86::R26, -2U },
{ X86::R27, -2U },
{ X86::R28, -2U },
{ X86::R29, -2U },
{ X86::R30, -2U },
{ X86::R31, -2U },
};
extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
{ X86::CS, 51U },
{ X86::DS, 53U },
{ X86::EAX, -2U },
{ X86::EBP, -2U },
{ X86::EBX, -2U },
{ X86::ECX, -2U },
{ X86::EDI, -2U },
{ X86::EDX, -2U },
{ X86::EFLAGS, 49U },
{ X86::EIP, -2U },
{ X86::ES, 50U },
{ X86::ESI, -2U },
{ X86::ESP, -2U },
{ X86::FS, 54U },
{ X86::FS_BASE, 58U },
{ X86::GS, 55U },
{ X86::GS_BASE, 59U },
{ X86::RAX, 0U },
{ X86::RBP, 6U },
{ X86::RBX, 3U },
{ X86::RCX, 2U },
{ X86::RDI, 5U },
{ X86::RDX, 1U },
{ X86::RFLAGS, 49U },
{ X86::RIP, 16U },
{ X86::RSI, 4U },
{ X86::RSP, 7U },
{ X86::SS, 52U },
{ X86::_EFLAGS, 49U },
{ X86::MM0, 41U },
{ X86::MM1, 42U },
{ X86::MM2, 43U },
{ X86::MM3, 44U },
{ X86::MM4, 45U },
{ X86::MM5, 46U },
{ X86::MM6, 47U },
{ X86::MM7, 48U },
{ X86::R8, 8U },
{ X86::R9, 9U },
{ X86::R10, 10U },
{ X86::R11, 11U },
{ X86::R12, 12U },
{ X86::R13, 13U },
{ X86::R14, 14U },
{ X86::R15, 15U },
{ X86::ST0, 33U },
{ X86::ST1, 34U },
{ X86::ST2, 35U },
{ X86::ST3, 36U },
{ X86::ST4, 37U },
{ X86::ST5, 38U },
{ X86::ST6, 39U },
{ X86::ST7, 40U },
{ X86::XMM0, 17U },
{ X86::XMM1, 18U },
{ X86::XMM2, 19U },
{ X86::XMM3, 20U },
{ X86::XMM4, 21U },
{ X86::XMM5, 22U },
{ X86::XMM6, 23U },
{ X86::XMM7, 24U },
{ X86::XMM8, 25U },
{ X86::XMM9, 26U },
{ X86::XMM10, 27U },
{ X86::XMM11, 28U },
{ X86::XMM12, 29U },
{ X86::XMM13, 30U },
{ X86::XMM14, 31U },
{ X86::XMM15, 32U },
{ X86::YMM0, 17U },
{ X86::YMM1, 18U },
{ X86::YMM2, 19U },
{ X86::YMM3, 20U },
{ X86::YMM4, 21U },
{ X86::YMM5, 22U },
{ X86::YMM6, 23U },
{ X86::YMM7, 24U },
{ X86::YMM8, 25U },
{ X86::YMM9, 26U },
{ X86::YMM10, 27U },
{ X86::YMM11, 28U },
{ X86::YMM12, 29U },
{ X86::YMM13, 30U },
{ X86::YMM14, 31U },
{ X86::YMM15, 32U },
{ X86::K0, 118U },
{ X86::K1, 119U },
{ X86::K2, 120U },
{ X86::K3, 121U },
{ X86::K4, 122U },
{ X86::K5, 123U },
{ X86::K6, 124U },
{ X86::K7, 125U },
{ X86::XMM16, 67U },
{ X86::XMM17, 68U },
{ X86::XMM18, 69U },
{ X86::XMM19, 70U },
{ X86::XMM20, 71U },
{ X86::XMM21, 72U },
{ X86::XMM22, 73U },
{ X86::XMM23, 74U },
{ X86::XMM24, 75U },
{ X86::XMM25, 76U },
{ X86::XMM26, 77U },
{ X86::XMM27, 78U },
{ X86::XMM28, 79U },
{ X86::XMM29, 80U },
{ X86::XMM30, 81U },
{ X86::XMM31, 82U },
{ X86::YMM16, 67U },
{ X86::YMM17, 68U },
{ X86::YMM18, 69U },
{ X86::YMM19, 70U },
{ X86::YMM20, 71U },
{ X86::YMM21, 72U },
{ X86::YMM22, 73U },
{ X86::YMM23, 74U },
{ X86::YMM24, 75U },
{ X86::YMM25, 76U },
{ X86::YMM26, 77U },
{ X86::YMM27, 78U },
{ X86::YMM28, 79U },
{ X86::YMM29, 80U },
{ X86::YMM30, 81U },
{ X86::YMM31, 82U },
{ X86::ZMM0, 17U },
{ X86::ZMM1, 18U },
{ X86::ZMM2, 19U },
{ X86::ZMM3, 20U },
{ X86::ZMM4, 21U },
{ X86::ZMM5, 22U },
{ X86::ZMM6, 23U },
{ X86::ZMM7, 24U },
{ X86::ZMM8, 25U },
{ X86::ZMM9, 26U },
{ X86::ZMM10, 27U },
{ X86::ZMM11, 28U },
{ X86::ZMM12, 29U },
{ X86::ZMM13, 30U },
{ X86::ZMM14, 31U },
{ X86::ZMM15, 32U },
{ X86::ZMM16, 67U },
{ X86::ZMM17, 68U },
{ X86::ZMM18, 69U },
{ X86::ZMM19, 70U },
{ X86::ZMM20, 71U },
{ X86::ZMM21, 72U },
{ X86::ZMM22, 73U },
{ X86::ZMM23, 74U },
{ X86::ZMM24, 75U },
{ X86::ZMM25, 76U },
{ X86::ZMM26, 77U },
{ X86::ZMM27, 78U },
{ X86::ZMM28, 79U },
{ X86::ZMM29, 80U },
{ X86::ZMM30, 81U },
{ X86::ZMM31, 82U },
{ X86::R16, 130U },
{ X86::R17, 131U },
{ X86::R18, 132U },
{ X86::R19, 133U },
{ X86::R20, 134U },
{ X86::R21, 135U },
{ X86::R22, 136U },
{ X86::R23, 137U },
{ X86::R24, 138U },
{ X86::R25, 139U },
{ X86::R26, 140U },
{ X86::R27, 141U },
{ X86::R28, 142U },
{ X86::R29, 143U },
{ X86::R30, 144U },
{ X86::R31, 145U },
};
extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
{ X86::CS, -2U },
{ X86::DS, -2U },
{ X86::EAX, 0U },
{ X86::EBP, 4U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ES, -2U },
{ X86::ESI, 6U },
{ X86::ESP, 5U },
{ X86::FS, -2U },
{ X86::FS_BASE, -2U },
{ X86::GS, -2U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::SS, -2U },
{ X86::_EFLAGS, 9U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 12U },
{ X86::ST1, 13U },
{ X86::ST2, 14U },
{ X86::ST3, 15U },
{ X86::ST4, 16U },
{ X86::ST5, 17U },
{ X86::ST6, 18U },
{ X86::ST7, 19U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
{ X86::R16, -2U },
{ X86::R17, -2U },
{ X86::R18, -2U },
{ X86::R19, -2U },
{ X86::R20, -2U },
{ X86::R21, -2U },
{ X86::R22, -2U },
{ X86::R23, -2U },
{ X86::R24, -2U },
{ X86::R25, -2U },
{ X86::R26, -2U },
{ X86::R27, -2U },
{ X86::R28, -2U },
{ X86::R29, -2U },
{ X86::R30, -2U },
{ X86::R31, -2U },
};
extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
{ X86::CS, 41U },
{ X86::DS, 43U },
{ X86::EAX, 0U },
{ X86::EBP, 5U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ES, 40U },
{ X86::ESI, 6U },
{ X86::ESP, 4U },
{ X86::FS, 44U },
{ X86::FS_BASE, -2U },
{ X86::GS, 45U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::SS, 42U },
{ X86::_EFLAGS, 9U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 11U },
{ X86::ST1, 12U },
{ X86::ST2, 13U },
{ X86::ST3, 14U },
{ X86::ST4, 15U },
{ X86::ST5, 16U },
{ X86::ST6, 17U },
{ X86::ST7, 18U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
{ X86::R16, -2U },
{ X86::R17, -2U },
{ X86::R18, -2U },
{ X86::R19, -2U },
{ X86::R20, -2U },
{ X86::R21, -2U },
{ X86::R22, -2U },
{ X86::R23, -2U },
{ X86::R24, -2U },
{ X86::R25, -2U },
{ X86::R26, -2U },
{ X86::R27, -2U },
{ X86::R28, -2U },
{ X86::R29, -2U },
{ X86::R30, -2U },
{ X86::R31, -2U },
};
extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
extern const uint16_t X86RegEncodingTable[] = {
0,
4,
0,
0,
7,
3,
5,
65535,
5,
3,
5,
1,
1,
1,
0,
6,
7,
65535,
7,
2,
3,
2,
0,
5,
3,
1,
7,
2,
0,
0,
4,
0,
6,
4,
0,
0,
4,
0,
5,
0,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
0,
0,
0,
5,
3,
1,
7,
2,
0,
0,
4,
6,
4,
6,
65535,
6,
4,
65535,
4,
2,
0,
0,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
8,
9,
10,
11,
12,
13,
14,
15,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
8,
9,
10,
11,
12,
13,
14,
15,
8,
9,
10,
11,
12,
13,
14,
15,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
1,
2,
3,
4,
5,
6,
7,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
2,
4,
6,
0,
0,
1,
2,
3,
4,
5,
6,
7,
0,
2,
4,
6,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
};
static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
RI->InitMCRegisterInfo(X86RegDesc, 392, RA, PC, X86MCRegisterClasses, 135, X86RegUnitRoots, 221, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 13,
X86RegEncodingTable);
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
break;
case 1:
RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
break;
case 2:
RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
break;
case 1:
RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
break;
case 2:
RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
break;
}
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
break;
case 1:
RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
break;
case 2:
RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
break;
case 1:
RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
break;
case 2:
RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
break;
}
}
} // end namespace llvm
#endif // GET_REGINFO_MC_DESC
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Register Information Header Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER
#include "llvm/CodeGen/TargetRegisterInfo.h"
namespace llvm {
class X86FrameLowering;
struct X86GenRegisterInfo : public TargetRegisterInfo {
explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
unsigned PC = 0, unsigned HwMode = 0);
unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
unsigned getRegUnitWeight(unsigned RegUnit) const override;
unsigned getNumRegPressureSets() const override;
const char *getRegPressureSetName(unsigned Idx) const override;
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
const int *getRegUnitPressureSets(unsigned RegUnit) const override;
ArrayRef<const char *> getRegMaskNames() const override;
ArrayRef<const uint32_t *> getRegMasks() const override;
bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
bool isFixedRegister(const MachineFunction &, MCRegister) const override;
bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
bool isConstantPhysReg(MCRegister PhysReg) const override final;
/// Devirtualized TargetFrameLowering.
static const X86FrameLowering *getFrameLowering(
const MachineFunction &MF);
};
namespace X86 { // Register classes
extern const TargetRegisterClass GR8RegClass;
extern const TargetRegisterClass GRH8RegClass;
extern const TargetRegisterClass GR8_NOREX2RegClass;
extern const TargetRegisterClass GR8_NOREXRegClass;
extern const TargetRegisterClass GR8_ABCD_HRegClass;
extern const TargetRegisterClass GR8_ABCD_LRegClass;
extern const TargetRegisterClass GRH16RegClass;
extern const TargetRegisterClass GR16RegClass;
extern const TargetRegisterClass GR16_NOREX2RegClass;
extern const TargetRegisterClass GR16_NOREXRegClass;
extern const TargetRegisterClass VK1RegClass;
extern const TargetRegisterClass VK16RegClass;
extern const TargetRegisterClass VK2RegClass;
extern const TargetRegisterClass VK4RegClass;
extern const TargetRegisterClass VK8RegClass;
extern const TargetRegisterClass VK16WMRegClass;
extern const TargetRegisterClass VK1WMRegClass;
extern const TargetRegisterClass VK2WMRegClass;
extern const TargetRegisterClass VK4WMRegClass;
extern const TargetRegisterClass VK8WMRegClass;
extern const TargetRegisterClass SEGMENT_REGRegClass;
extern const TargetRegisterClass GR16_ABCDRegClass;
extern const TargetRegisterClass FPCCRRegClass;
extern const TargetRegisterClass FR16XRegClass;
extern const TargetRegisterClass FR16RegClass;
extern const TargetRegisterClass VK16PAIRRegClass;
extern const TargetRegisterClass VK1PAIRRegClass;
extern const TargetRegisterClass VK2PAIRRegClass;
extern const TargetRegisterClass VK4PAIRRegClass;
extern const TargetRegisterClass VK8PAIRRegClass;
extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
extern const TargetRegisterClass FR32XRegClass;
extern const TargetRegisterClass GR32RegClass;
extern const TargetRegisterClass GR32_NOSPRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass;
extern const TargetRegisterClass DEBUG_REGRegClass;
extern const TargetRegisterClass FR32RegClass;
extern const TargetRegisterClass GR32_NOREX2RegClass;
extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
extern const TargetRegisterClass GR32_NOREXRegClass;
extern const TargetRegisterClass VK32RegClass;
extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
extern const TargetRegisterClass RFP32RegClass;
extern const TargetRegisterClass VK32WMRegClass;
extern const TargetRegisterClass GR32_ABCDRegClass;
extern const TargetRegisterClass GR32_TCRegClass;
extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
extern const TargetRegisterClass GR32_ADRegClass;
extern const TargetRegisterClass GR32_ArgRefRegClass;
extern const TargetRegisterClass GR32_BPSPRegClass;
extern const TargetRegisterClass GR32_BSIRegClass;
extern const TargetRegisterClass GR32_CBRegClass;
extern const TargetRegisterClass GR32_DCRegClass;
extern const TargetRegisterClass GR32_DIBPRegClass;
extern const TargetRegisterClass GR32_SIDIRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
extern const TargetRegisterClass CCRRegClass;
extern const TargetRegisterClass DFCCRRegClass;
extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass;
extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass;
extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
extern const TargetRegisterClass RFP64RegClass;
extern const TargetRegisterClass GR64RegClass;
extern const TargetRegisterClass FR64XRegClass;
extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
extern const TargetRegisterClass GR64_NOSPRegClass;
extern const TargetRegisterClass GR64_NOREX2RegClass;
extern const TargetRegisterClass CONTROL_REGRegClass;
extern const TargetRegisterClass FR64RegClass;
extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass;
extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass;
extern const TargetRegisterClass GR64PLTSafeRegClass;
extern const TargetRegisterClass GR64_TCRegClass;
extern const TargetRegisterClass GR64_NOREXRegClass;
extern const TargetRegisterClass GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
extern const TargetRegisterClass VK64RegClass;
extern const TargetRegisterClass VR64RegClass;
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
extern const TargetRegisterClass VK64WMRegClass;
extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_ABCDRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
extern const TargetRegisterClass GR64_ADRegClass;
extern const TargetRegisterClass GR64_ArgRefRegClass;
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
extern const TargetRegisterClass RSTRegClass;
extern const TargetRegisterClass RFP80RegClass;
extern const TargetRegisterClass RFP80_7RegClass;
extern const TargetRegisterClass VR128XRegClass;
extern const TargetRegisterClass VR128RegClass;
extern const TargetRegisterClass VR256XRegClass;
extern const TargetRegisterClass VR256RegClass;
extern const TargetRegisterClass VR512RegClass;
extern const TargetRegisterClass VR512_0_15RegClass;
extern const TargetRegisterClass TILERegClass;
extern const TargetRegisterClass TILEPAIRRegClass;
} // end namespace X86
} // end namespace llvm
#endif // GET_REGINFO_HEADER
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register and Register Classes Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC
namespace llvm {
extern const MCRegisterClass X86MCRegisterClasses[];
static const MVT::SimpleValueType VTLists[] = {
/* 0 */ MVT::i8, MVT::Other,
/* 2 */ MVT::i16, MVT::Other,
/* 4 */ MVT::i32, MVT::Other,
/* 6 */ MVT::i64, MVT::Other,
/* 8 */ MVT::f16, MVT::Other,
/* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
/* 14 */ MVT::f64, MVT::Other,
/* 16 */ MVT::f80, MVT::Other,
/* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
/* 28 */ MVT::v1i1, MVT::Other,
/* 30 */ MVT::v2i1, MVT::Other,
/* 32 */ MVT::v4i1, MVT::Other,
/* 34 */ MVT::v8i1, MVT::Other,
/* 36 */ MVT::v16i1, MVT::Other,
/* 38 */ MVT::v32i1, MVT::Other,
/* 40 */ MVT::v64i1, MVT::Other,
/* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
/* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
/* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
/* 67 */ MVT::x86mmx, MVT::Other,
/* 69 */ MVT::Untyped, MVT::Other,
/* 71 */ MVT::x86amx, MVT::Other,
};
static const char *SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_t0", "sub_t1", "sub_xmm", "sub_ymm", "" };
static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
{ 65535, 65535 },
{ 0, 8 }, // sub_8bit
{ 8, 8 }, // sub_8bit_hi
{ 8, 8 }, // sub_8bit_hi_phony
{ 0, 16 }, // sub_16bit
{ 16, 16 }, // sub_16bit_hi
{ 0, 32 }, // sub_32bit
{ 0, 65535 }, // sub_mask_0
{ 65535, 65535 }, // sub_mask_1
{ 0, 8192 }, // sub_t0
{ 8192, 8192 }, // sub_t1
{ 0, 128 }, // sub_xmm
{ 0, 256 }, // sub_ymm
};
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
LaneBitmask::getAll(),
LaneBitmask(0x0000000000000001), // sub_8bit
LaneBitmask(0x0000000000000002), // sub_8bit_hi
LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
LaneBitmask(0x0000000000000007), // sub_16bit
LaneBitmask(0x0000000000000008), // sub_16bit_hi
LaneBitmask(0x000000000000000F), // sub_32bit
LaneBitmask(0x0000000000000010), // sub_mask_0
LaneBitmask(0x0000000000000020), // sub_mask_1
LaneBitmask(0x0000000000000040), // sub_t0
LaneBitmask(0x0000000000000080), // sub_t1
LaneBitmask(0x0000000000000100), // sub_xmm
LaneBitmask(0x0000000000000100), // sub_ymm
};
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
// Mode = 0 (Default)
{ 8, 8, 8, /*VTLists+*/0 }, // GR8
{ 8, 8, 8, /*VTLists+*/0 }, // GRH8
{ 8, 8, 8, /*VTLists+*/0 }, // GR8_NOREX2
{ 8, 8, 8, /*VTLists+*/0 }, // GR8_NOREX
{ 8, 8, 8, /*VTLists+*/0 }, // GR8_ABCD_H
{ 8, 8, 8, /*VTLists+*/0 }, // GR8_ABCD_L
{ 16, 16, 16, /*VTLists+*/2 }, // GRH16
{ 16, 16, 16, /*VTLists+*/2 }, // GR16
{ 16, 16, 16, /*VTLists+*/2 }, // GR16_NOREX2
{ 16, 16, 16, /*VTLists+*/2 }, // GR16_NOREX
{ 16, 16, 16, /*VTLists+*/28 }, // VK1
{ 16, 16, 16, /*VTLists+*/36 }, // VK16
{ 16, 16, 16, /*VTLists+*/30 }, // VK2
{ 16, 16, 16, /*VTLists+*/32 }, // VK4
{ 16, 16, 16, /*VTLists+*/34 }, // VK8
{ 16, 16, 16, /*VTLists+*/36 }, // VK16WM
{ 16, 16, 16, /*VTLists+*/28 }, // VK1WM
{ 16, 16, 16, /*VTLists+*/30 }, // VK2WM
{ 16, 16, 16, /*VTLists+*/32 }, // VK4WM
{ 16, 16, 16, /*VTLists+*/34 }, // VK8WM
{ 16, 16, 16, /*VTLists+*/2 }, // SEGMENT_REG
{ 16, 16, 16, /*VTLists+*/2 }, // GR16_ABCD
{ 16, 16, 16, /*VTLists+*/2 }, // FPCCR
{ 32, 32, 16, /*VTLists+*/8 }, // FR16X
{ 32, 32, 16, /*VTLists+*/8 }, // FR16
{ 32, 32, 16, /*VTLists+*/69 }, // VK16PAIR
{ 32, 32, 16, /*VTLists+*/69 }, // VK1PAIR
{ 32, 32, 16, /*VTLists+*/69 }, // VK2PAIR
{ 32, 32, 16, /*VTLists+*/69 }, // VK4PAIR
{ 32, 32, 16, /*VTLists+*/69 }, // VK8PAIR
{ 32, 32, 16, /*VTLists+*/69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
{ 32, 32, 32, /*VTLists+*/12 }, // FR32X
{ 32, 32, 32, /*VTLists+*/4 }, // GR32
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_NOSP
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
{ 32, 32, 32, /*VTLists+*/4 }, // DEBUG_REG
{ 32, 32, 32, /*VTLists+*/12 }, // FR32
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX2
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX2_NOSP
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX
{ 32, 32, 32, /*VTLists+*/38 }, // VK32
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX_NOSP
{ 32, 32, 32, /*VTLists+*/12 }, // RFP32
{ 32, 32, 32, /*VTLists+*/38 }, // VK32WM
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_TC
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD_and_GR32_TC
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_AD
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_ArgRef
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_BSI
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_CB
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_DC
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_DIBP
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_SIDI
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
{ 32, 32, 32, /*VTLists+*/4 }, // CCR
{ 32, 32, 32, /*VTLists+*/4 }, // DFCCR
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD_and_GR32_BSI
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_AD_and_GR32_ArgRef
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_ArgRef_and_GR32_CB
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP_and_GR32_DIBP
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP_and_GR32_TC
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_BSI_and_GR32_SIDI
{ 32, 32, 32, /*VTLists+*/4 }, // GR32_DIBP_and_GR32_SIDI
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
{ 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
{ 64, 64, 32, /*VTLists+*/14 }, // RFP64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64
{ 64, 64, 64, /*VTLists+*/14 }, // FR64X
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_8bit
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOSP
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2
{ 64, 64, 64, /*VTLists+*/6 }, // CONTROL_REG
{ 64, 64, 64, /*VTLists+*/14 }, // FR64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP
{ 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_with_sub_8bit
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP_and_GR64_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64_with_sub_8bit
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_TCW64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_16bit_in_GR16_NOREX
{ 64, 64, 64, /*VTLists+*/40 }, // VK64
{ 64, 64, 64, /*VTLists+*/67 }, // VR64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe_and_GR64_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_NOSP
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
{ 64, 64, 64, /*VTLists+*/40 }, // VK64WM
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
{ 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe_and_GR64_TCW64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64_TCW64
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_ABCD
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_AD
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_ArgRef
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BSI
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_CB
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_DIBP
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_SIDI
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_ArgRef_and_GR64_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_and_LOW32_ADDR_ACCESS
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
{ 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
{ 80, 80, 32, /*VTLists+*/10 }, // RST
{ 80, 80, 32, /*VTLists+*/16 }, // RFP80
{ 80, 80, 32, /*VTLists+*/16 }, // RFP80_7
{ 128, 128, 128, /*VTLists+*/18 }, // VR128X
{ 128, 128, 128, /*VTLists+*/18 }, // VR128
{ 256, 256, 256, /*VTLists+*/42 }, // VR256X
{ 256, 256, 256, /*VTLists+*/42 }, // VR256
{ 512, 512, 512, /*VTLists+*/51 }, // VR512
{ 512, 512, 512, /*VTLists+*/60 }, // VR512_0_15
{ 8192, 8192, 8192, /*VTLists+*/71 }, // TILE
{ 16384, 16384, 512, /*VTLists+*/69 }, // TILEPAIR
};
static const uint32_t GR8SubClassMask[] = {
0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x0fefefbd, 0x00000000, // sub_8bit
0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
};
static const uint32_t GRH8SubClassMask[] = {
0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t GR8_NOREX2SubClassMask[] = {
0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00200300, 0xc7ff2f20, 0x72e3803f, 0x0fefefbd, 0x00000000, // sub_8bit
0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
};
static const uint32_t GR8_NOREXSubClassMask[] = {
0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit
0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
};
static const uint32_t GR8_ABCD_HSubClassMask[] = {
0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
};
static const uint32_t GR8_ABCD_LSubClassMask[] = {
0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit
};
static const uint32_t GRH16SubClassMask[] = {
0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t GR16SubClassMask[] = {
0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x0fefefbd, 0x00000000, // sub_16bit
};
static const uint32_t GR16_NOREX2SubClassMask[] = {
0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xc7ff2f20, 0x72e3803f, 0x0fefefbd, 0x00000000, // sub_16bit
};
static const uint32_t GR16_NOREXSubClassMask[] = {
0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xc7ff2c00, 0x4200003f, 0x0fe7e7a8, 0x00000000, // sub_16bit
};
static const uint32_t VK1SubClassMask[] = {
0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK16SubClassMask[] = {
0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK2SubClassMask[] = {
0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK4SubClassMask[] = {
0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK8SubClassMask[] = {
0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK16WMSubClassMask[] = {
0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK1WMSubClassMask[] = {
0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK2WMSubClassMask[] = {
0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK4WMSubClassMask[] = {
0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK8WMSubClassMask[] = {
0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t SEGMENT_REGSubClassMask[] = {
0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t GR16_ABCDSubClassMask[] = {
0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_16bit
};
static const uint32_t FPCCRSubClassMask[] = {
0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t FR16XSubClassMask[] = {
0x01800000, 0x00000084, 0x00004200, 0x80000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
};
static const uint32_t FR16SubClassMask[] = {
0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
};
static const uint32_t VK16PAIRSubClassMask[] = {
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK1PAIRSubClassMask[] = {
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK2PAIRSubClassMask[] = {
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK4PAIRSubClassMask[] = {
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK8PAIRSubClassMask[] = {
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask[] = {
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
0x80000000, 0xcfff2f3b, 0x0000007f, 0x01101000, 0x00000000,
0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
0x00000000, 0xc7ff2b19, 0x0000005f, 0x00100000, 0x00000000,
0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
0x00000000, 0xc7ff2f3a, 0x0000003f, 0x01000000, 0x00000000,
0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
};
static const uint32_t FR32XSubClassMask[] = {
0x00000000, 0x00000084, 0x00004200, 0x80000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
};
static const uint32_t GR32SubClassMask[] = {
0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
};
static const uint32_t GR32_NOSPSubClassMask[] = {
0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x70430820, 0x0defaeb4, 0x00000000, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
0x00000000, 0xc7ff2f20, 0x0000003f, 0x01000000, 0x00000000,
0x00000000, 0x00000000, 0x72e38020, 0x0fefefbd, 0x00000000, // sub_32bit
};
static const uint32_t DEBUG_REGSubClassMask[] = {
0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t FR32SubClassMask[] = {
0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
};
static const uint32_t GR32_NOREX2SubClassMask[] = {
0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x72e38020, 0x0fefefbd, 0x00000000, // sub_32bit
};
static const uint32_t GR32_NOREX2_NOSPSubClassMask[] = {
0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x70430020, 0x0defaeb4, 0x00000000, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
0x00000000, 0xc7ff2c00, 0x0000003f, 0x01000000, 0x00000000,
0x00000000, 0x00000000, 0x42000020, 0x0fe7e7a8, 0x00000000, // sub_32bit
};
static const uint32_t GR32_NOREXSubClassMask[] = {
0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x42000020, 0x0fe7e7a8, 0x00000000, // sub_32bit
};
static const uint32_t VK32SubClassMask[] = {
0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x40000020, 0x0de7a6a0, 0x00000000, // sub_32bit
};
static const uint32_t RFP32SubClassMask[] = {
0x00000000, 0x00004000, 0x00000080, 0x20000000, 0x00000000,
};
static const uint32_t VK32WMSubClassMask[] = {
0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t GR32_ABCDSubClassMask[] = {
0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00e12680, 0x00000000, // sub_32bit
};
static const uint32_t GR32_TCSubClassMask[] = {
0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x02c02700, 0x00000000, // sub_32bit
};
static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00c02600, 0x00000000, // sub_32bit
};
static const uint32_t GR32_ADSubClassMask[] = {
0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00400400, 0x00000000, // sub_32bit
};
static const uint32_t GR32_ArgRefSubClassMask[] = {
0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00c02000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_BPSPSubClassMask[] = {
0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000020, 0x03004000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_BSISubClassMask[] = {
0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x04208000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_CBSubClassMask[] = {
0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00a10000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_DCSubClassMask[] = {
0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00c02000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_DIBPSubClassMask[] = {
0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000020, 0x09020000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_SIDISubClassMask[] = {
0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x0c040000, 0x00000000, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
0x00000000, 0x08000000, 0x00000060, 0x01101000, 0x00000000,
};
static const uint32_t CCRSubClassMask[] = {
0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t DFCCRSubClassMask[] = {
0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_AD_and_GR32_ArgRefSubClassMask[] = {
0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_ArgRef_and_GR32_CBSubClassMask[] = {
0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000020, 0x01000000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
};
static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
0x00000000, 0x00000000, 0x00000020, 0x01000000, 0x00000000,
};
static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
0x00000000, 0x00000000, 0x00000040, 0x00100000, 0x00000000,
};
static const uint32_t RFP64SubClassMask[] = {
0x00000000, 0x00000000, 0x00000080, 0x20000000, 0x00000000,
};
static const uint32_t GR64SubClassMask[] = {
0x00000000, 0x00000000, 0xf3ff9d00, 0x0ffffffd, 0x00000000,
};
static const uint32_t FR64XSubClassMask[] = {
0x00000000, 0x00000000, 0x00004200, 0x80000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
};
static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0x72e38c00, 0x0fefefbd, 0x00000000,
};
static const uint32_t GR64_NOSPSubClassMask[] = {
0x00000000, 0x00000000, 0x70430800, 0x0defaeb4, 0x00000000,
};
static const uint32_t GR64_NOREX2SubClassMask[] = {
0x00000000, 0x00000000, 0xf3ff9000, 0x0ffffffd, 0x00000000,
};
static const uint32_t CONTROL_REGSubClassMask[] = {
0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
};
static const uint32_t FR64SubClassMask[] = {
0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
};
static const uint32_t GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
0x00000000, 0x00000000, 0x72e38000, 0x0fefefbd, 0x00000000,
};
static const uint32_t GR64_NOREX2_NOSPSubClassMask[] = {
0x00000000, 0x00000000, 0x70430000, 0x0defaeb4, 0x00000000,
};
static const uint32_t GR64PLTSafeSubClassMask[] = {
0x00000000, 0x00000000, 0x50020000, 0x0de7a6b0, 0x00000000,
};
static const uint32_t GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x91640000, 0x0edc277d, 0x00000000,
};
static const uint32_t GR64_NOREXSubClassMask[] = {
0x00000000, 0x00000000, 0xc2080000, 0x0ff7f7e8, 0x00000000,
};
static const uint32_t GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x21900000, 0x02d82f55, 0x00000000,
};
static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0x10600000, 0x0ecc273d, 0x00000000,
};
static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x10400000, 0x0ccc2634, 0x00000000,
};
static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0x20800000, 0x02c82f15, 0x00000000,
};
static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x01000000, 0x02d82755, 0x00000000,
};
static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
0x00000000, 0x00000000, 0x42000000, 0x0fe7e7a8, 0x00000000,
};
static const uint32_t VK64SubClassMask[] = {
0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VR64SubClassMask[] = {
0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
};
static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x10000000, 0x0cc42630, 0x00000000,
};
static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x20000000, 0x00c82e14, 0x00000000,
};
static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
0x00000000, 0x00000000, 0x40000000, 0x0de7a6a0, 0x00000000,
};
static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x80000000, 0x0ed42768, 0x00000000,
};
static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x02c82715, 0x00000000,
};
static const uint32_t VK64WMSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00c82614, 0x00000000,
};
static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x0ec42728, 0x00000000,
};
static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00c02610, 0x00000000,
};
static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x0cc42620, 0x00000000,
};
static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x02d02740, 0x00000000,
};
static const uint32_t GR64_ABCDSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00e12680, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x02c02700, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00c02600, 0x00000000,
};
static const uint32_t GR64_ADSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00400400, 0x00000000,
};
static const uint32_t GR64_ArgRefSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00080800, 0x00000000,
};
static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x01101000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00c02000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x03004000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x04208000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00a10000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x09020000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x0c040000, 0x00000000,
};
static const uint32_t GR64_ArgRef_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
};
static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
};
static const uint32_t RSTSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
};
static const uint32_t RFP80SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
};
static const uint32_t RFP80_7SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
};
static const uint32_t VR128XSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
};
static const uint32_t VR128SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
};
static const uint32_t VR256XSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000006,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000018, // sub_ymm
};
static const uint32_t VR256SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000004,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010, // sub_ymm
};
static const uint32_t VR512SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000018,
};
static const uint32_t VR512_0_15SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010,
};
static const uint32_t TILESubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040, // sub_t0
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040, // sub_t1
};
static const uint32_t TILEPAIRSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
};
static const uint16_t SuperRegIdxSeqs[] = {
/* 0 */ 1, 0,
/* 2 */ 1, 2, 0,
/* 5 */ 4, 0,
/* 7 */ 6, 0,
/* 9 */ 7, 8, 0,
/* 12 */ 9, 10, 0,
/* 15 */ 11, 0,
/* 17 */ 12, 0,
};
static unsigned const GR8_NOREX2Superclasses[] = {
X86::GR8RegClassID,
};
static unsigned const GR8_NOREXSuperclasses[] = {
X86::GR8RegClassID,
X86::GR8_NOREX2RegClassID,
};
static unsigned const GR8_ABCD_HSuperclasses[] = {
X86::GR8RegClassID,
X86::GR8_NOREX2RegClassID,
X86::GR8_NOREXRegClassID,
};
static unsigned const GR8_ABCD_LSuperclasses[] = {
X86::GR8RegClassID,
X86::GR8_NOREX2RegClassID,
X86::GR8_NOREXRegClassID,
};
static unsigned const GR16_NOREX2Superclasses[] = {
X86::GR16RegClassID,
};
static unsigned const GR16_NOREXSuperclasses[] = {
X86::GR16RegClassID,
X86::GR16_NOREX2RegClassID,
};
static unsigned const VK1Superclasses[] = {
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
};
static unsigned const VK16Superclasses[] = {
X86::VK1RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
};
static unsigned const VK2Superclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
};
static unsigned const VK4Superclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK8RegClassID,
};
static unsigned const VK8Superclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
};
static unsigned const VK16WMSuperclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK1WMRegClassID,
X86::VK2WMRegClassID,
X86::VK4WMRegClassID,
X86::VK8WMRegClassID,
};
static unsigned const VK1WMSuperclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK16WMRegClassID,
X86::VK2WMRegClassID,
X86::VK4WMRegClassID,
X86::VK8WMRegClassID,
};
static unsigned const VK2WMSuperclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK16WMRegClassID,
X86::VK1WMRegClassID,
X86::VK4WMRegClassID,
X86::VK8WMRegClassID,
};
static unsigned const VK4WMSuperclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK16WMRegClassID,
X86::VK1WMRegClassID,
X86::VK2WMRegClassID,
X86::VK8WMRegClassID,
};
static unsigned const VK8WMSuperclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK16WMRegClassID,
X86::VK1WMRegClassID,
X86::VK2WMRegClassID,
X86::VK4WMRegClassID,
};
static unsigned const GR16_ABCDSuperclasses[] = {
X86::GR16RegClassID,
X86::GR16_NOREX2RegClassID,
X86::GR16_NOREXRegClassID,
};
static unsigned const FR16Superclasses[] = {
X86::FR16XRegClassID,
};
static unsigned const VK16PAIRSuperclasses[] = {
X86::VK1PAIRRegClassID,
X86::VK2PAIRRegClassID,
X86::VK4PAIRRegClassID,
X86::VK8PAIRRegClassID,
};
static unsigned const VK1PAIRSuperclasses[] = {
X86::VK16PAIRRegClassID,
X86::VK2PAIRRegClassID,
X86::VK4PAIRRegClassID,
X86::VK8PAIRRegClassID,
};
static unsigned const VK2PAIRSuperclasses[] = {
X86::VK16PAIRRegClassID,
X86::VK1PAIRRegClassID,
X86::VK4PAIRRegClassID,
X86::VK8PAIRRegClassID,
};
static unsigned const VK4PAIRSuperclasses[] = {
X86::VK16PAIRRegClassID,
X86::VK1PAIRRegClassID,
X86::VK2PAIRRegClassID,
X86::VK8PAIRRegClassID,
};
static unsigned const VK8PAIRSuperclasses[] = {
X86::VK16PAIRRegClassID,
X86::VK1PAIRRegClassID,
X86::VK2PAIRRegClassID,
X86::VK4PAIRRegClassID,
};
static unsigned const VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses[] = {
X86::VK16PAIRRegClassID,
X86::VK1PAIRRegClassID,
X86::VK2PAIRRegClassID,
X86::VK4PAIRRegClassID,
X86::VK8PAIRRegClassID,
};
static unsigned const LOW32_ADDR_ACCESSSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
};
static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
};
static unsigned const FR32XSuperclasses[] = {
X86::FR16XRegClassID,
};
static unsigned const GR32Superclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
};
static unsigned const GR32_NOSPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
};
static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
};
static unsigned const FR32Superclasses[] = {
X86::FR16XRegClassID,
X86::FR16RegClassID,
X86::FR32XRegClassID,
};
static unsigned const GR32_NOREX2Superclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
};
static unsigned const GR32_NOREX2_NOSPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
};
static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
};
static unsigned const GR32_NOREXSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
};
static unsigned const VK32Superclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
};
static unsigned const GR32_NOREX_NOSPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
};
static unsigned const VK32WMSuperclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK16WMRegClassID,
X86::VK1WMRegClassID,
X86::VK2WMRegClassID,
X86::VK4WMRegClassID,
X86::VK8WMRegClassID,
X86::VK32RegClassID,
};
static unsigned const GR32_ABCDSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
};
static unsigned const GR32_TCSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
};
static unsigned const GR32_ABCD_and_GR32_TCSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
X86::GR32_TCRegClassID,
};
static unsigned const GR32_ADSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
X86::GR32_TCRegClassID,
X86::GR32_ABCD_and_GR32_TCRegClassID,
};
static unsigned const GR32_ArgRefSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
X86::GR32_TCRegClassID,
X86::GR32_ABCD_and_GR32_TCRegClassID,
};
static unsigned const GR32_BPSPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
};
static unsigned const GR32_BSISuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
};
static unsigned const GR32_CBSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
};
static unsigned const GR32_DCSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
X86::GR32_TCRegClassID,
X86::GR32_ABCD_and_GR32_TCRegClassID,
X86::GR32_ArgRefRegClassID,
};
static unsigned const GR32_DIBPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
};
static unsigned const GR32_SIDISuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
};
static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
};
static unsigned const GR32_ABCD_and_GR32_BSISuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
X86::GR32_BSIRegClassID,
X86::GR32_CBRegClassID,
};
static unsigned const GR32_AD_and_GR32_ArgRefSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
X86::GR32_TCRegClassID,
X86::GR32_ABCD_and_GR32_TCRegClassID,
X86::GR32_ADRegClassID,
X86::GR32_ArgRefRegClassID,
X86::GR32_DCRegClassID,
};
static unsigned const GR32_ArgRef_and_GR32_CBSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_ABCDRegClassID,
X86::GR32_TCRegClassID,
X86::GR32_ABCD_and_GR32_TCRegClassID,
X86::GR32_ArgRefRegClassID,
X86::GR32_CBRegClassID,
X86::GR32_DCRegClassID,
};
static unsigned const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_BPSPRegClassID,
X86::GR32_DIBPRegClassID,
};
static unsigned const GR32_BPSP_and_GR32_TCSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_TCRegClassID,
X86::GR32_BPSPRegClassID,
};
static unsigned const GR32_BSI_and_GR32_SIDISuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_BSIRegClassID,
X86::GR32_SIDIRegClassID,
};
static unsigned const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::GR32RegClassID,
X86::GR32_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR32_NOREX2RegClassID,
X86::GR32_NOREX2_NOSPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR32_NOREXRegClassID,
X86::GR32_NOREX_NOSPRegClassID,
X86::GR32_DIBPRegClassID,
X86::GR32_SIDIRegClassID,
};
static unsigned const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
};
static unsigned const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
};
static unsigned const RFP64Superclasses[] = {
X86::RFP32RegClassID,
};
static unsigned const FR64XSuperclasses[] = {
X86::FR16XRegClassID,
X86::FR32XRegClassID,
};
static unsigned const GR64_with_sub_8bitSuperclasses[] = {
X86::GR64RegClassID,
};
static unsigned const GR64_NOSPSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
};
static unsigned const GR64_NOREX2Superclasses[] = {
X86::GR64RegClassID,
};
static unsigned const FR64Superclasses[] = {
X86::FR16XRegClassID,
X86::FR16RegClassID,
X86::FR32XRegClassID,
X86::FR32RegClassID,
X86::FR64XRegClassID,
};
static unsigned const GR64_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
};
static unsigned const GR64_NOREX2_NOSPSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
};
static unsigned const GR64PLTSafeSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
};
static unsigned const GR64_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
};
static unsigned const GR64_NOREXSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
};
static unsigned const GR64_TCW64Superclasses[] = {
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
};
static unsigned const GR64_TC_with_sub_8bitSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_TCRegClassID,
};
static unsigned const GR64_NOREX2_NOSP_and_GR64_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
};
static unsigned const GR64_TCW64_with_sub_8bitSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_TCW64RegClassID,
};
static unsigned const GR64_TC_and_GR64_TCW64Superclasses[] = {
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_TCW64RegClassID,
};
static unsigned const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREXRegClassID,
};
static unsigned const VK64Superclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK32RegClassID,
};
static unsigned const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
};
static unsigned const GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
};
static unsigned const GR64_NOREX_NOSPSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
};
static unsigned const GR64_NOREX_and_GR64_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
};
static unsigned const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
};
static unsigned const VK64WMSuperclasses[] = {
X86::VK1RegClassID,
X86::VK16RegClassID,
X86::VK2RegClassID,
X86::VK4RegClassID,
X86::VK8RegClassID,
X86::VK16WMRegClassID,
X86::VK1WMRegClassID,
X86::VK2WMRegClassID,
X86::VK4WMRegClassID,
X86::VK8WMRegClassID,
X86::VK32RegClassID,
X86::VK32WMRegClassID,
X86::VK64RegClassID,
};
static unsigned const GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
};
static unsigned const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
};
static unsigned const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
};
static unsigned const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
};
static unsigned const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
};
static unsigned const GR64_ABCDSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
X86::GR64_ABCDRegClassID,
X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
};
static unsigned const GR64_ADSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
X86::GR64_ABCDRegClassID,
X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
};
static unsigned const GR64_ArgRefSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
};
static unsigned const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_NOREXRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
X86::GR64_ABCDRegClassID,
X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_ABCDRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
};
static unsigned const GR64_ArgRef_and_GR64_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_ArgRefRegClassID,
};
static unsigned const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESSRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID,
X86::GR64RegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_ABCDRegClassID,
X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
X86::GR64_ABCDRegClassID,
X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
X86::GR64_ADRegClassID,
X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCW64RegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
X86::GR64_ABCDRegClassID,
X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID,
X86::GR64_with_sub_32bit_in_GR32_CBRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
X86::LOW32_ADDR_ACCESS_RBPRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID,
X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID,
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID,
X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TCW64RegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TCW64_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64_TCW64RegClassID,
X86::GR64_with_sub_32bit_in_GR32_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID,
X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
};
static unsigned const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
X86::GR64RegClassID,
X86::GR64_with_sub_8bitRegClassID,
X86::GR64_NOSPRegClassID,
X86::GR64_NOREX2RegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID,
X86::GR64_NOREX2_NOSPRegClassID,
X86::GR64PLTSafeRegClassID,
X86::GR64_TCRegClassID,
X86::GR64_NOREXRegClassID,
X86::GR64_TC_with_sub_8bitRegClassID,
X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID,
X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_NOREX_NOSPRegClassID,
X86::GR64_NOREX_and_GR64_TCRegClassID,
X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID,
X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID,
X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID,
X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID,
};
static unsigned const RFP80Superclasses[] = {
X86::RFP32RegClassID,
X86::RFP64RegClassID,
};
static unsigned const VR128XSuperclasses[] = {
X86::FR16XRegClassID,
X86::FR32XRegClassID,
X86::FR64XRegClassID,
};
static unsigned const VR128Superclasses[] = {
X86::FR16XRegClassID,
X86::FR16RegClassID,
X86::FR32XRegClassID,
X86::FR32RegClassID,
X86::FR64XRegClassID,
X86::FR64RegClassID,
X86::VR128XRegClassID,
};
static unsigned const VR256Superclasses[] = {
X86::VR256XRegClassID,
};
static unsigned const VR512_0_15Superclasses[] = {
X86::VR512RegClassID,
};
static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<X86Subtarget>().is64Bit();
}
static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::R20B, X86::R21B, X86::R28B, X86::R29B };
const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = GR8AltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
static inline unsigned GR8_NOREX2AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<X86Subtarget>().is64Bit();
}
static ArrayRef<MCPhysReg> GR8_NOREX2GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREX2RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = GR8_NOREX2AltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<X86Subtarget>().is64Bit();
}
static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = GR8_NOREXAltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
namespace X86 { // Register class instances
extern const TargetRegisterClass GR8RegClass = {
&X86MCRegisterClasses[GR8RegClassID],
GR8SubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
GR8GetRawAllocationOrder
};
extern const TargetRegisterClass GRH8RegClass = {
&X86MCRegisterClasses[GRH8RegClassID],
GRH8SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass GR8_NOREX2RegClass = {
&X86MCRegisterClasses[GR8_NOREX2RegClassID],
GR8_NOREX2SubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR8_NOREX2Superclasses, 1,
GR8_NOREX2GetRawAllocationOrder
};
extern const TargetRegisterClass GR8_NOREXRegClass = {
&X86MCRegisterClasses[GR8_NOREXRegClassID],
GR8_NOREXSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR8_NOREXSuperclasses, 2,
GR8_NOREXGetRawAllocationOrder
};
extern const TargetRegisterClass GR8_ABCD_HRegClass = {
&X86MCRegisterClasses[GR8_ABCD_HRegClassID],
GR8_ABCD_HSubClassMask,
SuperRegIdxSeqs + 3,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR8_ABCD_HSuperclasses, 3,
nullptr
};
extern const TargetRegisterClass GR8_ABCD_LRegClass = {
&X86MCRegisterClasses[GR8_ABCD_LRegClassID],
GR8_ABCD_LSubClassMask,
SuperRegIdxSeqs + 0,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR8_ABCD_LSuperclasses, 3,
nullptr
};
extern const TargetRegisterClass GRH16RegClass = {
&X86MCRegisterClasses[GRH16RegClassID],
GRH16SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass GR16RegClass = {
&X86MCRegisterClasses[GR16RegClassID],
GR16SubClassMask,
SuperRegIdxSeqs + 5,
LaneBitmask(0x0000000000000003),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass GR16_NOREX2RegClass = {
&X86MCRegisterClasses[GR16_NOREX2RegClassID],
GR16_NOREX2SubClassMask,
SuperRegIdxSeqs + 5,
LaneBitmask(0x0000000000000003),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR16_NOREX2Superclasses, 1,
nullptr
};
extern const TargetRegisterClass GR16_NOREXRegClass = {
&X86MCRegisterClasses[GR16_NOREXRegClassID],
GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 5,
LaneBitmask(0x0000000000000003),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR16_NOREXSuperclasses, 2,
nullptr
};
extern const TargetRegisterClass VK1RegClass = {
&X86MCRegisterClasses[VK1RegClassID],
VK1SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK1Superclasses, 4,
nullptr
};
extern const TargetRegisterClass VK16RegClass = {
&X86MCRegisterClasses[VK16RegClassID],
VK16SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK16Superclasses, 4,
nullptr
};
extern const TargetRegisterClass VK2RegClass = {
&X86MCRegisterClasses[VK2RegClassID],
VK2SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK2Superclasses, 4,
nullptr
};
extern const TargetRegisterClass VK4RegClass = {
&X86MCRegisterClasses[VK4RegClassID],
VK4SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK4Superclasses, 4,
nullptr
};
extern const TargetRegisterClass VK8RegClass = {
&X86MCRegisterClasses[VK8RegClassID],
VK8SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK8Superclasses, 4,
nullptr
};
extern const TargetRegisterClass VK16WMRegClass = {
&X86MCRegisterClasses[VK16WMRegClassID],
VK16WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK16WMSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass VK1WMRegClass = {
&X86MCRegisterClasses[VK1WMRegClassID],
VK1WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK1WMSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass VK2WMRegClass = {
&X86MCRegisterClasses[VK2WMRegClassID],
VK2WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK2WMSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass VK4WMRegClass = {
&X86MCRegisterClasses[VK4WMRegClassID],
VK4WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK4WMSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass VK8WMRegClass = {
&X86MCRegisterClasses[VK8WMRegClassID],
VK8WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK8WMSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass SEGMENT_REGRegClass = {
&X86MCRegisterClasses[SEGMENT_REGRegClassID],
SEGMENT_REGSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass GR16_ABCDRegClass = {
&X86MCRegisterClasses[GR16_ABCDRegClassID],
GR16_ABCDSubClassMask,
SuperRegIdxSeqs + 5,
LaneBitmask(0x0000000000000003),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR16_ABCDSuperclasses, 3,
nullptr
};
extern const TargetRegisterClass FPCCRRegClass = {
&X86MCRegisterClasses[FPCCRRegClassID],
FPCCRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass FR16XRegClass = {
&X86MCRegisterClasses[FR16XRegClassID],
FR16XSubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass FR16RegClass = {
&X86MCRegisterClasses[FR16RegClassID],
FR16SubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR16Superclasses, 1,
nullptr
};
extern const TargetRegisterClass VK16PAIRRegClass = {
&X86MCRegisterClasses[VK16PAIRRegClassID],
VK16PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK16PAIRSuperclasses, 4,
nullptr
};
extern const TargetRegisterClass VK1PAIRRegClass = {
&X86MCRegisterClasses[VK1PAIRRegClassID],
VK1PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK1PAIRSuperclasses, 4,
nullptr
};
extern const TargetRegisterClass VK2PAIRRegClass = {
&X86MCRegisterClasses[VK2PAIRRegClassID],
VK2PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK2PAIRSuperclasses, 4,
nullptr
};
extern const TargetRegisterClass VK4PAIRRegClass = {
&X86MCRegisterClasses[VK4PAIRRegClassID],
VK4PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK4PAIRSuperclasses, 4,
nullptr
};
extern const TargetRegisterClass VK8PAIRRegClass = {
&X86MCRegisterClasses[VK8PAIRRegClassID],
VK8PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK8PAIRSuperclasses, 4,
nullptr
};
extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass = {
&X86MCRegisterClasses[VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID],
VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses, 5,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
LOW32_ADDR_ACCESS_RBPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
LOW32_ADDR_ACCESSSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESSSuperclasses, 1,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses, 1,
nullptr
};
extern const TargetRegisterClass FR32XRegClass = {
&X86MCRegisterClasses[FR32XRegClassID],
FR32XSubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR32XSuperclasses, 1,
nullptr
};
extern const TargetRegisterClass GR32RegClass = {
&X86MCRegisterClasses[GR32RegClassID],
GR32SubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32Superclasses, 3,
nullptr
};
extern const TargetRegisterClass GR32_NOSPRegClass = {
&X86MCRegisterClasses[GR32_NOSPRegClassID],
GR32_NOSPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOSPSuperclasses, 4,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses, 2,
nullptr
};
extern const TargetRegisterClass DEBUG_REGRegClass = {
&X86MCRegisterClasses[DEBUG_REGRegClassID],
DEBUG_REGSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass FR32RegClass = {
&X86MCRegisterClasses[FR32RegClassID],
FR32SubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR32Superclasses, 3,
nullptr
};
extern const TargetRegisterClass GR32_NOREX2RegClass = {
&X86MCRegisterClasses[GR32_NOREX2RegClassID],
GR32_NOREX2SubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOREX2Superclasses, 5,
nullptr
};
extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass = {
&X86MCRegisterClasses[GR32_NOREX2_NOSPRegClassID],
GR32_NOREX2_NOSPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOREX2_NOSPSuperclasses, 7,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses, 3,
nullptr
};
extern const TargetRegisterClass GR32_NOREXRegClass = {
&X86MCRegisterClasses[GR32_NOREXRegClassID],
GR32_NOREXSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOREXSuperclasses, 7,
nullptr
};
extern const TargetRegisterClass VK32RegClass = {
&X86MCRegisterClasses[VK32RegClassID],
VK32SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK32Superclasses, 5,
nullptr
};
extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
&X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
GR32_NOREX_NOSPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOREX_NOSPSuperclasses, 10,
nullptr
};
extern const TargetRegisterClass RFP32RegClass = {
&X86MCRegisterClasses[RFP32RegClassID],
RFP32SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass VK32WMRegClass = {
&X86MCRegisterClasses[VK32WMRegClassID],
VK32WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK32WMSuperclasses, 11,
nullptr
};
extern const TargetRegisterClass GR32_ABCDRegClass = {
&X86MCRegisterClasses[GR32_ABCDRegClassID],
GR32_ABCDSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ABCDSuperclasses, 11,
nullptr
};
extern const TargetRegisterClass GR32_TCRegClass = {
&X86MCRegisterClasses[GR32_TCRegClassID],
GR32_TCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_TCSuperclasses, 8,
nullptr
};
extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
GR32_ABCD_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ABCD_and_GR32_TCSuperclasses, 13,
nullptr
};
extern const TargetRegisterClass GR32_ADRegClass = {
&X86MCRegisterClasses[GR32_ADRegClassID],
GR32_ADSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ADSuperclasses, 14,
nullptr
};
extern const TargetRegisterClass GR32_ArgRefRegClass = {
&X86MCRegisterClasses[GR32_ArgRefRegClassID],
GR32_ArgRefSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ArgRefSuperclasses, 14,
nullptr
};
extern const TargetRegisterClass GR32_BPSPRegClass = {
&X86MCRegisterClasses[GR32_BPSPRegClassID],
GR32_BPSPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BPSPSuperclasses, 8,
nullptr
};
extern const TargetRegisterClass GR32_BSIRegClass = {
&X86MCRegisterClasses[GR32_BSIRegClassID],
GR32_BSISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BSISuperclasses, 11,
nullptr
};
extern const TargetRegisterClass GR32_CBRegClass = {
&X86MCRegisterClasses[GR32_CBRegClassID],
GR32_CBSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_CBSuperclasses, 12,
nullptr
};
extern const TargetRegisterClass GR32_DCRegClass = {
&X86MCRegisterClasses[GR32_DCRegClassID],
GR32_DCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_DCSuperclasses, 15,
nullptr
};
extern const TargetRegisterClass GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR32_DIBPRegClassID],
GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_DIBPSuperclasses, 11,
nullptr
};
extern const TargetRegisterClass GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR32_SIDIRegClassID],
GR32_SIDISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_SIDISuperclasses, 11,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses, 1,
nullptr
};
extern const TargetRegisterClass CCRRegClass = {
&X86MCRegisterClasses[CCRRegClassID],
CCRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass DFCCRRegClass = {
&X86MCRegisterClasses[DFCCRRegClassID],
DFCCRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
&X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
GR32_ABCD_and_GR32_BSISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ABCD_and_GR32_BSISuperclasses, 14,
nullptr
};
extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass = {
&X86MCRegisterClasses[GR32_AD_and_GR32_ArgRefRegClassID],
GR32_AD_and_GR32_ArgRefSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_AD_and_GR32_ArgRefSuperclasses, 17,
nullptr
};
extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass = {
&X86MCRegisterClasses[GR32_ArgRef_and_GR32_CBRegClassID],
GR32_ArgRef_and_GR32_CBSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ArgRef_and_GR32_CBSuperclasses, 17,
nullptr
};
extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
GR32_BPSP_and_GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BPSP_and_GR32_DIBPSuperclasses, 13,
nullptr
};
extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
GR32_BPSP_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BPSP_and_GR32_TCSuperclasses, 10,
nullptr
};
extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
GR32_BSI_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BSI_and_GR32_SIDISuperclasses, 13,
nullptr
};
extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
GR32_DIBP_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_DIBP_and_GR32_SIDISuperclasses, 13,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses, 5,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses, 3,
nullptr
};
extern const TargetRegisterClass RFP64RegClass = {
&X86MCRegisterClasses[RFP64RegClassID],
RFP64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
RFP64Superclasses, 1,
nullptr
};
extern const TargetRegisterClass GR64RegClass = {
&X86MCRegisterClasses[GR64RegClassID],
GR64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass FR64XRegClass = {
&X86MCRegisterClasses[FR64XRegClassID],
FR64XSubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR64XSuperclasses, 2,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
GR64_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_8bitSuperclasses, 1,
nullptr
};
extern const TargetRegisterClass GR64_NOSPRegClass = {
&X86MCRegisterClasses[GR64_NOSPRegClassID],
GR64_NOSPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOSPSuperclasses, 2,
nullptr
};
extern const TargetRegisterClass GR64_NOREX2RegClass = {
&X86MCRegisterClasses[GR64_NOREX2RegClassID],
GR64_NOREX2SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX2Superclasses, 1,
nullptr
};
extern const TargetRegisterClass CONTROL_REGRegClass = {
&X86MCRegisterClasses[CONTROL_REGRegClassID],
CONTROL_REGSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass FR64RegClass = {
&X86MCRegisterClasses[FR64RegClassID],
FR64SubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR64Superclasses, 5,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass = {
&X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREX2RegClassID],
GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_16bit_in_GR16_NOREX2Superclasses, 3,
nullptr
};
extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass = {
&X86MCRegisterClasses[GR64_NOREX2_NOSPRegClassID],
GR64_NOREX2_NOSPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX2_NOSPSuperclasses, 5,
nullptr
};
extern const TargetRegisterClass GR64PLTSafeRegClass = {
&X86MCRegisterClasses[GR64PLTSafeRegClassID],
GR64PLTSafeSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64PLTSafeSuperclasses, 6,
nullptr
};
extern const TargetRegisterClass GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_TCRegClassID],
GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCSuperclasses, 2,
nullptr
};
extern const TargetRegisterClass GR64_NOREXRegClass = {
&X86MCRegisterClasses[GR64_NOREXRegClassID],
GR64_NOREXSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREXSuperclasses, 2,
nullptr
};
extern const TargetRegisterClass GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_TCW64RegClassID],
GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCW64Superclasses, 2,
nullptr
};
extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
GR64_TC_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_with_sub_8bitSuperclasses, 5,
nullptr
};
extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCRegClassID],
GR64_NOREX2_NOSP_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX2_NOSP_and_GR64_TCSuperclasses, 8,
nullptr
};
extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
GR64_TCW64_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCW64_with_sub_8bitSuperclasses, 5,
nullptr
};
extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
GR64_TC_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_and_GR64_TCW64Superclasses, 4,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
&X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, 5,
nullptr
};
extern const TargetRegisterClass VK64RegClass = {
&X86MCRegisterClasses[VK64RegClassID],
VK64SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK64Superclasses, 6,
nullptr
};
extern const TargetRegisterClass VR64RegClass = {
&X86MCRegisterClasses[VR64RegClassID],
VR64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
GR64PLTSafe_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64PLTSafe_and_GR64_TCSuperclasses, 10,
nullptr
};
extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, 8,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
&X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
GR64_NOREX_NOSPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_NOSPSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
GR64_NOREX_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_and_GR64_TCSuperclasses, 4,
nullptr
};
extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass VK64WMRegClass = {
&X86MCRegisterClasses[VK64WMRegClassID],
VK64WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK64WMSuperclasses, 13,
nullptr
};
extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses, 14,
nullptr
};
extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
&X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
GR64PLTSafe_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64PLTSafe_and_GR64_TCW64Superclasses, 17,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses, 16,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
GR64_NOREX_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_and_GR64_TCW64Superclasses, 7,
nullptr
};
extern const TargetRegisterClass GR64_ABCDRegClass = {
&X86MCRegisterClasses[GR64_ABCDRegClassID],
GR64_ABCDSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_ABCDSuperclasses, 10,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
GR64_with_sub_32bit_in_GR32_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_TCSuperclasses, 15,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses, 27,
nullptr
};
extern const TargetRegisterClass GR64_ADRegClass = {
&X86MCRegisterClasses[GR64_ADRegClassID],
GR64_ADSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_ADSuperclasses, 28,
nullptr
};
extern const TargetRegisterClass GR64_ArgRefRegClass = {
&X86MCRegisterClasses[GR64_ArgRefRegClassID],
GR64_ArgRefSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_ArgRefSuperclasses, 9,
nullptr
};
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
&X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses, 5,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRefRegClassID],
GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses, 28,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BPSPSuperclasses, 6,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
GR64_with_sub_32bit_in_GR32_BSISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BSISuperclasses, 10,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
GR64_with_sub_32bit_in_GR32_CBSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_CBSuperclasses, 11,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_DIBPSuperclasses, 10,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_SIDISuperclasses, 17,
nullptr
};
extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_ArgRef_and_GR64_TCRegClassID],
GR64_ArgRef_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_ArgRef_and_GR64_TCSuperclasses, 16,
nullptr
};
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
&X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
GR64_and_LOW32_ADDR_ACCESSSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_and_LOW32_ADDR_ACCESSSuperclasses, 13,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses, 13,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID],
GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses, 30,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID],
GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses, 30,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses, 19,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses, 17,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses, 19,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses, 19,
nullptr
};
extern const TargetRegisterClass RSTRegClass = {
&X86MCRegisterClasses[RSTRegClassID],
RSTSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass RFP80RegClass = {
&X86MCRegisterClasses[RFP80RegClassID],
RFP80SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
RFP80Superclasses, 2,
nullptr
};
extern const TargetRegisterClass RFP80_7RegClass = {
&X86MCRegisterClasses[RFP80_7RegClassID],
RFP80_7SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass VR128XRegClass = {
&X86MCRegisterClasses[VR128XRegClassID],
VR128XSubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR128XSuperclasses, 3,
nullptr
};
extern const TargetRegisterClass VR128RegClass = {
&X86MCRegisterClasses[VR128RegClassID],
VR128SubClassMask,
SuperRegIdxSeqs + 15,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR128Superclasses, 7,
nullptr
};
extern const TargetRegisterClass VR256XRegClass = {
&X86MCRegisterClasses[VR256XRegClassID],
VR256XSubClassMask,
SuperRegIdxSeqs + 17,
LaneBitmask(0x0000000000000100),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass VR256RegClass = {
&X86MCRegisterClasses[VR256RegClassID],
VR256SubClassMask,
SuperRegIdxSeqs + 17,
LaneBitmask(0x0000000000000100),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR256Superclasses, 1,
nullptr
};
extern const TargetRegisterClass VR512RegClass = {
&X86MCRegisterClasses[VR512RegClassID],
VR512SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000100),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass VR512_0_15RegClass = {
&X86MCRegisterClasses[VR512_0_15RegClassID],
VR512_0_15SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000100),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR512_0_15Superclasses, 1,
nullptr
};
extern const TargetRegisterClass TILERegClass = {
&X86MCRegisterClasses[TILERegClassID],
TILESubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
extern const TargetRegisterClass TILEPAIRRegClass = {
&X86MCRegisterClasses[TILEPAIRRegClassID],
TILEPAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x00000000000000C0),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
nullptr, 0,
nullptr
};
} // end namespace X86
namespace {
const TargetRegisterClass *const RegisterClasses[] = {
&X86::GR8RegClass,
&X86::GRH8RegClass,
&X86::GR8_NOREX2RegClass,
&X86::GR8_NOREXRegClass,
&X86::GR8_ABCD_HRegClass,
&X86::GR8_ABCD_LRegClass,
&X86::GRH16RegClass,
&X86::GR16RegClass,
&X86::GR16_NOREX2RegClass,
&X86::GR16_NOREXRegClass,
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK1WMRegClass,
&X86::VK2WMRegClass,
&X86::VK4WMRegClass,
&X86::VK8WMRegClass,
&X86::SEGMENT_REGRegClass,
&X86::GR16_ABCDRegClass,
&X86::FPCCRRegClass,
&X86::FR16XRegClass,
&X86::FR16RegClass,
&X86::VK16PAIRRegClass,
&X86::VK1PAIRRegClass,
&X86::VK2PAIRRegClass,
&X86::VK4PAIRRegClass,
&X86::VK8PAIRRegClass,
&X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClass,
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::FR32XRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
&X86::DEBUG_REGRegClass,
&X86::FR32RegClass,
&X86::GR32_NOREX2RegClass,
&X86::GR32_NOREX2_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::VK32RegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::RFP32RegClass,
&X86::VK32WMRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_TCRegClass,
&X86::GR32_ABCD_and_GR32_TCRegClass,
&X86::GR32_ADRegClass,
&X86::GR32_ArgRefRegClass,
&X86::GR32_BPSPRegClass,
&X86::GR32_BSIRegClass,
&X86::GR32_CBRegClass,
&X86::GR32_DCRegClass,
&X86::GR32_DIBPRegClass,
&X86::GR32_SIDIRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
&X86::CCRRegClass,
&X86::DFCCRRegClass,
&X86::GR32_ABCD_and_GR32_BSIRegClass,
&X86::GR32_AD_and_GR32_ArgRefRegClass,
&X86::GR32_ArgRef_and_GR32_CBRegClass,
&X86::GR32_BPSP_and_GR32_DIBPRegClass,
&X86::GR32_BPSP_and_GR32_TCRegClass,
&X86::GR32_BSI_and_GR32_SIDIRegClass,
&X86::GR32_DIBP_and_GR32_SIDIRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
&X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
&X86::RFP64RegClass,
&X86::GR64RegClass,
&X86::FR64XRegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64_NOREX2RegClass,
&X86::CONTROL_REGRegClass,
&X86::FR64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
&X86::GR64_NOREX2_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::VK64RegClass,
&X86::VR64RegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::VK64WMRegClass,
&X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
&X86::GR64_ADRegClass,
&X86::GR64_ArgRefRegClass,
&X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
&X86::GR64_ArgRef_and_GR64_TCRegClass,
&X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
&X86::RSTRegClass,
&X86::RFP80RegClass,
&X86::RFP80_7RegClass,
&X86::VR128XRegClass,
&X86::VR128RegClass,
&X86::VR256XRegClass,
&X86::VR256RegClass,
&X86::VR512RegClass,
&X86::VR512_0_15RegClass,
&X86::TILERegClass,
&X86::TILEPAIRRegClass,
};
} // end anonymous namespace
static const uint8_t CostPerUseTable[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
static const bool InAllocatableClassTable[] = {
false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};
unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
static const uint8_t Rows[1][12] = {
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
};
--IdxA; assert(IdxA < 12); (void) IdxA;
--IdxB; assert(IdxB < 12);
return Rows[0][IdxB];
}
unsigned X86GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
static const uint8_t Table[12][12] = {
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, 0, 0, X86::sub_xmm, 0, },
};
--IdxA; assert(IdxA < 12);
--IdxB; assert(IdxB < 12);
return Table[IdxA][IdxB];
}
struct MaskRolOp {
LaneBitmask Mask;
uint8_t RotateLeft;
};
static const MaskRolOp LaneMaskComposeSequences[] = {
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 12
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 14
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 } // Sequence 16
};
static const uint8_t CompositeSequences[] = {
0, // to sub_8bit
2, // to sub_8bit_hi
4, // to sub_8bit_hi_phony
0, // to sub_16bit
6, // to sub_16bit_hi
0, // to sub_32bit
8, // to sub_mask_0
10, // to sub_mask_1
12, // to sub_t0
14, // to sub_t1
16, // to sub_xmm
0 // to sub_ymm
};
LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
--IdxA; assert(IdxA < 12 && "Subregister index out of bounds");
LaneBitmask Result;
for (const MaskRolOp *Ops =
&LaneMaskComposeSequences[CompositeSequences[IdxA]];
Ops->Mask.any(); ++Ops) {
LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
if (unsigned S = Ops->RotateLeft)
Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
else
Result |= LaneBitmask(M);
}
return Result;
}
LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
LaneMask &= getSubRegIndexLaneMask(IdxA);
--IdxA; assert(IdxA < 12 && "Subregister index out of bounds");
LaneBitmask Result;
for (const MaskRolOp *Ops =
&LaneMaskComposeSequences[CompositeSequences[IdxA]];
Ops->Mask.any(); ++Ops) {
LaneBitmask::Type M = LaneMask.getAsInteger();
if (unsigned S = Ops->RotateLeft)
Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
else
Result |= LaneBitmask(M);
}
return Result;
}
const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
static const uint8_t Table[135][12] = {
{ // GR8
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GRH8
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR8_NOREX2
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR8_NOREX
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR8_ABCD_H
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR8_ABCD_L
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GRH16
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR16
8, // sub_8bit -> GR16
22, // sub_8bit_hi -> GR16_ABCD
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR16_NOREX2
9, // sub_8bit -> GR16_NOREX2
22, // sub_8bit_hi -> GR16_ABCD
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR16_NOREX
10, // sub_8bit -> GR16_NOREX
22, // sub_8bit_hi -> GR16_ABCD
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK1
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK16
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK2
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK4
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK8
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK16WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK1WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK2WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK4WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK8WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // SEGMENT_REG
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR16_ABCD
22, // sub_8bit -> GR16_ABCD
22, // sub_8bit_hi -> GR16_ABCD
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // FPCCR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // FR16X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // FR16
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK16PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
26, // sub_mask_0 -> VK16PAIR
26, // sub_mask_1 -> VK16PAIR
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK1PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
27, // sub_mask_0 -> VK1PAIR
27, // sub_mask_1 -> VK1PAIR
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK2PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
28, // sub_mask_0 -> VK2PAIR
28, // sub_mask_1 -> VK2PAIR
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK4PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
29, // sub_mask_0 -> VK4PAIR
29, // sub_mask_1 -> VK4PAIR
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK8PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
30, // sub_mask_0 -> VK8PAIR
30, // sub_mask_1 -> VK8PAIR
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK1PAIR_with_sub_mask_0_in_VK1WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
31, // sub_mask_0 -> VK1PAIR_with_sub_mask_0_in_VK1WM
31, // sub_mask_1 -> VK1PAIR_with_sub_mask_0_in_VK1WM
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP
34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
32, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
32, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP
60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS
36, // sub_8bit -> GR32
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
33, // sub_16bit -> LOW32_ADDR_ACCESS
33, // sub_16bit_hi -> LOW32_ADDR_ACCESS
71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
34, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
34, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // FR32X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32
36, // sub_8bit -> GR32
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
36, // sub_16bit -> GR32
36, // sub_16bit_hi -> GR32
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOSP
37, // sub_8bit -> GR32_NOSP
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
37, // sub_16bit -> GR32_NOSP
37, // sub_16bit_hi -> GR32_NOSP
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
38, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // DEBUG_REG
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // FR32
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOREX2
41, // sub_8bit -> GR32_NOREX2
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
41, // sub_16bit -> GR32_NOREX2
41, // sub_16bit_hi -> GR32_NOREX2
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOREX2_NOSP
42, // sub_8bit -> GR32_NOREX2_NOSP
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
42, // sub_16bit -> GR32_NOREX2_NOSP
42, // sub_16bit_hi -> GR32_NOREX2_NOSP
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
43, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
43, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
43, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOREX
44, // sub_8bit -> GR32_NOREX
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
44, // sub_16bit -> GR32_NOREX
44, // sub_16bit_hi -> GR32_NOREX
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK32
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOREX_NOSP
46, // sub_8bit -> GR32_NOREX_NOSP
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
46, // sub_16bit -> GR32_NOREX_NOSP
46, // sub_16bit_hi -> GR32_NOREX_NOSP
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP32
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK32WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ABCD
49, // sub_8bit -> GR32_ABCD
49, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
49, // sub_16bit -> GR32_ABCD
49, // sub_16bit_hi -> GR32_ABCD
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_TC
50, // sub_8bit -> GR32_TC
51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
50, // sub_16bit -> GR32_TC
50, // sub_16bit_hi -> GR32_TC
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ABCD_and_GR32_TC
51, // sub_8bit -> GR32_ABCD_and_GR32_TC
51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
51, // sub_16bit -> GR32_ABCD_and_GR32_TC
51, // sub_16bit_hi -> GR32_ABCD_and_GR32_TC
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_AD
52, // sub_8bit -> GR32_AD
52, // sub_8bit_hi -> GR32_AD
0, // sub_8bit_hi_phony
52, // sub_16bit -> GR32_AD
52, // sub_16bit_hi -> GR32_AD
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ArgRef
53, // sub_8bit -> GR32_ArgRef
53, // sub_8bit_hi -> GR32_ArgRef
0, // sub_8bit_hi_phony
53, // sub_16bit -> GR32_ArgRef
53, // sub_16bit_hi -> GR32_ArgRef
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BPSP
54, // sub_8bit -> GR32_BPSP
0, // sub_8bit_hi
54, // sub_8bit_hi_phony -> GR32_BPSP
54, // sub_16bit -> GR32_BPSP
54, // sub_16bit_hi -> GR32_BPSP
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BSI
55, // sub_8bit -> GR32_BSI
63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
55, // sub_16bit -> GR32_BSI
55, // sub_16bit_hi -> GR32_BSI
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_CB
56, // sub_8bit -> GR32_CB
56, // sub_8bit_hi -> GR32_CB
0, // sub_8bit_hi_phony
56, // sub_16bit -> GR32_CB
56, // sub_16bit_hi -> GR32_CB
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_DC
57, // sub_8bit -> GR32_DC
57, // sub_8bit_hi -> GR32_DC
0, // sub_8bit_hi_phony
57, // sub_16bit -> GR32_DC
57, // sub_16bit_hi -> GR32_DC
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_DIBP
58, // sub_8bit -> GR32_DIBP
0, // sub_8bit_hi
58, // sub_8bit_hi_phony -> GR32_DIBP
58, // sub_16bit -> GR32_DIBP
58, // sub_16bit_hi -> GR32_DIBP
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_SIDI
59, // sub_8bit -> GR32_SIDI
0, // sub_8bit_hi
59, // sub_8bit_hi_phony -> GR32_SIDI
59, // sub_16bit -> GR32_SIDI
59, // sub_16bit_hi -> GR32_SIDI
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
60, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
60, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // CCR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // DFCCR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ABCD_and_GR32_BSI
63, // sub_8bit -> GR32_ABCD_and_GR32_BSI
63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
63, // sub_16bit -> GR32_ABCD_and_GR32_BSI
63, // sub_16bit_hi -> GR32_ABCD_and_GR32_BSI
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_AD_and_GR32_ArgRef
64, // sub_8bit -> GR32_AD_and_GR32_ArgRef
64, // sub_8bit_hi -> GR32_AD_and_GR32_ArgRef
0, // sub_8bit_hi_phony
64, // sub_16bit -> GR32_AD_and_GR32_ArgRef
64, // sub_16bit_hi -> GR32_AD_and_GR32_ArgRef
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ArgRef_and_GR32_CB
65, // sub_8bit -> GR32_ArgRef_and_GR32_CB
65, // sub_8bit_hi -> GR32_ArgRef_and_GR32_CB
0, // sub_8bit_hi_phony
65, // sub_16bit -> GR32_ArgRef_and_GR32_CB
65, // sub_16bit_hi -> GR32_ArgRef_and_GR32_CB
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BPSP_and_GR32_DIBP
66, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
0, // sub_8bit_hi
66, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_DIBP
66, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
66, // sub_16bit_hi -> GR32_BPSP_and_GR32_DIBP
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BPSP_and_GR32_TC
67, // sub_8bit -> GR32_BPSP_and_GR32_TC
0, // sub_8bit_hi
67, // sub_8bit_hi_phony -> GR32_BPSP_and_GR32_TC
67, // sub_16bit -> GR32_BPSP_and_GR32_TC
67, // sub_16bit_hi -> GR32_BPSP_and_GR32_TC
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BSI_and_GR32_SIDI
68, // sub_8bit -> GR32_BSI_and_GR32_SIDI
0, // sub_8bit_hi
68, // sub_8bit_hi_phony -> GR32_BSI_and_GR32_SIDI
68, // sub_16bit -> GR32_BSI_and_GR32_SIDI
68, // sub_16bit_hi -> GR32_BSI_and_GR32_SIDI
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_DIBP_and_GR32_SIDI
69, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
0, // sub_8bit_hi
69, // sub_8bit_hi_phony -> GR32_DIBP_and_GR32_SIDI
69, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
69, // sub_16bit_hi -> GR32_DIBP_and_GR32_SIDI
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_8bit_hi
70, // sub_8bit_hi_phony -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
70, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
70, // sub_16bit_hi -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_with_sub_32bit
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
71, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
71, // sub_16bit_hi -> LOW32_ADDR_ACCESS_with_sub_32bit
71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64
75, // sub_8bit -> GR64_with_sub_8bit
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
73, // sub_16bit -> GR64
73, // sub_16bit_hi -> GR64
73, // sub_32bit -> GR64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // FR64X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_8bit
75, // sub_8bit -> GR64_with_sub_8bit
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
75, // sub_16bit -> GR64_with_sub_8bit
75, // sub_16bit_hi -> GR64_with_sub_8bit
75, // sub_32bit -> GR64_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOSP
76, // sub_8bit -> GR64_NOSP
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
76, // sub_16bit -> GR64_NOSP
76, // sub_16bit_hi -> GR64_NOSP
76, // sub_32bit -> GR64_NOSP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX2
80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
77, // sub_16bit -> GR64_NOREX2
77, // sub_16bit_hi -> GR64_NOREX2
77, // sub_32bit -> GR64_NOREX2
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // CONTROL_REG
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // FR64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_16bit_in_GR16_NOREX2
80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
80, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX2
80, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX2
80, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX2
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX2_NOSP
81, // sub_8bit -> GR64_NOREX2_NOSP
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
81, // sub_16bit -> GR64_NOREX2_NOSP
81, // sub_16bit_hi -> GR64_NOREX2_NOSP
81, // sub_32bit -> GR64_NOREX2_NOSP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64PLTSafe
82, // sub_8bit -> GR64PLTSafe
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
82, // sub_16bit -> GR64PLTSafe
82, // sub_16bit_hi -> GR64PLTSafe
82, // sub_32bit -> GR64PLTSafe
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC
86, // sub_8bit -> GR64_TC_with_sub_8bit
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
83, // sub_16bit -> GR64_TC
83, // sub_16bit_hi -> GR64_TC
83, // sub_32bit -> GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX
90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
84, // sub_16bit -> GR64_NOREX
84, // sub_16bit_hi -> GR64_NOREX
84, // sub_32bit -> GR64_NOREX
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TCW64
88, // sub_8bit -> GR64_TCW64_with_sub_8bit
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
85, // sub_16bit -> GR64_TCW64
85, // sub_16bit_hi -> GR64_TCW64
85, // sub_32bit -> GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_with_sub_8bit
86, // sub_8bit -> GR64_TC_with_sub_8bit
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
86, // sub_16bit -> GR64_TC_with_sub_8bit
86, // sub_16bit_hi -> GR64_TC_with_sub_8bit
86, // sub_32bit -> GR64_TC_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX2_NOSP_and_GR64_TC
87, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TC
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
87, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TC
87, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TC
87, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TCW64_with_sub_8bit
88, // sub_8bit -> GR64_TCW64_with_sub_8bit
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
88, // sub_16bit -> GR64_TCW64_with_sub_8bit
88, // sub_16bit_hi -> GR64_TCW64_with_sub_8bit
88, // sub_32bit -> GR64_TCW64_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_and_GR64_TCW64
97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
89, // sub_16bit -> GR64_TC_and_GR64_TCW64
89, // sub_16bit_hi -> GR64_TC_and_GR64_TCW64
89, // sub_32bit -> GR64_TC_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_16bit_in_GR16_NOREX
90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
90, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
90, // sub_16bit_hi -> GR64_with_sub_16bit_in_GR16_NOREX
90, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VR64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64PLTSafe_and_GR64_TC
93, // sub_8bit -> GR64PLTSafe_and_GR64_TC
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
93, // sub_16bit -> GR64PLTSafe_and_GR64_TC
93, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TC
93, // sub_32bit -> GR64PLTSafe_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX2_NOSP_and_GR64_TCW64
94, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
94, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
94, // sub_16bit_hi -> GR64_NOREX2_NOSP_and_GR64_TCW64
94, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_NOSP
95, // sub_8bit -> GR64_NOREX_NOSP
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
95, // sub_16bit -> GR64_NOREX_NOSP
95, // sub_16bit_hi -> GR64_NOREX_NOSP
95, // sub_32bit -> GR64_NOREX_NOSP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_and_GR64_TC
100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
96, // sub_16bit -> GR64_NOREX_and_GR64_TC
96, // sub_16bit_hi -> GR64_NOREX_and_GR64_TC
96, // sub_32bit -> GR64_NOREX_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TCW64_and_GR64_TC_with_sub_8bit
97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
97, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
97, // sub_16bit_hi -> GR64_TCW64_and_GR64_TC_with_sub_8bit
97, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VK64WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
99, // sub_8bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
99, // sub_16bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
99, // sub_16bit_hi -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
99, // sub_32bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
100, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
100, // sub_16bit_hi -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
100, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64PLTSafe_and_GR64_TCW64
101, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
101, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
101, // sub_16bit_hi -> GR64PLTSafe_and_GR64_TCW64
101, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
102, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
102, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
102, // sub_16bit_hi -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
102, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_and_GR64_TCW64
105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
103, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
103, // sub_16bit_hi -> GR64_NOREX_and_GR64_TCW64
103, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_ABCD
104, // sub_8bit -> GR64_ABCD
104, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
104, // sub_16bit -> GR64_ABCD
104, // sub_16bit_hi -> GR64_ABCD
104, // sub_32bit -> GR64_ABCD
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_TC
105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
105, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_TC
105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
106, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_AD
107, // sub_8bit -> GR64_AD
107, // sub_8bit_hi -> GR64_AD
0, // sub_8bit_hi_phony
107, // sub_16bit -> GR64_AD
107, // sub_16bit_hi -> GR64_AD
107, // sub_32bit -> GR64_AD
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_ArgRef
108, // sub_8bit -> GR64_ArgRef
0, // sub_8bit_hi
108, // sub_8bit_hi_phony -> GR64_ArgRef
108, // sub_16bit -> GR64_ArgRef
108, // sub_16bit_hi -> GR64_ArgRef
108, // sub_32bit -> GR64_ArgRef
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS_RBP
121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
109, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
109, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS_RBP
109, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ArgRef
110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef
110, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
0, // sub_8bit_hi_phony
110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef
110, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP
111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
0, // sub_8bit_hi
111, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP
111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
111, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP
111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI
112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
118, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
112, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI
112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_CB
113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
113, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
0, // sub_8bit_hi_phony
113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
113, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_CB
113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP
114, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
0, // sub_8bit_hi
114, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP
114, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
114, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP
114, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_SIDI
115, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
0, // sub_8bit_hi
115, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_SIDI
115, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
115, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_SIDI
115, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_ArgRef_and_GR64_TC
116, // sub_8bit -> GR64_ArgRef_and_GR64_TC
0, // sub_8bit_hi
116, // sub_8bit_hi_phony -> GR64_ArgRef_and_GR64_TC
116, // sub_16bit -> GR64_ArgRef_and_GR64_TC
116, // sub_16bit_hi -> GR64_ArgRef_and_GR64_TC
116, // sub_32bit -> GR64_ArgRef_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
117, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
117, // sub_16bit_hi -> GR64_and_LOW32_ADDR_ACCESS
117, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
118, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
118, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
118, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
118, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
118, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
119, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
0, // sub_8bit_hi_phony
119, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
119, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
119, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
120, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
120, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
0, // sub_8bit_hi_phony
120, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
120, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
120, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
0, // sub_8bit_hi
121, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
121, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
121, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
121, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
0, // sub_8bit_hi
122, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
122, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
122, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
122, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
123, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
0, // sub_8bit_hi
123, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
123, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
123, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
123, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
124, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
0, // sub_8bit_hi
124, // sub_8bit_hi_phony -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
124, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
124, // sub_16bit_hi -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
124, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // RST
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP80
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP80_7
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VR128X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VR128
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // VR256X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
130, // sub_xmm -> VR256X
0, // sub_ymm
},
{ // VR256
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
131, // sub_xmm -> VR256
0, // sub_ymm
},
{ // VR512
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
132, // sub_xmm -> VR512
132, // sub_ymm -> VR512
},
{ // VR512_0_15
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
133, // sub_xmm -> VR512_0_15
133, // sub_ymm -> VR512_0_15
},
{ // TILE
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_t0
0, // sub_t1
0, // sub_xmm
0, // sub_ymm
},
{ // TILEPAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
135, // sub_t0 -> TILEPAIR
135, // sub_t1 -> TILEPAIR
0, // sub_xmm
0, // sub_ymm
},
};
assert(RC && "Missing regclass");
if (!Idx) return RC;
--Idx;
assert(Idx < 12 && "Bad subreg");
unsigned TV = Table[RC->getID()][Idx];
return TV ? getRegClass(TV - 1) : nullptr;
}
const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
static const uint8_t Table[135][12] = {
{ // GR8
0, // GR8:sub_8bit
0, // GR8:sub_8bit_hi
0, // GR8:sub_8bit_hi_phony
0, // GR8:sub_16bit
0, // GR8:sub_16bit_hi
0, // GR8:sub_32bit
0, // GR8:sub_mask_0
0, // GR8:sub_mask_1
0, // GR8:sub_t0
0, // GR8:sub_t1
0, // GR8:sub_xmm
0, // GR8:sub_ymm
},
{ // GRH8
0, // GRH8:sub_8bit
0, // GRH8:sub_8bit_hi
0, // GRH8:sub_8bit_hi_phony
0, // GRH8:sub_16bit
0, // GRH8:sub_16bit_hi
0, // GRH8:sub_32bit
0, // GRH8:sub_mask_0
0, // GRH8:sub_mask_1
0, // GRH8:sub_t0
0, // GRH8:sub_t1
0, // GRH8:sub_xmm
0, // GRH8:sub_ymm
},
{ // GR8_NOREX2
0, // GR8_NOREX2:sub_8bit
0, // GR8_NOREX2:sub_8bit_hi
0, // GR8_NOREX2:sub_8bit_hi_phony
0, // GR8_NOREX2:sub_16bit
0, // GR8_NOREX2:sub_16bit_hi
0, // GR8_NOREX2:sub_32bit
0, // GR8_NOREX2:sub_mask_0
0, // GR8_NOREX2:sub_mask_1
0, // GR8_NOREX2:sub_t0
0, // GR8_NOREX2:sub_t1
0, // GR8_NOREX2:sub_xmm
0, // GR8_NOREX2:sub_ymm
},
{ // GR8_NOREX
0, // GR8_NOREX:sub_8bit
0, // GR8_NOREX:sub_8bit_hi
0, // GR8_NOREX:sub_8bit_hi_phony
0, // GR8_NOREX:sub_16bit
0, // GR8_NOREX:sub_16bit_hi
0, // GR8_NOREX:sub_32bit
0, // GR8_NOREX:sub_mask_0
0, // GR8_NOREX:sub_mask_1
0, // GR8_NOREX:sub_t0
0, // GR8_NOREX:sub_t1
0, // GR8_NOREX:sub_xmm
0, // GR8_NOREX:sub_ymm
},
{ // GR8_ABCD_H
0, // GR8_ABCD_H:sub_8bit
0, // GR8_ABCD_H:sub_8bit_hi
0, // GR8_ABCD_H:sub_8bit_hi_phony
0, // GR8_ABCD_H:sub_16bit
0, // GR8_ABCD_H:sub_16bit_hi
0, // GR8_ABCD_H:sub_32bit
0, // GR8_ABCD_H:sub_mask_0
0, // GR8_ABCD_H:sub_mask_1
0, // GR8_ABCD_H:sub_t0
0, // GR8_ABCD_H:sub_t1
0, // GR8_ABCD_H:sub_xmm
0, // GR8_ABCD_H:sub_ymm
},
{ // GR8_ABCD_L
0, // GR8_ABCD_L:sub_8bit
0, // GR8_ABCD_L:sub_8bit_hi
0, // GR8_ABCD_L:sub_8bit_hi_phony
0, // GR8_ABCD_L:sub_16bit
0, // GR8_ABCD_L:sub_16bit_hi
0, // GR8_ABCD_L:sub_32bit
0, // GR8_ABCD_L:sub_mask_0
0, // GR8_ABCD_L:sub_mask_1
0, // GR8_ABCD_L:sub_t0
0, // GR8_ABCD_L:sub_t1
0, // GR8_ABCD_L:sub_xmm
0, // GR8_ABCD_L:sub_ymm
},
{ // GRH16
0, // GRH16:sub_8bit
0, // GRH16:sub_8bit_hi
0, // GRH16:sub_8bit_hi_phony
0, // GRH16:sub_16bit
0, // GRH16:sub_16bit_hi
0, // GRH16:sub_32bit
0, // GRH16:sub_mask_0
0, // GRH16:sub_mask_1
0, // GRH16:sub_t0
0, // GRH16:sub_t1
0, // GRH16:sub_xmm
0, // GRH16:sub_ymm
},
{ // GR16
1, // GR16:sub_8bit -> GR8
5, // GR16:sub_8bit_hi -> GR8_ABCD_H
0, // GR16:sub_8bit_hi_phony
0, // GR16:sub_16bit
0, // GR16:sub_16bit_hi
0, // GR16:sub_32bit
0, // GR16:sub_mask_0
0, // GR16:sub_mask_1
0, // GR16:sub_t0
0, // GR16:sub_t1
0, // GR16:sub_xmm
0, // GR16:sub_ymm
},
{ // GR16_NOREX2
3, // GR16_NOREX2:sub_8bit -> GR8_NOREX2
5, // GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
0, // GR16_NOREX2:sub_8bit_hi_phony
0, // GR16_NOREX2:sub_16bit
0, // GR16_NOREX2:sub_16bit_hi
0, // GR16_NOREX2:sub_32bit
0, // GR16_NOREX2:sub_mask_0
0, // GR16_NOREX2:sub_mask_1
0, // GR16_NOREX2:sub_t0
0, // GR16_NOREX2:sub_t1
0, // GR16_NOREX2:sub_xmm
0, // GR16_NOREX2:sub_ymm
},
{ // GR16_NOREX
3, // GR16_NOREX:sub_8bit -> GR8_NOREX2
5, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR16_NOREX:sub_8bit_hi_phony
0, // GR16_NOREX:sub_16bit
0, // GR16_NOREX:sub_16bit_hi
0, // GR16_NOREX:sub_32bit
0, // GR16_NOREX:sub_mask_0
0, // GR16_NOREX:sub_mask_1
0, // GR16_NOREX:sub_t0
0, // GR16_NOREX:sub_t1
0, // GR16_NOREX:sub_xmm
0, // GR16_NOREX:sub_ymm
},
{ // VK1
0, // VK1:sub_8bit
0, // VK1:sub_8bit_hi
0, // VK1:sub_8bit_hi_phony
0, // VK1:sub_16bit
0, // VK1:sub_16bit_hi
0, // VK1:sub_32bit
0, // VK1:sub_mask_0
0, // VK1:sub_mask_1
0, // VK1:sub_t0
0, // VK1:sub_t1
0, // VK1:sub_xmm
0, // VK1:sub_ymm
},
{ // VK16
0, // VK16:sub_8bit
0, // VK16:sub_8bit_hi
0, // VK16:sub_8bit_hi_phony
0, // VK16:sub_16bit
0, // VK16:sub_16bit_hi
0, // VK16:sub_32bit
0, // VK16:sub_mask_0
0, // VK16:sub_mask_1
0, // VK16:sub_t0
0, // VK16:sub_t1
0, // VK16:sub_xmm
0, // VK16:sub_ymm
},
{ // VK2
0, // VK2:sub_8bit
0, // VK2:sub_8bit_hi
0, // VK2:sub_8bit_hi_phony
0, // VK2:sub_16bit
0, // VK2:sub_16bit_hi
0, // VK2:sub_32bit
0, // VK2:sub_mask_0
0, // VK2:sub_mask_1
0, // VK2:sub_t0
0, // VK2:sub_t1
0, // VK2:sub_xmm
0, // VK2:sub_ymm
},
{ // VK4
0, // VK4:sub_8bit
0, // VK4:sub_8bit_hi
0, // VK4:sub_8bit_hi_phony
0, // VK4:sub_16bit
0, // VK4:sub_16bit_hi
0, // VK4:sub_32bit
0, // VK4:sub_mask_0
0, // VK4:sub_mask_1
0, // VK4:sub_t0
0, // VK4:sub_t1
0, // VK4:sub_xmm
0, // VK4:sub_ymm
},
{ // VK8
0, // VK8:sub_8bit
0, // VK8:sub_8bit_hi
0, // VK8:sub_8bit_hi_phony
0, // VK8:sub_16bit
0, // VK8:sub_16bit_hi
0, // VK8:sub_32bit
0, // VK8:sub_mask_0
0, // VK8:sub_mask_1
0, // VK8:sub_t0
0, // VK8:sub_t1
0, // VK8:sub_xmm
0, // VK8:sub_ymm
},
{ // VK16WM
0, // VK16WM:sub_8bit
0, // VK16WM:sub_8bit_hi
0, // VK16WM:sub_8bit_hi_phony
0, // VK16WM:sub_16bit
0, // VK16WM:sub_16bit_hi
0, // VK16WM:sub_32bit
0, // VK16WM:sub_mask_0
0, // VK16WM:sub_mask_1
0, // VK16WM:sub_t0
0, // VK16WM:sub_t1
0, // VK16WM:sub_xmm
0, // VK16WM:sub_ymm
},
{ // VK1WM
0, // VK1WM:sub_8bit
0, // VK1WM:sub_8bit_hi
0, // VK1WM:sub_8bit_hi_phony
0, // VK1WM:sub_16bit
0, // VK1WM:sub_16bit_hi
0, // VK1WM:sub_32bit
0, // VK1WM:sub_mask_0
0, // VK1WM:sub_mask_1
0, // VK1WM:sub_t0
0, // VK1WM:sub_t1
0, // VK1WM:sub_xmm
0, // VK1WM:sub_ymm
},
{ // VK2WM
0, // VK2WM:sub_8bit
0, // VK2WM:sub_8bit_hi
0, // VK2WM:sub_8bit_hi_phony
0, // VK2WM:sub_16bit
0, // VK2WM:sub_16bit_hi
0, // VK2WM:sub_32bit
0, // VK2WM:sub_mask_0
0, // VK2WM:sub_mask_1
0, // VK2WM:sub_t0
0, // VK2WM:sub_t1
0, // VK2WM:sub_xmm
0, // VK2WM:sub_ymm
},
{ // VK4WM
0, // VK4WM:sub_8bit
0, // VK4WM:sub_8bit_hi
0, // VK4WM:sub_8bit_hi_phony
0, // VK4WM:sub_16bit
0, // VK4WM:sub_16bit_hi
0, // VK4WM:sub_32bit
0, // VK4WM:sub_mask_0
0, // VK4WM:sub_mask_1
0, // VK4WM:sub_t0
0, // VK4WM:sub_t1
0, // VK4WM:sub_xmm
0, // VK4WM:sub_ymm
},
{ // VK8WM
0, // VK8WM:sub_8bit
0, // VK8WM:sub_8bit_hi
0, // VK8WM:sub_8bit_hi_phony
0, // VK8WM:sub_16bit
0, // VK8WM:sub_16bit_hi
0, // VK8WM:sub_32bit
0, // VK8WM:sub_mask_0
0, // VK8WM:sub_mask_1
0, // VK8WM:sub_t0
0, // VK8WM:sub_t1
0, // VK8WM:sub_xmm
0, // VK8WM:sub_ymm
},
{ // SEGMENT_REG
0, // SEGMENT_REG:sub_8bit
0, // SEGMENT_REG:sub_8bit_hi
0, // SEGMENT_REG:sub_8bit_hi_phony
0, // SEGMENT_REG:sub_16bit
0, // SEGMENT_REG:sub_16bit_hi
0, // SEGMENT_REG:sub_32bit
0, // SEGMENT_REG:sub_mask_0
0, // SEGMENT_REG:sub_mask_1
0, // SEGMENT_REG:sub_t0
0, // SEGMENT_REG:sub_t1
0, // SEGMENT_REG:sub_xmm
0, // SEGMENT_REG:sub_ymm
},
{ // GR16_ABCD
6, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
5, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
0, // GR16_ABCD:sub_8bit_hi_phony
0, // GR16_ABCD:sub_16bit
0, // GR16_ABCD:sub_16bit_hi
0, // GR16_ABCD:sub_32bit
0, // GR16_ABCD:sub_mask_0
0, // GR16_ABCD:sub_mask_1
0, // GR16_ABCD:sub_t0
0, // GR16_ABCD:sub_t1
0, // GR16_ABCD:sub_xmm
0, // GR16_ABCD:sub_ymm
},
{ // FPCCR
0, // FPCCR:sub_8bit
0, // FPCCR:sub_8bit_hi
0, // FPCCR:sub_8bit_hi_phony
0, // FPCCR:sub_16bit
0, // FPCCR:sub_16bit_hi
0, // FPCCR:sub_32bit
0, // FPCCR:sub_mask_0
0, // FPCCR:sub_mask_1
0, // FPCCR:sub_t0
0, // FPCCR:sub_t1
0, // FPCCR:sub_xmm
0, // FPCCR:sub_ymm
},
{ // FR16X
0, // FR16X:sub_8bit
0, // FR16X:sub_8bit_hi
0, // FR16X:sub_8bit_hi_phony
0, // FR16X:sub_16bit
0, // FR16X:sub_16bit_hi
0, // FR16X:sub_32bit
0, // FR16X:sub_mask_0
0, // FR16X:sub_mask_1
0, // FR16X:sub_t0
0, // FR16X:sub_t1
0, // FR16X:sub_xmm
0, // FR16X:sub_ymm
},
{ // FR16
0, // FR16:sub_8bit
0, // FR16:sub_8bit_hi
0, // FR16:sub_8bit_hi_phony
0, // FR16:sub_16bit
0, // FR16:sub_16bit_hi
0, // FR16:sub_32bit
0, // FR16:sub_mask_0
0, // FR16:sub_mask_1
0, // FR16:sub_t0
0, // FR16:sub_t1
0, // FR16:sub_xmm
0, // FR16:sub_ymm
},
{ // VK16PAIR
0, // VK16PAIR:sub_8bit
0, // VK16PAIR:sub_8bit_hi
0, // VK16PAIR:sub_8bit_hi_phony
0, // VK16PAIR:sub_16bit
0, // VK16PAIR:sub_16bit_hi
0, // VK16PAIR:sub_32bit
91, // VK16PAIR:sub_mask_0 -> VK64
98, // VK16PAIR:sub_mask_1 -> VK64WM
0, // VK16PAIR:sub_t0
0, // VK16PAIR:sub_t1
0, // VK16PAIR:sub_xmm
0, // VK16PAIR:sub_ymm
},
{ // VK1PAIR
0, // VK1PAIR:sub_8bit
0, // VK1PAIR:sub_8bit_hi
0, // VK1PAIR:sub_8bit_hi_phony
0, // VK1PAIR:sub_16bit
0, // VK1PAIR:sub_16bit_hi
0, // VK1PAIR:sub_32bit
91, // VK1PAIR:sub_mask_0 -> VK64
98, // VK1PAIR:sub_mask_1 -> VK64WM
0, // VK1PAIR:sub_t0
0, // VK1PAIR:sub_t1
0, // VK1PAIR:sub_xmm
0, // VK1PAIR:sub_ymm
},
{ // VK2PAIR
0, // VK2PAIR:sub_8bit
0, // VK2PAIR:sub_8bit_hi
0, // VK2PAIR:sub_8bit_hi_phony
0, // VK2PAIR:sub_16bit
0, // VK2PAIR:sub_16bit_hi
0, // VK2PAIR:sub_32bit
91, // VK2PAIR:sub_mask_0 -> VK64
98, // VK2PAIR:sub_mask_1 -> VK64WM
0, // VK2PAIR:sub_t0
0, // VK2PAIR:sub_t1
0, // VK2PAIR:sub_xmm
0, // VK2PAIR:sub_ymm
},
{ // VK4PAIR
0, // VK4PAIR:sub_8bit
0, // VK4PAIR:sub_8bit_hi
0, // VK4PAIR:sub_8bit_hi_phony
0, // VK4PAIR:sub_16bit
0, // VK4PAIR:sub_16bit_hi
0, // VK4PAIR:sub_32bit
91, // VK4PAIR:sub_mask_0 -> VK64
98, // VK4PAIR:sub_mask_1 -> VK64WM
0, // VK4PAIR:sub_t0
0, // VK4PAIR:sub_t1
0, // VK4PAIR:sub_xmm
0, // VK4PAIR:sub_ymm
},
{ // VK8PAIR
0, // VK8PAIR:sub_8bit
0, // VK8PAIR:sub_8bit_hi
0, // VK8PAIR:sub_8bit_hi_phony
0, // VK8PAIR:sub_16bit
0, // VK8PAIR:sub_16bit_hi
0, // VK8PAIR:sub_32bit
91, // VK8PAIR:sub_mask_0 -> VK64
98, // VK8PAIR:sub_mask_1 -> VK64WM
0, // VK8PAIR:sub_t0
0, // VK8PAIR:sub_t1
0, // VK8PAIR:sub_xmm
0, // VK8PAIR:sub_ymm
},
{ // VK1PAIR_with_sub_mask_0_in_VK1WM
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi_phony
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit_hi
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_32bit
98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_0 -> VK64WM
98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_1 -> VK64WM
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_t0
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_t1
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_xmm
0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP
1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
5, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
8, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
66, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP:sub_t0
0, // LOW32_ADDR_ACCESS_RBP:sub_t1
0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
},
{ // LOW32_ADDR_ACCESS
1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
5, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
8, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
0, // LOW32_ADDR_ACCESS:sub_16bit_hi
0, // LOW32_ADDR_ACCESS:sub_32bit
0, // LOW32_ADDR_ACCESS:sub_mask_0
0, // LOW32_ADDR_ACCESS:sub_mask_1
0, // LOW32_ADDR_ACCESS:sub_t0
0, // LOW32_ADDR_ACCESS:sub_t1
0, // LOW32_ADDR_ACCESS:sub_xmm
0, // LOW32_ADDR_ACCESS:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
5, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_t0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_t1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
},
{ // FR32X
0, // FR32X:sub_8bit
0, // FR32X:sub_8bit_hi
0, // FR32X:sub_8bit_hi_phony
0, // FR32X:sub_16bit
0, // FR32X:sub_16bit_hi
0, // FR32X:sub_32bit
0, // FR32X:sub_mask_0
0, // FR32X:sub_mask_1
0, // FR32X:sub_t0
0, // FR32X:sub_t1
0, // FR32X:sub_xmm
0, // FR32X:sub_ymm
},
{ // GR32
1, // GR32:sub_8bit -> GR8
5, // GR32:sub_8bit_hi -> GR8_ABCD_H
0, // GR32:sub_8bit_hi_phony
8, // GR32:sub_16bit -> GR16
0, // GR32:sub_16bit_hi
0, // GR32:sub_32bit
0, // GR32:sub_mask_0
0, // GR32:sub_mask_1
0, // GR32:sub_t0
0, // GR32:sub_t1
0, // GR32:sub_xmm
0, // GR32:sub_ymm
},
{ // GR32_NOSP
1, // GR32_NOSP:sub_8bit -> GR8
5, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOSP:sub_8bit_hi_phony
8, // GR32_NOSP:sub_16bit -> GR16
0, // GR32_NOSP:sub_16bit_hi
0, // GR32_NOSP:sub_32bit
0, // GR32_NOSP:sub_mask_0
0, // GR32_NOSP:sub_mask_1
0, // GR32_NOSP:sub_t0
0, // GR32_NOSP:sub_t1
0, // GR32_NOSP:sub_xmm
0, // GR32_NOSP:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
9, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_t0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_t1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_ymm
},
{ // DEBUG_REG
0, // DEBUG_REG:sub_8bit
0, // DEBUG_REG:sub_8bit_hi
0, // DEBUG_REG:sub_8bit_hi_phony
0, // DEBUG_REG:sub_16bit
0, // DEBUG_REG:sub_16bit_hi
0, // DEBUG_REG:sub_32bit
0, // DEBUG_REG:sub_mask_0
0, // DEBUG_REG:sub_mask_1
0, // DEBUG_REG:sub_t0
0, // DEBUG_REG:sub_t1
0, // DEBUG_REG:sub_xmm
0, // DEBUG_REG:sub_ymm
},
{ // FR32
0, // FR32:sub_8bit
0, // FR32:sub_8bit_hi
0, // FR32:sub_8bit_hi_phony
0, // FR32:sub_16bit
0, // FR32:sub_16bit_hi
0, // FR32:sub_32bit
0, // FR32:sub_mask_0
0, // FR32:sub_mask_1
0, // FR32:sub_t0
0, // FR32:sub_t1
0, // FR32:sub_xmm
0, // FR32:sub_ymm
},
{ // GR32_NOREX2
3, // GR32_NOREX2:sub_8bit -> GR8_NOREX2
5, // GR32_NOREX2:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOREX2:sub_8bit_hi_phony
9, // GR32_NOREX2:sub_16bit -> GR16_NOREX2
0, // GR32_NOREX2:sub_16bit_hi
0, // GR32_NOREX2:sub_32bit
0, // GR32_NOREX2:sub_mask_0
0, // GR32_NOREX2:sub_mask_1
0, // GR32_NOREX2:sub_t0
0, // GR32_NOREX2:sub_t1
0, // GR32_NOREX2:sub_xmm
0, // GR32_NOREX2:sub_ymm
},
{ // GR32_NOREX2_NOSP
3, // GR32_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
5, // GR32_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOREX2_NOSP:sub_8bit_hi_phony
9, // GR32_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
0, // GR32_NOREX2_NOSP:sub_16bit_hi
0, // GR32_NOREX2_NOSP:sub_32bit
0, // GR32_NOREX2_NOSP:sub_mask_0
0, // GR32_NOREX2_NOSP:sub_mask_1
0, // GR32_NOREX2_NOSP:sub_t0
0, // GR32_NOREX2_NOSP:sub_t1
0, // GR32_NOREX2_NOSP:sub_xmm
0, // GR32_NOREX2_NOSP:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
10, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_t0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_t1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
},
{ // GR32_NOREX
3, // GR32_NOREX:sub_8bit -> GR8_NOREX2
5, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOREX:sub_8bit_hi_phony
10, // GR32_NOREX:sub_16bit -> GR16_NOREX
0, // GR32_NOREX:sub_16bit_hi
0, // GR32_NOREX:sub_32bit
0, // GR32_NOREX:sub_mask_0
0, // GR32_NOREX:sub_mask_1
0, // GR32_NOREX:sub_t0
0, // GR32_NOREX:sub_t1
0, // GR32_NOREX:sub_xmm
0, // GR32_NOREX:sub_ymm
},
{ // VK32
0, // VK32:sub_8bit
0, // VK32:sub_8bit_hi
0, // VK32:sub_8bit_hi_phony
0, // VK32:sub_16bit
0, // VK32:sub_16bit_hi
0, // VK32:sub_32bit
0, // VK32:sub_mask_0
0, // VK32:sub_mask_1
0, // VK32:sub_t0
0, // VK32:sub_t1
0, // VK32:sub_xmm
0, // VK32:sub_ymm
},
{ // GR32_NOREX_NOSP
3, // GR32_NOREX_NOSP:sub_8bit -> GR8_NOREX2
5, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
10, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
0, // GR32_NOREX_NOSP:sub_16bit_hi
0, // GR32_NOREX_NOSP:sub_32bit
0, // GR32_NOREX_NOSP:sub_mask_0
0, // GR32_NOREX_NOSP:sub_mask_1
0, // GR32_NOREX_NOSP:sub_t0
0, // GR32_NOREX_NOSP:sub_t1
0, // GR32_NOREX_NOSP:sub_xmm
0, // GR32_NOREX_NOSP:sub_ymm
},
{ // RFP32
0, // RFP32:sub_8bit
0, // RFP32:sub_8bit_hi
0, // RFP32:sub_8bit_hi_phony
0, // RFP32:sub_16bit
0, // RFP32:sub_16bit_hi
0, // RFP32:sub_32bit
0, // RFP32:sub_mask_0
0, // RFP32:sub_mask_1
0, // RFP32:sub_t0
0, // RFP32:sub_t1
0, // RFP32:sub_xmm
0, // RFP32:sub_ymm
},
{ // VK32WM
0, // VK32WM:sub_8bit
0, // VK32WM:sub_8bit_hi
0, // VK32WM:sub_8bit_hi_phony
0, // VK32WM:sub_16bit
0, // VK32WM:sub_16bit_hi
0, // VK32WM:sub_32bit
0, // VK32WM:sub_mask_0
0, // VK32WM:sub_mask_1
0, // VK32WM:sub_t0
0, // VK32WM:sub_t1
0, // VK32WM:sub_xmm
0, // VK32WM:sub_ymm
},
{ // GR32_ABCD
6, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
5, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ABCD:sub_8bit_hi_phony
22, // GR32_ABCD:sub_16bit -> GR16_ABCD
0, // GR32_ABCD:sub_16bit_hi
0, // GR32_ABCD:sub_32bit
0, // GR32_ABCD:sub_mask_0
0, // GR32_ABCD:sub_mask_1
0, // GR32_ABCD:sub_t0
0, // GR32_ABCD:sub_t1
0, // GR32_ABCD:sub_xmm
0, // GR32_ABCD:sub_ymm
},
{ // GR32_TC
3, // GR32_TC:sub_8bit -> GR8_NOREX2
5, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_TC:sub_8bit_hi_phony
10, // GR32_TC:sub_16bit -> GR16_NOREX
0, // GR32_TC:sub_16bit_hi
0, // GR32_TC:sub_32bit
0, // GR32_TC:sub_mask_0
0, // GR32_TC:sub_mask_1
0, // GR32_TC:sub_t0
0, // GR32_TC:sub_t1
0, // GR32_TC:sub_xmm
0, // GR32_TC:sub_ymm
},
{ // GR32_ABCD_and_GR32_TC
6, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
5, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
22, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
0, // GR32_ABCD_and_GR32_TC:sub_32bit
0, // GR32_ABCD_and_GR32_TC:sub_mask_0
0, // GR32_ABCD_and_GR32_TC:sub_mask_1
0, // GR32_ABCD_and_GR32_TC:sub_t0
0, // GR32_ABCD_and_GR32_TC:sub_t1
0, // GR32_ABCD_and_GR32_TC:sub_xmm
0, // GR32_ABCD_and_GR32_TC:sub_ymm
},
{ // GR32_AD
6, // GR32_AD:sub_8bit -> GR8_ABCD_L
5, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_AD:sub_8bit_hi_phony
22, // GR32_AD:sub_16bit -> GR16_ABCD
0, // GR32_AD:sub_16bit_hi
0, // GR32_AD:sub_32bit
0, // GR32_AD:sub_mask_0
0, // GR32_AD:sub_mask_1
0, // GR32_AD:sub_t0
0, // GR32_AD:sub_t1
0, // GR32_AD:sub_xmm
0, // GR32_AD:sub_ymm
},
{ // GR32_ArgRef
6, // GR32_ArgRef:sub_8bit -> GR8_ABCD_L
5, // GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ArgRef:sub_8bit_hi_phony
22, // GR32_ArgRef:sub_16bit -> GR16_ABCD
0, // GR32_ArgRef:sub_16bit_hi
0, // GR32_ArgRef:sub_32bit
0, // GR32_ArgRef:sub_mask_0
0, // GR32_ArgRef:sub_mask_1
0, // GR32_ArgRef:sub_t0
0, // GR32_ArgRef:sub_t1
0, // GR32_ArgRef:sub_xmm
0, // GR32_ArgRef:sub_ymm
},
{ // GR32_BPSP
3, // GR32_BPSP:sub_8bit -> GR8_NOREX2
0, // GR32_BPSP:sub_8bit_hi
0, // GR32_BPSP:sub_8bit_hi_phony
10, // GR32_BPSP:sub_16bit -> GR16_NOREX
0, // GR32_BPSP:sub_16bit_hi
0, // GR32_BPSP:sub_32bit
0, // GR32_BPSP:sub_mask_0
0, // GR32_BPSP:sub_mask_1
0, // GR32_BPSP:sub_t0
0, // GR32_BPSP:sub_t1
0, // GR32_BPSP:sub_xmm
0, // GR32_BPSP:sub_ymm
},
{ // GR32_BSI
3, // GR32_BSI:sub_8bit -> GR8_NOREX2
5, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_BSI:sub_8bit_hi_phony
10, // GR32_BSI:sub_16bit -> GR16_NOREX
0, // GR32_BSI:sub_16bit_hi
0, // GR32_BSI:sub_32bit
0, // GR32_BSI:sub_mask_0
0, // GR32_BSI:sub_mask_1
0, // GR32_BSI:sub_t0
0, // GR32_BSI:sub_t1
0, // GR32_BSI:sub_xmm
0, // GR32_BSI:sub_ymm
},
{ // GR32_CB
6, // GR32_CB:sub_8bit -> GR8_ABCD_L
5, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_CB:sub_8bit_hi_phony
22, // GR32_CB:sub_16bit -> GR16_ABCD
0, // GR32_CB:sub_16bit_hi
0, // GR32_CB:sub_32bit
0, // GR32_CB:sub_mask_0
0, // GR32_CB:sub_mask_1
0, // GR32_CB:sub_t0
0, // GR32_CB:sub_t1
0, // GR32_CB:sub_xmm
0, // GR32_CB:sub_ymm
},
{ // GR32_DC
6, // GR32_DC:sub_8bit -> GR8_ABCD_L
5, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_DC:sub_8bit_hi_phony
22, // GR32_DC:sub_16bit -> GR16_ABCD
0, // GR32_DC:sub_16bit_hi
0, // GR32_DC:sub_32bit
0, // GR32_DC:sub_mask_0
0, // GR32_DC:sub_mask_1
0, // GR32_DC:sub_t0
0, // GR32_DC:sub_t1
0, // GR32_DC:sub_xmm
0, // GR32_DC:sub_ymm
},
{ // GR32_DIBP
3, // GR32_DIBP:sub_8bit -> GR8_NOREX2
0, // GR32_DIBP:sub_8bit_hi
0, // GR32_DIBP:sub_8bit_hi_phony
10, // GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR32_DIBP:sub_16bit_hi
0, // GR32_DIBP:sub_32bit
0, // GR32_DIBP:sub_mask_0
0, // GR32_DIBP:sub_mask_1
0, // GR32_DIBP:sub_t0
0, // GR32_DIBP:sub_t1
0, // GR32_DIBP:sub_xmm
0, // GR32_DIBP:sub_ymm
},
{ // GR32_SIDI
3, // GR32_SIDI:sub_8bit -> GR8_NOREX2
0, // GR32_SIDI:sub_8bit_hi
0, // GR32_SIDI:sub_8bit_hi_phony
10, // GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR32_SIDI:sub_16bit_hi
0, // GR32_SIDI:sub_32bit
0, // GR32_SIDI:sub_mask_0
0, // GR32_SIDI:sub_mask_1
0, // GR32_SIDI:sub_t0
0, // GR32_SIDI:sub_t1
0, // GR32_SIDI:sub_xmm
0, // GR32_SIDI:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
3, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8_NOREX2
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
10, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
66, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_t0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_t1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
},
{ // CCR
0, // CCR:sub_8bit
0, // CCR:sub_8bit_hi
0, // CCR:sub_8bit_hi_phony
0, // CCR:sub_16bit
0, // CCR:sub_16bit_hi
0, // CCR:sub_32bit
0, // CCR:sub_mask_0
0, // CCR:sub_mask_1
0, // CCR:sub_t0
0, // CCR:sub_t1
0, // CCR:sub_xmm
0, // CCR:sub_ymm
},
{ // DFCCR
0, // DFCCR:sub_8bit
0, // DFCCR:sub_8bit_hi
0, // DFCCR:sub_8bit_hi_phony
0, // DFCCR:sub_16bit
0, // DFCCR:sub_16bit_hi
0, // DFCCR:sub_32bit
0, // DFCCR:sub_mask_0
0, // DFCCR:sub_mask_1
0, // DFCCR:sub_t0
0, // DFCCR:sub_t1
0, // DFCCR:sub_xmm
0, // DFCCR:sub_ymm
},
{ // GR32_ABCD_and_GR32_BSI
6, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
5, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
22, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
0, // GR32_ABCD_and_GR32_BSI:sub_32bit
0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
0, // GR32_ABCD_and_GR32_BSI:sub_t0
0, // GR32_ABCD_and_GR32_BSI:sub_t1
0, // GR32_ABCD_and_GR32_BSI:sub_xmm
0, // GR32_ABCD_and_GR32_BSI:sub_ymm
},
{ // GR32_AD_and_GR32_ArgRef
6, // GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
5, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
22, // GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
0, // GR32_AD_and_GR32_ArgRef:sub_16bit_hi
0, // GR32_AD_and_GR32_ArgRef:sub_32bit
0, // GR32_AD_and_GR32_ArgRef:sub_mask_0
0, // GR32_AD_and_GR32_ArgRef:sub_mask_1
0, // GR32_AD_and_GR32_ArgRef:sub_t0
0, // GR32_AD_and_GR32_ArgRef:sub_t1
0, // GR32_AD_and_GR32_ArgRef:sub_xmm
0, // GR32_AD_and_GR32_ArgRef:sub_ymm
},
{ // GR32_ArgRef_and_GR32_CB
6, // GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
5, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
22, // GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
0, // GR32_ArgRef_and_GR32_CB:sub_16bit_hi
0, // GR32_ArgRef_and_GR32_CB:sub_32bit
0, // GR32_ArgRef_and_GR32_CB:sub_mask_0
0, // GR32_ArgRef_and_GR32_CB:sub_mask_1
0, // GR32_ArgRef_and_GR32_CB:sub_t0
0, // GR32_ArgRef_and_GR32_CB:sub_t1
0, // GR32_ArgRef_and_GR32_CB:sub_xmm
0, // GR32_ArgRef_and_GR32_CB:sub_ymm
},
{ // GR32_BPSP_and_GR32_DIBP
3, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
10, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
0, // GR32_BPSP_and_GR32_DIBP:sub_t0
0, // GR32_BPSP_and_GR32_DIBP:sub_t1
0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
},
{ // GR32_BPSP_and_GR32_TC
3, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
10, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
0, // GR32_BPSP_and_GR32_TC:sub_32bit
0, // GR32_BPSP_and_GR32_TC:sub_mask_0
0, // GR32_BPSP_and_GR32_TC:sub_mask_1
0, // GR32_BPSP_and_GR32_TC:sub_t0
0, // GR32_BPSP_and_GR32_TC:sub_t1
0, // GR32_BPSP_and_GR32_TC:sub_xmm
0, // GR32_BPSP_and_GR32_TC:sub_ymm
},
{ // GR32_BSI_and_GR32_SIDI
3, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
10, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
0, // GR32_BSI_and_GR32_SIDI:sub_32bit
0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
0, // GR32_BSI_and_GR32_SIDI:sub_t0
0, // GR32_BSI_and_GR32_SIDI:sub_t1
0, // GR32_BSI_and_GR32_SIDI:sub_xmm
0, // GR32_BSI_and_GR32_SIDI:sub_ymm
},
{ // GR32_DIBP_and_GR32_SIDI
3, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
10, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
0, // GR32_DIBP_and_GR32_SIDI:sub_t0
0, // GR32_DIBP_and_GR32_SIDI:sub_t1
0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
3, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8_NOREX2
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
10, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_t0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_t1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
},
{ // LOW32_ADDR_ACCESS_with_sub_32bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_t0
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_t1
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
},
{ // RFP64
0, // RFP64:sub_8bit
0, // RFP64:sub_8bit_hi
0, // RFP64:sub_8bit_hi_phony
0, // RFP64:sub_16bit
0, // RFP64:sub_16bit_hi
0, // RFP64:sub_32bit
0, // RFP64:sub_mask_0
0, // RFP64:sub_mask_1
0, // RFP64:sub_t0
0, // RFP64:sub_t1
0, // RFP64:sub_xmm
0, // RFP64:sub_ymm
},
{ // GR64
1, // GR64:sub_8bit -> GR8
5, // GR64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64:sub_8bit_hi_phony
8, // GR64:sub_16bit -> GR16
0, // GR64:sub_16bit_hi
36, // GR64:sub_32bit -> GR32
0, // GR64:sub_mask_0
0, // GR64:sub_mask_1
0, // GR64:sub_t0
0, // GR64:sub_t1
0, // GR64:sub_xmm
0, // GR64:sub_ymm
},
{ // FR64X
0, // FR64X:sub_8bit
0, // FR64X:sub_8bit_hi
0, // FR64X:sub_8bit_hi_phony
0, // FR64X:sub_16bit
0, // FR64X:sub_16bit_hi
0, // FR64X:sub_32bit
0, // FR64X:sub_mask_0
0, // FR64X:sub_mask_1
0, // FR64X:sub_t0
0, // FR64X:sub_t1
0, // FR64X:sub_xmm
0, // FR64X:sub_ymm
},
{ // GR64_with_sub_8bit
1, // GR64_with_sub_8bit:sub_8bit -> GR8
5, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_8bit:sub_8bit_hi_phony
8, // GR64_with_sub_8bit:sub_16bit -> GR16
0, // GR64_with_sub_8bit:sub_16bit_hi
36, // GR64_with_sub_8bit:sub_32bit -> GR32
0, // GR64_with_sub_8bit:sub_mask_0
0, // GR64_with_sub_8bit:sub_mask_1
0, // GR64_with_sub_8bit:sub_t0
0, // GR64_with_sub_8bit:sub_t1
0, // GR64_with_sub_8bit:sub_xmm
0, // GR64_with_sub_8bit:sub_ymm
},
{ // GR64_NOSP
1, // GR64_NOSP:sub_8bit -> GR8
5, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOSP:sub_8bit_hi_phony
8, // GR64_NOSP:sub_16bit -> GR16
0, // GR64_NOSP:sub_16bit_hi
37, // GR64_NOSP:sub_32bit -> GR32_NOSP
0, // GR64_NOSP:sub_mask_0
0, // GR64_NOSP:sub_mask_1
0, // GR64_NOSP:sub_t0
0, // GR64_NOSP:sub_t1
0, // GR64_NOSP:sub_xmm
0, // GR64_NOSP:sub_ymm
},
{ // GR64_NOREX2
3, // GR64_NOREX2:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX2:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX2:sub_8bit_hi_phony
9, // GR64_NOREX2:sub_16bit -> GR16_NOREX2
0, // GR64_NOREX2:sub_16bit_hi
41, // GR64_NOREX2:sub_32bit -> GR32_NOREX2
0, // GR64_NOREX2:sub_mask_0
0, // GR64_NOREX2:sub_mask_1
0, // GR64_NOREX2:sub_t0
0, // GR64_NOREX2:sub_t1
0, // GR64_NOREX2:sub_xmm
0, // GR64_NOREX2:sub_ymm
},
{ // CONTROL_REG
0, // CONTROL_REG:sub_8bit
0, // CONTROL_REG:sub_8bit_hi
0, // CONTROL_REG:sub_8bit_hi_phony
0, // CONTROL_REG:sub_16bit
0, // CONTROL_REG:sub_16bit_hi
0, // CONTROL_REG:sub_32bit
0, // CONTROL_REG:sub_mask_0
0, // CONTROL_REG:sub_mask_1
0, // CONTROL_REG:sub_t0
0, // CONTROL_REG:sub_t1
0, // CONTROL_REG:sub_xmm
0, // CONTROL_REG:sub_ymm
},
{ // FR64
0, // FR64:sub_8bit
0, // FR64:sub_8bit_hi
0, // FR64:sub_8bit_hi_phony
0, // FR64:sub_16bit
0, // FR64:sub_16bit_hi
0, // FR64:sub_32bit
0, // FR64:sub_mask_0
0, // FR64:sub_mask_1
0, // FR64:sub_t0
0, // FR64:sub_t1
0, // FR64:sub_xmm
0, // FR64:sub_ymm
},
{ // GR64_with_sub_16bit_in_GR16_NOREX2
3, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
5, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
9, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
41, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_NOREX2
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_t0
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_t1
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_xmm
0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_ymm
},
{ // GR64_NOREX2_NOSP
3, // GR64_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX2_NOSP:sub_8bit_hi_phony
9, // GR64_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
0, // GR64_NOREX2_NOSP:sub_16bit_hi
42, // GR64_NOREX2_NOSP:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64_NOREX2_NOSP:sub_mask_0
0, // GR64_NOREX2_NOSP:sub_mask_1
0, // GR64_NOREX2_NOSP:sub_t0
0, // GR64_NOREX2_NOSP:sub_t1
0, // GR64_NOREX2_NOSP:sub_xmm
0, // GR64_NOREX2_NOSP:sub_ymm
},
{ // GR64PLTSafe
3, // GR64PLTSafe:sub_8bit -> GR8_NOREX2
5, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
0, // GR64PLTSafe:sub_8bit_hi_phony
9, // GR64PLTSafe:sub_16bit -> GR16_NOREX2
0, // GR64PLTSafe:sub_16bit_hi
42, // GR64PLTSafe:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64PLTSafe:sub_mask_0
0, // GR64PLTSafe:sub_mask_1
0, // GR64PLTSafe:sub_t0
0, // GR64PLTSafe:sub_t1
0, // GR64PLTSafe:sub_xmm
0, // GR64PLTSafe:sub_ymm
},
{ // GR64_TC
3, // GR64_TC:sub_8bit -> GR8_NOREX2
5, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC:sub_8bit_hi_phony
9, // GR64_TC:sub_16bit -> GR16_NOREX2
0, // GR64_TC:sub_16bit_hi
41, // GR64_TC:sub_32bit -> GR32_NOREX2
0, // GR64_TC:sub_mask_0
0, // GR64_TC:sub_mask_1
0, // GR64_TC:sub_t0
0, // GR64_TC:sub_t1
0, // GR64_TC:sub_xmm
0, // GR64_TC:sub_ymm
},
{ // GR64_NOREX
3, // GR64_NOREX:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX:sub_8bit_hi_phony
10, // GR64_NOREX:sub_16bit -> GR16_NOREX
0, // GR64_NOREX:sub_16bit_hi
44, // GR64_NOREX:sub_32bit -> GR32_NOREX
0, // GR64_NOREX:sub_mask_0
0, // GR64_NOREX:sub_mask_1
0, // GR64_NOREX:sub_t0
0, // GR64_NOREX:sub_t1
0, // GR64_NOREX:sub_xmm
0, // GR64_NOREX:sub_ymm
},
{ // GR64_TCW64
3, // GR64_TCW64:sub_8bit -> GR8_NOREX2
5, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TCW64:sub_8bit_hi_phony
9, // GR64_TCW64:sub_16bit -> GR16_NOREX2
0, // GR64_TCW64:sub_16bit_hi
41, // GR64_TCW64:sub_32bit -> GR32_NOREX2
0, // GR64_TCW64:sub_mask_0
0, // GR64_TCW64:sub_mask_1
0, // GR64_TCW64:sub_t0
0, // GR64_TCW64:sub_t1
0, // GR64_TCW64:sub_xmm
0, // GR64_TCW64:sub_ymm
},
{ // GR64_TC_with_sub_8bit
3, // GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
5, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
9, // GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
0, // GR64_TC_with_sub_8bit:sub_16bit_hi
41, // GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
0, // GR64_TC_with_sub_8bit:sub_mask_0
0, // GR64_TC_with_sub_8bit:sub_mask_1
0, // GR64_TC_with_sub_8bit:sub_t0
0, // GR64_TC_with_sub_8bit:sub_t1
0, // GR64_TC_with_sub_8bit:sub_xmm
0, // GR64_TC_with_sub_8bit:sub_ymm
},
{ // GR64_NOREX2_NOSP_and_GR64_TC
3, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi_phony
9, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit -> GR16_NOREX2
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit_hi
42, // GR64_NOREX2_NOSP_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_0
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_1
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_t0
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_t1
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_xmm
0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_ymm
},
{ // GR64_TCW64_with_sub_8bit
3, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8_NOREX2
5, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
9, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16_NOREX2
0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
41, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32_NOREX2
0, // GR64_TCW64_with_sub_8bit:sub_mask_0
0, // GR64_TCW64_with_sub_8bit:sub_mask_1
0, // GR64_TCW64_with_sub_8bit:sub_t0
0, // GR64_TCW64_with_sub_8bit:sub_t1
0, // GR64_TCW64_with_sub_8bit:sub_xmm
0, // GR64_TCW64_with_sub_8bit:sub_ymm
},
{ // GR64_TC_and_GR64_TCW64
3, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
5, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
9, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
41, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32_NOREX2
0, // GR64_TC_and_GR64_TCW64:sub_mask_0
0, // GR64_TC_and_GR64_TCW64:sub_mask_1
0, // GR64_TC_and_GR64_TCW64:sub_t0
0, // GR64_TC_and_GR64_TCW64:sub_t1
0, // GR64_TC_and_GR64_TCW64:sub_xmm
0, // GR64_TC_and_GR64_TCW64:sub_ymm
},
{ // GR64_with_sub_16bit_in_GR16_NOREX
3, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
5, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
10, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
44, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_t0
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_t1
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
},
{ // VK64
0, // VK64:sub_8bit
0, // VK64:sub_8bit_hi
0, // VK64:sub_8bit_hi_phony
0, // VK64:sub_16bit
0, // VK64:sub_16bit_hi
0, // VK64:sub_32bit
0, // VK64:sub_mask_0
0, // VK64:sub_mask_1
0, // VK64:sub_t0
0, // VK64:sub_t1
0, // VK64:sub_xmm
0, // VK64:sub_ymm
},
{ // VR64
0, // VR64:sub_8bit
0, // VR64:sub_8bit_hi
0, // VR64:sub_8bit_hi_phony
0, // VR64:sub_16bit
0, // VR64:sub_16bit_hi
0, // VR64:sub_32bit
0, // VR64:sub_mask_0
0, // VR64:sub_mask_1
0, // VR64:sub_t0
0, // VR64:sub_t1
0, // VR64:sub_xmm
0, // VR64:sub_ymm
},
{ // GR64PLTSafe_and_GR64_TC
3, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
5, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
9, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX2
0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
42, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
0, // GR64PLTSafe_and_GR64_TC:sub_t0
0, // GR64PLTSafe_and_GR64_TC:sub_t1
0, // GR64PLTSafe_and_GR64_TC:sub_xmm
0, // GR64PLTSafe_and_GR64_TC:sub_ymm
},
{ // GR64_NOREX2_NOSP_and_GR64_TCW64
3, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
9, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
42, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t0
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t1
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
},
{ // GR64_NOREX_NOSP
3, // GR64_NOREX_NOSP:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
10, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_NOSP:sub_16bit_hi
46, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
0, // GR64_NOREX_NOSP:sub_mask_0
0, // GR64_NOREX_NOSP:sub_mask_1
0, // GR64_NOREX_NOSP:sub_t0
0, // GR64_NOREX_NOSP:sub_t1
0, // GR64_NOREX_NOSP:sub_xmm
0, // GR64_NOREX_NOSP:sub_ymm
},
{ // GR64_NOREX_and_GR64_TC
3, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
10, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
44, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
0, // GR64_NOREX_and_GR64_TC:sub_mask_0
0, // GR64_NOREX_and_GR64_TC:sub_mask_1
0, // GR64_NOREX_and_GR64_TC:sub_t0
0, // GR64_NOREX_and_GR64_TC:sub_t1
0, // GR64_NOREX_and_GR64_TC:sub_xmm
0, // GR64_NOREX_and_GR64_TC:sub_ymm
},
{ // GR64_TCW64_and_GR64_TC_with_sub_8bit
3, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
5, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
9, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
41, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_t0
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_t1
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
},
{ // VK64WM
0, // VK64WM:sub_8bit
0, // VK64WM:sub_8bit_hi
0, // VK64WM:sub_8bit_hi_phony
0, // VK64WM:sub_16bit
0, // VK64WM:sub_16bit_hi
0, // VK64WM:sub_32bit
0, // VK64WM:sub_mask_0
0, // VK64WM:sub_mask_1
0, // VK64WM:sub_t0
0, // VK64WM:sub_t1
0, // VK64WM:sub_xmm
0, // VK64WM:sub_ymm
},
{ // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
3, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
5, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
9, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
42, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t0
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_t1
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
},
{ // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
3, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
5, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
10, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
44, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_t0
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_t1
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
},
{ // GR64PLTSafe_and_GR64_TCW64
3, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
5, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
9, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
42, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
0, // GR64PLTSafe_and_GR64_TCW64:sub_t0
0, // GR64PLTSafe_and_GR64_TCW64:sub_t1
0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
},
{ // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
3, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
10, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
46, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_t0
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_t1
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
},
{ // GR64_NOREX_and_GR64_TCW64
3, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
5, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
10, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
50, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
0, // GR64_NOREX_and_GR64_TCW64:sub_t0
0, // GR64_NOREX_and_GR64_TCW64:sub_t1
0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
},
{ // GR64_ABCD
6, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
5, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_ABCD:sub_8bit_hi_phony
22, // GR64_ABCD:sub_16bit -> GR16_ABCD
0, // GR64_ABCD:sub_16bit_hi
49, // GR64_ABCD:sub_32bit -> GR32_ABCD
0, // GR64_ABCD:sub_mask_0
0, // GR64_ABCD:sub_mask_1
0, // GR64_ABCD:sub_t0
0, // GR64_ABCD:sub_t1
0, // GR64_ABCD:sub_xmm
0, // GR64_ABCD:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_TC
3, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8_NOREX2
5, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
50, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_TC:sub_t0
0, // GR64_with_sub_32bit_in_GR32_TC:sub_t1
0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
51, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_t0
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_t1
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
},
{ // GR64_AD
6, // GR64_AD:sub_8bit -> GR8_ABCD_L
5, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_AD:sub_8bit_hi_phony
22, // GR64_AD:sub_16bit -> GR16_ABCD
0, // GR64_AD:sub_16bit_hi
52, // GR64_AD:sub_32bit -> GR32_AD
0, // GR64_AD:sub_mask_0
0, // GR64_AD:sub_mask_1
0, // GR64_AD:sub_t0
0, // GR64_AD:sub_t1
0, // GR64_AD:sub_xmm
0, // GR64_AD:sub_ymm
},
{ // GR64_ArgRef
3, // GR64_ArgRef:sub_8bit -> GR8_NOREX2
0, // GR64_ArgRef:sub_8bit_hi
0, // GR64_ArgRef:sub_8bit_hi_phony
9, // GR64_ArgRef:sub_16bit -> GR16_NOREX2
0, // GR64_ArgRef:sub_16bit_hi
42, // GR64_ArgRef:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64_ArgRef:sub_mask_0
0, // GR64_ArgRef:sub_mask_1
0, // GR64_ArgRef:sub_t0
0, // GR64_ArgRef:sub_t1
0, // GR64_ArgRef:sub_xmm
0, // GR64_ArgRef:sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS_RBP
3, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8_NOREX2
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
10, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
66, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_t0
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_t1
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ArgRef
6, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
5, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi_phony
22, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit_hi
53, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_32bit -> GR32_ArgRef
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_t0
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_t1
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP
3, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8_NOREX2
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
54, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_t0
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_t1
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI
3, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8_NOREX2
5, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
55, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_t0
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_t1
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_CB
6, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
22, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
56, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_CB:sub_t0
0, // GR64_with_sub_32bit_in_GR32_CB:sub_t1
0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP
3, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8_NOREX2
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
58, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_t0
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_t1
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_SIDI
3, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8_NOREX2
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
59, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_t0
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_t1
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
},
{ // GR64_ArgRef_and_GR64_TC
3, // GR64_ArgRef_and_GR64_TC:sub_8bit -> GR8_NOREX2
0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi
0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi_phony
9, // GR64_ArgRef_and_GR64_TC:sub_16bit -> GR16_NOREX2
0, // GR64_ArgRef_and_GR64_TC:sub_16bit_hi
42, // GR64_ArgRef_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
0, // GR64_ArgRef_and_GR64_TC:sub_mask_0
0, // GR64_ArgRef_and_GR64_TC:sub_mask_1
0, // GR64_ArgRef_and_GR64_TC:sub_t0
0, // GR64_ArgRef_and_GR64_TC:sub_t1
0, // GR64_ArgRef_and_GR64_TC:sub_xmm
0, // GR64_ArgRef_and_GR64_TC:sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS
0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
0, // GR64_and_LOW32_ADDR_ACCESS:sub_t0
0, // GR64_and_LOW32_ADDR_ACCESS:sub_t1
0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
63, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_t0
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_t1
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
6, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
22, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit_hi
64, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_32bit -> GR32_AD_and_GR32_ArgRef
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_t0
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_t1
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
6, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
5, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
22, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit_hi
65, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_32bit -> GR32_ArgRef_and_GR32_CB
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_t0
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_t1
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
66, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_t0
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_t1
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
67, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_t0
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_t1
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
3, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
68, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_t0
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_t1
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
3, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
10, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
69, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_t0
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_t1
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
},
{ // RST
0, // RST:sub_8bit
0, // RST:sub_8bit_hi
0, // RST:sub_8bit_hi_phony
0, // RST:sub_16bit
0, // RST:sub_16bit_hi
0, // RST:sub_32bit
0, // RST:sub_mask_0
0, // RST:sub_mask_1
0, // RST:sub_t0
0, // RST:sub_t1
0, // RST:sub_xmm
0, // RST:sub_ymm
},
{ // RFP80
0, // RFP80:sub_8bit
0, // RFP80:sub_8bit_hi
0, // RFP80:sub_8bit_hi_phony
0, // RFP80:sub_16bit
0, // RFP80:sub_16bit_hi
0, // RFP80:sub_32bit
0, // RFP80:sub_mask_0
0, // RFP80:sub_mask_1
0, // RFP80:sub_t0
0, // RFP80:sub_t1
0, // RFP80:sub_xmm
0, // RFP80:sub_ymm
},
{ // RFP80_7
0, // RFP80_7:sub_8bit
0, // RFP80_7:sub_8bit_hi
0, // RFP80_7:sub_8bit_hi_phony
0, // RFP80_7:sub_16bit
0, // RFP80_7:sub_16bit_hi
0, // RFP80_7:sub_32bit
0, // RFP80_7:sub_mask_0
0, // RFP80_7:sub_mask_1
0, // RFP80_7:sub_t0
0, // RFP80_7:sub_t1
0, // RFP80_7:sub_xmm
0, // RFP80_7:sub_ymm
},
{ // VR128X
0, // VR128X:sub_8bit
0, // VR128X:sub_8bit_hi
0, // VR128X:sub_8bit_hi_phony
0, // VR128X:sub_16bit
0, // VR128X:sub_16bit_hi
0, // VR128X:sub_32bit
0, // VR128X:sub_mask_0
0, // VR128X:sub_mask_1
0, // VR128X:sub_t0
0, // VR128X:sub_t1
0, // VR128X:sub_xmm
0, // VR128X:sub_ymm
},
{ // VR128
0, // VR128:sub_8bit
0, // VR128:sub_8bit_hi
0, // VR128:sub_8bit_hi_phony
0, // VR128:sub_16bit
0, // VR128:sub_16bit_hi
0, // VR128:sub_32bit
0, // VR128:sub_mask_0
0, // VR128:sub_mask_1
0, // VR128:sub_t0
0, // VR128:sub_t1
0, // VR128:sub_xmm
0, // VR128:sub_ymm
},
{ // VR256X
0, // VR256X:sub_8bit
0, // VR256X:sub_8bit_hi
0, // VR256X:sub_8bit_hi_phony
0, // VR256X:sub_16bit
0, // VR256X:sub_16bit_hi
0, // VR256X:sub_32bit
0, // VR256X:sub_mask_0
0, // VR256X:sub_mask_1
0, // VR256X:sub_t0
0, // VR256X:sub_t1
24, // VR256X:sub_xmm -> FR16X
0, // VR256X:sub_ymm
},
{ // VR256
0, // VR256:sub_8bit
0, // VR256:sub_8bit_hi
0, // VR256:sub_8bit_hi_phony
0, // VR256:sub_16bit
0, // VR256:sub_16bit_hi
0, // VR256:sub_32bit
0, // VR256:sub_mask_0
0, // VR256:sub_mask_1
0, // VR256:sub_t0
0, // VR256:sub_t1
25, // VR256:sub_xmm -> FR16
0, // VR256:sub_ymm
},
{ // VR512
0, // VR512:sub_8bit
0, // VR512:sub_8bit_hi
0, // VR512:sub_8bit_hi_phony
0, // VR512:sub_16bit
0, // VR512:sub_16bit_hi
0, // VR512:sub_32bit
0, // VR512:sub_mask_0
0, // VR512:sub_mask_1
0, // VR512:sub_t0
0, // VR512:sub_t1
24, // VR512:sub_xmm -> FR16X
130, // VR512:sub_ymm -> VR256X
},
{ // VR512_0_15
0, // VR512_0_15:sub_8bit
0, // VR512_0_15:sub_8bit_hi
0, // VR512_0_15:sub_8bit_hi_phony
0, // VR512_0_15:sub_16bit
0, // VR512_0_15:sub_16bit_hi
0, // VR512_0_15:sub_32bit
0, // VR512_0_15:sub_mask_0
0, // VR512_0_15:sub_mask_1
0, // VR512_0_15:sub_t0
0, // VR512_0_15:sub_t1
25, // VR512_0_15:sub_xmm -> FR16
131, // VR512_0_15:sub_ymm -> VR256
},
{ // TILE
0, // TILE:sub_8bit
0, // TILE:sub_8bit_hi
0, // TILE:sub_8bit_hi_phony
0, // TILE:sub_16bit
0, // TILE:sub_16bit_hi
0, // TILE:sub_32bit
0, // TILE:sub_mask_0
0, // TILE:sub_mask_1
0, // TILE:sub_t0
0, // TILE:sub_t1
0, // TILE:sub_xmm
0, // TILE:sub_ymm
},
{ // TILEPAIR
0, // TILEPAIR:sub_8bit
0, // TILEPAIR:sub_8bit_hi
0, // TILEPAIR:sub_8bit_hi_phony
0, // TILEPAIR:sub_16bit
0, // TILEPAIR:sub_16bit_hi
0, // TILEPAIR:sub_32bit
0, // TILEPAIR:sub_mask_0
0, // TILEPAIR:sub_mask_1
134, // TILEPAIR:sub_t0 -> TILE
134, // TILEPAIR:sub_t1 -> TILE
0, // TILEPAIR:sub_xmm
0, // TILEPAIR:sub_ymm
},
};
assert(RC && "Missing regclass");
if (!Idx) return RC;
--Idx;
assert(Idx < 12 && "Bad subreg");
unsigned TV = Table[RC->getID()][Idx];
return TV ? getRegClass(TV - 1) : nullptr;
}
/// Get the weight in units of pressure for this register class.
const RegClassWeight &X86GenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
static const RegClassWeight RCWeightTable[] = {
{1, 36}, // GR8
{0, 0}, // GRH8
{1, 20}, // GR8_NOREX2
{1, 8}, // GR8_NOREX
{1, 4}, // GR8_ABCD_H
{1, 4}, // GR8_ABCD_L
{0, 0}, // GRH16
{2, 64}, // GR16
{2, 32}, // GR16_NOREX2
{2, 16}, // GR16_NOREX
{1, 8}, // VK1
{1, 8}, // VK16
{1, 8}, // VK2
{1, 8}, // VK4
{1, 8}, // VK8
{1, 7}, // VK16WM
{1, 7}, // VK1WM
{1, 7}, // VK2WM
{1, 7}, // VK4WM
{1, 7}, // VK8WM
{1, 6}, // SEGMENT_REG
{2, 8}, // GR16_ABCD
{0, 0}, // FPCCR
{1, 32}, // FR16X
{1, 16}, // FR16
{2, 8}, // VK16PAIR
{2, 8}, // VK1PAIR
{2, 8}, // VK2PAIR
{2, 8}, // VK4PAIR
{2, 8}, // VK8PAIR
{2, 6}, // VK1PAIR_with_sub_mask_0_in_VK1WM
{2, 66}, // LOW32_ADDR_ACCESS_RBP
{2, 66}, // LOW32_ADDR_ACCESS
{2, 64}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
{1, 32}, // FR32X
{2, 64}, // GR32
{2, 62}, // GR32_NOSP
{2, 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
{1, 16}, // DEBUG_REG
{1, 16}, // FR32
{2, 32}, // GR32_NOREX2
{2, 30}, // GR32_NOREX2_NOSP
{2, 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
{2, 16}, // GR32_NOREX
{1, 8}, // VK32
{2, 14}, // GR32_NOREX_NOSP
{1, 7}, // RFP32
{1, 7}, // VK32WM
{2, 8}, // GR32_ABCD
{2, 8}, // GR32_TC
{2, 6}, // GR32_ABCD_and_GR32_TC
{2, 4}, // GR32_AD
{2, 4}, // GR32_ArgRef
{2, 4}, // GR32_BPSP
{2, 4}, // GR32_BSI
{2, 4}, // GR32_CB
{2, 4}, // GR32_DC
{2, 4}, // GR32_DIBP
{2, 4}, // GR32_SIDI
{2, 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
{0, 0}, // CCR
{0, 0}, // DFCCR
{2, 2}, // GR32_ABCD_and_GR32_BSI
{2, 2}, // GR32_AD_and_GR32_ArgRef
{2, 2}, // GR32_ArgRef_and_GR32_CB
{2, 2}, // GR32_BPSP_and_GR32_DIBP
{2, 2}, // GR32_BPSP_and_GR32_TC
{2, 2}, // GR32_BSI_and_GR32_SIDI
{2, 2}, // GR32_DIBP_and_GR32_SIDI
{2, 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
{2, 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
{1, 7}, // RFP64
{2, 66}, // GR64
{1, 32}, // FR64X
{2, 64}, // GR64_with_sub_8bit
{2, 62}, // GR64_NOSP
{2, 34}, // GR64_NOREX2
{1, 16}, // CONTROL_REG
{1, 16}, // FR64
{2, 32}, // GR64_with_sub_16bit_in_GR16_NOREX2
{2, 30}, // GR64_NOREX2_NOSP
{2, 26}, // GR64PLTSafe
{2, 20}, // GR64_TC
{2, 18}, // GR64_NOREX
{2, 18}, // GR64_TCW64
{2, 18}, // GR64_TC_with_sub_8bit
{2, 16}, // GR64_NOREX2_NOSP_and_GR64_TC
{2, 16}, // GR64_TCW64_with_sub_8bit
{2, 16}, // GR64_TC_and_GR64_TCW64
{2, 16}, // GR64_with_sub_16bit_in_GR16_NOREX
{1, 8}, // VK64
{1, 8}, // VR64
{2, 14}, // GR64PLTSafe_and_GR64_TC
{2, 14}, // GR64_NOREX2_NOSP_and_GR64_TCW64
{2, 14}, // GR64_NOREX_NOSP
{2, 14}, // GR64_NOREX_and_GR64_TC
{2, 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
{1, 7}, // VK64WM
{2, 12}, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
{2, 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
{2, 10}, // GR64PLTSafe_and_GR64_TCW64
{2, 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
{2, 10}, // GR64_NOREX_and_GR64_TCW64
{2, 8}, // GR64_ABCD
{2, 8}, // GR64_with_sub_32bit_in_GR32_TC
{2, 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
{2, 4}, // GR64_AD
{2, 4}, // GR64_ArgRef
{2, 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
{2, 4}, // GR64_with_sub_32bit_in_GR32_ArgRef
{2, 4}, // GR64_with_sub_32bit_in_GR32_BPSP
{2, 4}, // GR64_with_sub_32bit_in_GR32_BSI
{2, 4}, // GR64_with_sub_32bit_in_GR32_CB
{2, 4}, // GR64_with_sub_32bit_in_GR32_DIBP
{2, 4}, // GR64_with_sub_32bit_in_GR32_SIDI
{2, 2}, // GR64_ArgRef_and_GR64_TC
{2, 2}, // GR64_and_LOW32_ADDR_ACCESS
{2, 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
{2, 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
{2, 2}, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
{2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
{2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
{2, 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
{2, 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
{0, 0}, // RST
{1, 7}, // RFP80
{0, 0}, // RFP80_7
{1, 32}, // VR128X
{1, 16}, // VR128
{1, 32}, // VR256X
{1, 16}, // VR256
{1, 32}, // VR512
{1, 16}, // VR512_0_15
{1, 8}, // TILE
{2, 8}, // TILEPAIR
};
return RCWeightTable[RC->getID()];
}
/// Get the weight in units of pressure for this register unit.
unsigned X86GenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
assert(RegUnit < 221 && "invalid register unit");
// All register units have unit weight.
return 1;
}
// Get the number of dimensions of register pressure.
unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
return 36;
}
// Get the name of this register unit pressure set.
const char *X86GenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
static const char *PressureNameTable[] = {
"SEGMENT_REG",
"GR32_BPSP",
"LOW32_ADDR_ACCESS_with_sub_32bit",
"GR32_BSI",
"GR32_SIDI",
"GR32_DIBP_with_GR32_SIDI",
"GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
"RFP32",
"GR8_ABCD_H_with_GR32_BSI",
"GR8_ABCD_L_with_GR32_BSI",
"VK1",
"VR64",
"TILE",
"GR8_NOREX",
"GR32_TC",
"GR32_BPSP_with_GR32_TC",
"FR16",
"DEBUG_REG",
"CONTROL_REG",
"GR64_NOREX",
"GR64_TCW64",
"GR32_BPSP_with_GR64_TCW64",
"GR64_TC_with_GR64_TCW64",
"GR64_TC",
"FR16X",
"GR64PLTSafe_with_GR64_TC",
"GR8",
"GR8_with_GR32_DIBP",
"GR8_with_GR32_BSI",
"GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
"GR8_with_GR64_NOREX",
"GR8_with_GR64_TCW64",
"GR8_with_GR64_TC",
"GR8_with_GR64PLTSafe",
"GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2",
"GR16",
};
return PressureNameTable[Idx];
}
// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned X86GenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
static const uint8_t PressureLimitTable[] = {
6, // 0: SEGMENT_REG
6, // 1: GR32_BPSP
6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
6, // 3: GR32_BSI
6, // 4: GR32_SIDI
6, // 5: GR32_DIBP_with_GR32_SIDI
6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
7, // 7: RFP32
7, // 8: GR8_ABCD_H_with_GR32_BSI
7, // 9: GR8_ABCD_L_with_GR32_BSI
8, // 10: VK1
8, // 11: VR64
8, // 12: TILE
10, // 13: GR8_NOREX
12, // 14: GR32_TC
12, // 15: GR32_BPSP_with_GR32_TC
16, // 16: FR16
16, // 17: DEBUG_REG
16, // 18: CONTROL_REG
18, // 19: GR64_NOREX
20, // 20: GR64_TCW64
20, // 21: GR32_BPSP_with_GR64_TCW64
22, // 22: GR64_TC_with_GR64_TCW64
26, // 23: GR64_TC
32, // 24: FR16X
34, // 25: GR64PLTSafe_with_GR64_TC
38, // 26: GR8
38, // 27: GR8_with_GR32_DIBP
38, // 28: GR8_with_GR32_BSI
39, // 29: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
42, // 30: GR8_with_GR64_NOREX
43, // 31: GR8_with_GR64_TCW64
44, // 32: GR8_with_GR64_TC
45, // 33: GR8_with_GR64PLTSafe
48, // 34: GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
66, // 35: GR16
};
return PressureLimitTable[Idx];
}
/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
/* 0 */ 0, -1,
/* 2 */ 7, -1,
/* 4 */ 10, -1,
/* 6 */ 11, -1,
/* 8 */ 12, -1,
/* 10 */ 17, -1,
/* 12 */ 18, -1,
/* 14 */ 16, 24, -1,
/* 17 */ 25, 35, -1,
/* 20 */ 19, 23, 25, 30, 35, -1,
/* 26 */ 2, 6, 15, 19, 21, 23, 25, 29, 30, 35, -1,
/* 37 */ 20, 21, 22, 23, 25, 31, 35, -1,
/* 45 */ 22, 23, 25, 32, 35, -1,
/* 51 */ 19, 22, 23, 25, 30, 32, 35, -1,
/* 59 */ 20, 21, 22, 23, 25, 31, 32, 35, -1,
/* 68 */ 14, 15, 19, 20, 21, 22, 23, 25, 30, 31, 32, 35, -1,
/* 81 */ 2, 6, 14, 15, 19, 20, 21, 22, 23, 25, 29, 30, 31, 32, 35, -1,
/* 97 */ 25, 34, 35, -1,
/* 101 */ 19, 23, 25, 30, 34, 35, -1,
/* 108 */ 1, 2, 15, 19, 21, 23, 25, 26, 30, 34, 35, -1,
/* 120 */ 20, 21, 22, 23, 25, 31, 34, 35, -1,
/* 129 */ 22, 23, 25, 32, 34, 35, -1,
/* 136 */ 19, 22, 23, 25, 30, 32, 34, 35, -1,
/* 145 */ 20, 21, 22, 23, 25, 31, 32, 34, 35, -1,
/* 155 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 30, 31, 32, 34, 35, -1,
/* 172 */ 25, 33, 34, 35, -1,
/* 177 */ 19, 23, 25, 30, 33, 34, 35, -1,
/* 185 */ 1, 5, 6, 19, 23, 25, 27, 30, 33, 34, 35, -1,
/* 197 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 29, 30, 33, 34, 35, -1,
/* 214 */ 22, 23, 25, 32, 33, 34, 35, -1,
/* 222 */ 3, 4, 8, 9, 13, 19, 23, 25, 28, 30, 32, 33, 34, 35, -1,
/* 237 */ 4, 5, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
/* 250 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
/* 267 */ 1, 4, 5, 6, 19, 22, 23, 25, 27, 28, 30, 32, 33, 34, 35, -1,
/* 283 */ 20, 21, 22, 23, 25, 31, 32, 33, 34, 35, -1,
/* 294 */ 3, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 312 */ 8, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 330 */ 3, 4, 8, 9, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 351 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 371 */ 1, 4, 5, 6, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 390 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 411 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 432 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 453 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
/* 475 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
};
/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *X86GenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
static const uint16_t RCSetStartTable[] = {
301,1,300,295,312,333,1,18,97,101,4,4,4,4,4,4,4,4,4,4,0,295,1,15,14,4,4,4,4,4,4,18,18,18,15,18,18,97,10,14,97,97,101,101,4,177,2,4,295,157,433,433,433,108,222,294,433,185,237,26,1,1,330,433,432,197,155,250,267,197,81,2,18,15,18,18,17,12,14,97,97,172,45,20,37,129,129,120,59,101,4,6,214,120,177,51,145,4,145,136,283,239,68,295,157,433,433,120,26,433,108,222,294,185,237,145,81,330,433,432,197,155,250,267,1,2,1,15,14,15,14,15,14,8,8,};
return &RCSetsTable[RCSetStartTable[RC->getID()]];
}
/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *X86GenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
assert(RegUnit < 221 && "invalid register unit");
static const uint16_t RUSetStartTable[] = {
454,476,330,330,351,1,453,475,0,1,454,371,1,476,0,1,1,1,1,1,1,1,81,1,1,0,390,1,1,411,1,1,1,1,0,1,0,1,1,1,1,0,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,6,6,6,6,6,6,6,6,416,1,1,416,1,1,416,1,1,416,1,1,300,1,1,300,1,1,300,1,1,300,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,4,4,4,4,4,4,4,4,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,1,8,8,8,8,8,8,8,8,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,};
return &RCSetsTable[RUSetStartTable[RegUnit]];
}
extern const MCRegisterDesc X86RegDesc[];
extern const int16_t X86RegDiffLists[];
extern const LaneBitmask X86LaneMaskLists[];
extern const char X86RegStrings[];
extern const char X86RegClassStrings[];
extern const MCPhysReg X86RegUnitRoots[][2];
extern const uint16_t X86SubRegIdxLists[];
extern const uint16_t X86RegEncodingTable[];
// X86 Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
extern const unsigned X86DwarfFlavour0Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
extern const unsigned X86DwarfFlavour1Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
extern const unsigned X86DwarfFlavour2Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
extern const unsigned X86EHFlavour0Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
extern const unsigned X86EHFlavour1Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
extern const unsigned X86EHFlavour2Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
extern const unsigned X86DwarfFlavour0L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
extern const unsigned X86DwarfFlavour1L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
extern const unsigned X86DwarfFlavour2L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
extern const unsigned X86EHFlavour0L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
extern const unsigned X86EHFlavour1L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
extern const unsigned X86EHFlavour2L2DwarfSize;
X86GenRegisterInfo::
X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
unsigned PC, unsigned HwMode)
: TargetRegisterInfo(&X86RegInfoDesc, RegisterClasses, RegisterClasses+135,
SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
LaneBitmask(0xFFFFFFFFFFFFFEF0), RegClassInfos, VTLists, HwMode) {
InitMCRegisterInfo(X86RegDesc, 392, RA, PC,
X86MCRegisterClasses, 135,
X86RegUnitRoots,
221,
X86RegDiffLists,
X86LaneMaskLists,
X86RegStrings,
X86RegClassStrings,
X86SubRegIdxLists,
13,
X86RegEncodingTable);
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
break;
case 1:
mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
break;
case 2:
mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
break;
case 1:
mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
break;
case 2:
mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
break;
}
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
break;
case 1:
mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
break;
case 2:
mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
break;
case 1:
mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
break;
case 2:
mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
break;
}
}
static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x007f807f, 0x7f800000, 0x07800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x60000000, 0x60000000, 0x60606060, 0xfff80000, 0x007fffff, 0x067fff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_NoneRegs_SaveList[] = { X86::RBP, 0 };
static const uint32_t CSR_64_NoneRegs_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0xfbfbfbfb, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfb800000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x70000000, 0x70000000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x48000000, 0x48000000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_IPRA_32_SaveList[] = { X86::EBP, X86::ESI, 0 };
static const uint32_t CSR_IPRA_32_RegMask[] = { 0x008001c0, 0xc0008201, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_IPRA_64_SaveList[] = { X86::RBP, X86::RBX, 0 };
static const uint32_t CSR_IPRA_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
static const uint32_t *const Masks[] = {
CSR_32_RegMask,
CSR_32EHRet_RegMask,
CSR_32_AllRegs_RegMask,
CSR_32_AllRegs_AVX_RegMask,
CSR_32_AllRegs_AVX512_RegMask,
CSR_32_AllRegs_SSE_RegMask,
CSR_32_RegCall_RegMask,
CSR_32_RegCall_NoSSE_RegMask,
CSR_64_RegMask,
CSR_64EHRet_RegMask,
CSR_64_AllRegs_RegMask,
CSR_64_AllRegs_AVX_RegMask,
CSR_64_AllRegs_AVX512_RegMask,
CSR_64_AllRegs_NoSSE_RegMask,
CSR_64_CXX_TLS_Darwin_PE_RegMask,
CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
CSR_64_Intel_OCL_BI_RegMask,
CSR_64_Intel_OCL_BI_AVX_RegMask,
CSR_64_Intel_OCL_BI_AVX512_RegMask,
CSR_64_MostRegs_RegMask,
CSR_64_NoneRegs_RegMask,
CSR_64_RT_AllRegs_RegMask,
CSR_64_RT_AllRegs_AVX_RegMask,
CSR_64_RT_MostRegs_RegMask,
CSR_64_SwiftError_RegMask,
CSR_64_SwiftTail_RegMask,
CSR_64_TLS_Darwin_RegMask,
CSR_IPRA_32_RegMask,
CSR_IPRA_64_RegMask,
CSR_NoRegs_RegMask,
CSR_SysV64_RegCall_RegMask,
CSR_SysV64_RegCall_NoSSE_RegMask,
CSR_Win32_CFGuard_Check_RegMask,
CSR_Win32_CFGuard_Check_NoSSE_RegMask,
CSR_Win64_RegMask,
CSR_Win64_Intel_OCL_BI_AVX_RegMask,
CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
CSR_Win64_NoSSE_RegMask,
CSR_Win64_RT_MostRegs_RegMask,
CSR_Win64_RegCall_RegMask,
CSR_Win64_RegCall_NoSSE_RegMask,
CSR_Win64_SwiftError_RegMask,
CSR_Win64_SwiftTail_RegMask,
};
return ArrayRef(Masks);
}
bool X86GenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
X86::GR64RegClass.contains(PhysReg) ||
X86::GR32RegClass.contains(PhysReg) ||
X86::GR16RegClass.contains(PhysReg) ||
X86::GR8RegClass.contains(PhysReg) ||
false;
}
bool X86GenRegisterInfo::
isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
return
X86::GR64RegClass.hasSubClassEq(RC) ||
X86::GR32RegClass.hasSubClassEq(RC) ||
X86::GR16RegClass.hasSubClassEq(RC) ||
X86::GR8RegClass.hasSubClassEq(RC) ||
false;
}
bool X86GenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
X86::DEBUG_REGRegClass.contains(PhysReg) ||
X86::CONTROL_REGRegClass.contains(PhysReg) ||
X86::CCRRegClass.contains(PhysReg) ||
X86::FPCCRRegClass.contains(PhysReg) ||
X86::DFCCRRegClass.contains(PhysReg) ||
X86::TILERegClass.contains(PhysReg) ||
X86::VK1PAIRRegClass.contains(PhysReg) ||
X86::VK2PAIRRegClass.contains(PhysReg) ||
X86::VK4PAIRRegClass.contains(PhysReg) ||
X86::VK8PAIRRegClass.contains(PhysReg) ||
X86::VK16PAIRRegClass.contains(PhysReg) ||
false;
}
bool X86GenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
false;
}
bool X86GenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
return
false;
}
ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
static const char *Names[] = {
"CSR_32",
"CSR_32EHRet",
"CSR_32_AllRegs",
"CSR_32_AllRegs_AVX",
"CSR_32_AllRegs_AVX512",
"CSR_32_AllRegs_SSE",
"CSR_32_RegCall",
"CSR_32_RegCall_NoSSE",
"CSR_64",
"CSR_64EHRet",
"CSR_64_AllRegs",
"CSR_64_AllRegs_AVX",
"CSR_64_AllRegs_AVX512",
"CSR_64_AllRegs_NoSSE",
"CSR_64_CXX_TLS_Darwin_PE",
"CSR_64_CXX_TLS_Darwin_ViaCopy",
"CSR_64_Intel_OCL_BI",
"CSR_64_Intel_OCL_BI_AVX",
"CSR_64_Intel_OCL_BI_AVX512",
"CSR_64_MostRegs",
"CSR_64_NoneRegs",
"CSR_64_RT_AllRegs",
"CSR_64_RT_AllRegs_AVX",
"CSR_64_RT_MostRegs",
"CSR_64_SwiftError",
"CSR_64_SwiftTail",
"CSR_64_TLS_Darwin",
"CSR_IPRA_32",
"CSR_IPRA_64",
"CSR_NoRegs",
"CSR_SysV64_RegCall",
"CSR_SysV64_RegCall_NoSSE",
"CSR_Win32_CFGuard_Check",
"CSR_Win32_CFGuard_Check_NoSSE",
"CSR_Win64",
"CSR_Win64_Intel_OCL_BI_AVX",
"CSR_Win64_Intel_OCL_BI_AVX512",
"CSR_Win64_NoSSE",
"CSR_Win64_RT_MostRegs",
"CSR_Win64_RegCall",
"CSR_Win64_RegCall_NoSSE",
"CSR_Win64_SwiftError",
"CSR_Win64_SwiftTail",
};
return ArrayRef(Names);
}
const X86FrameLowering *
X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
return static_cast<const X86FrameLowering *>(
MF.getSubtarget().getFrameLowering());
}
} // end namespace llvm
#endif // GET_REGINFO_TARGET_DESC
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