gistfile1.vhdl

entity exemplo is

port (

	a,b : in bit;
	c : in bit_vector (2 downto 0);
	d : buffer bit;
	e : inout std_logic_vector (3 downto 0);
	f : out bit
     );

end exemplo;


architecture arquitetura of exemplo is


	signal interno : bit_vector (4 downto 0);
	constant const : integer := 100;

begin

	


end;