mux.vhd

entity mux is
port (
    din_1 : in bit_vector (7 downto 0);
    din_2 : in bit_vector (7 downto 0);
    din_3 : in bit_vector (7 downto 0);
    din_4 : in bit_vector (7 downto 0);
    dout  : out bit_vector(7 downto 0);
    sel   : in bit_vector (1 downto 0)
    );
end mux;

architecture arch of mux is

begin

with sel select 
  dout <= din_1 when "00",
          din_2 when "01",
          din_3 when "10",
          din_4 when "11";

end arch;