Output of CLaSH CPU

CPU1_cycle.v

// Automatically generated Verilog-2001
module CPU1_cycle(ds,result);
  input [4546:0] ds;
  output [4546:0] result;
  wire [4546:0] case_alt;
  wire [4546:0] result_0;
  wire [450:0] ds1;
  wire [4546:0] case_alt_0;
  wire [4546:0] case_alt_1;
  wire [4546:0] case_alt_2;
  wire [4546:0] case_alt_3;
  wire [130:0] activity;
  wire [450:0] app_arg;
  wire [4546:0] case_alt_4;
  wire [4546:0] case_alt_5;
  wire [4546:0] case_alt_6;
  wire [4546:0] case_alt_7;
  wire [4546:0] case_alt_8;
  wire [4546:0] case_alt_9;
  wire [4546:0] case_alt_10;
  wire [450:0] app_arg_0;
  wire [450:0] app_arg_1;
  wire [4095:0] app_arg_2;
  wire [450:0] app_arg_3;
  wire [61:0] instr;
  wire [4095:0] ram;
  wire [130:0] app_arg_4;
  wire [319:0] app_arg_5;
  wire [450:0] app_arg_6;
  wire [450:0] app_arg_7;
  wire [450:0] app_arg_8;
  wire [450:0] app_arg_9;
  wire [450:0] app_arg_10;
  wire [63:0] ptr;
  wire [63:0] val;
  wire [319:0] registers;
  wire [61:0] app_arg_11;
  wire [319:0] case_alt_11;
  wire [130:0] app_arg_12;
  wire [130:0] app_arg_13;
  wire [319:0] app_arg_14;
  wire [319:0] app_arg_15;
  wire [130:0] app_arg_16;
  wire [319:0] result_1;
  wire [61:0] case_alt_12;
  wire [63:0] app_arg_17;
  wire [63:0] ds2;
  wire [63:0] ds3;
  wire [63:0] ds4;
  wire [63:0] ds5;
  wire [63:0] app_arg_18;
  wire [63:0] app_arg_19;
  wire [63:0] app_arg_20;
  wire [319:0] case_alt_13;
  wire [63:0] case_scrut;
  wire [319:0] case_alt_14;
  wire [63:0] app_arg_21;
  wire [1:0] valReg;
  wire [1:0] writeRegisterOut_app_arg;
  wire [63:0] writeRegisterOut_app_arg_0;
  wire [63:0] app_arg_22;
  wire [63:0] ds6;
  wire [63:0] case_alt_15;
  wire [63:0] case_alt_16;
  wire [63:0] case_alt_17;
  wire [63:0] app_arg_23;
  wire [63:0] case_alt_18;
  wire [319:0] case_alt_19;
  wire [63:0] case_alt_20;
  wire [65:0] tupIn;
  wire [63:0] result_2;
  wire [63:0] app_arg_24;
  wire [1:0] ptrReg;
  wire [1:0] valReg_0;
  wire [1:0] ptrReg_0;
  wire [1:0] destReg;
  wire [1:0] zeroReg;
  wire [1:0] reg_r;
  wire [1:0] sel;
  wire [63:0] sel_0;
  wire [65:0] tupIn_case_alt;
  wire [65:0] tupIn_case_alt_0;
  wire signed [63:0] app_arg_25;
  wire [4095:0] contents;
  wire [1:0] destReg_0;
  wire [65:0] tupIn_case_alt_1;
  wire [65:0] tupIn_case_alt_2;
  wire [65:0] tupIn_case_alt_3;
  wire [65:0] tupIn_case_alt_4;
  wire [63:0] tupIn_app_arg;
  wire [1:0] reg_r_0;
  wire signed [63:0] wild1;
  wire [63:0] tupIn_app_arg_0;
  wire [63:0] tupIn_app_arg_1;
  wire [63:0] tupIn_app_arg_2;
  wire [63:0] tupIn_app_arg_3;
  wire [1:0] reg_r_1;
  wire [1:0] d;
  wire [1:0] d_0;
  wire [1:0] d_1;
  wire [63:0] result_3;
  wire signed [63:0] wild1_app_arg;
  wire [63:0] tupIn_app_arg_4;
  wire [63:0] tupIn_app_arg_5;
  wire [63:0] tupIn_app_arg_6;
  wire [63:0] tupIn_app_arg_7;
  wire [63:0] tupIn_app_arg_8;
  wire [63:0] tupIn_app_arg_9;
  wire [55:0] val_0;
  wire signed [63:0] tupIn_app_arg_10;
  wire [63:0] tupIn_case_alt_5;
  wire [63:0] tupIn_case_alt_6;
  wire [63:0] tupIn_case_alt_7;
  wire [63:0] tupIn_case_alt_8;
  wire [63:0] tupIn_case_alt_9;
  wire [63:0] tupIn_case_alt_10;
  wire signed [63:0] wild1_0;
  wire [1:0] a;
  wire [1:0] b;
  wire [1:0] a_0;
  wire [1:0] b_0;
  wire [1:0] a_1;
  wire [1:0] b_1;
  wire signed [63:0] wild1_app_arg_0;
  wire [63:0] ptr_0;
  assign case_alt = result_0;
  
  reg [4546:0] result_0_reg;
  always @(*) begin
    case(activity[130:128])
      3'b000 : result_0_reg = case_alt_0;
      3'b001 : result_0_reg = case_alt_1;
      3'b010 : result_0_reg = case_alt_4;
      3'b011 : result_0_reg = case_alt_2;
      3'b100 : result_0_reg = case_alt_3;
      default : result_0_reg = case_alt_10;
    endcase
  end
  assign result_0 = result_0_reg;
  
  assign ds1 = ds[4546:4096];
  
  assign case_alt_0 = {app_arg
                      ,ram};
  
  reg [4546:0] case_alt_1_reg;
  always @(*) begin
    case(instr[61:58])
      4'b0000 : case_alt_1_reg = case_alt_4;
      4'b0001 : case_alt_1_reg = case_alt_4;
      4'b0010 : case_alt_1_reg = case_alt_4;
      4'b0011 : case_alt_1_reg = case_alt_4;
      4'b0100 : case_alt_1_reg = case_alt_5;
      4'b0101 : case_alt_1_reg = case_alt_6;
      4'b0110 : case_alt_1_reg = case_alt_7;
      4'b0111 : case_alt_1_reg = case_alt_8;
      4'b1000 : case_alt_1_reg = case_alt_9;
      default : case_alt_1_reg = case_alt_10;
    endcase
  end
  assign case_alt_1 = case_alt_1_reg;
  
  assign case_alt_2 = {app_arg_1
                      ,app_arg_2};
  
  assign case_alt_3 = {app_arg_1
                      ,ram};
  
  assign activity = ds1[450:320];
  
  assign app_arg = {app_arg_4
                   ,app_arg_5};
  
  assign case_alt_4 = {app_arg_0
                      ,ram};
  
  assign case_alt_5 = {app_arg_6
                      ,ram};
  
  assign case_alt_6 = {app_arg_7
                      ,ram};
  
  assign case_alt_7 = {app_arg_8
                      ,ram};
  
  assign case_alt_8 = {app_arg_9
                      ,ram};
  
  assign case_alt_9 = {app_arg_10
                      ,ram};
  
  assign case_alt_10 = {app_arg_3
                       ,ram};
  
  assign app_arg_0 = {{3'b000,128'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx}
                     ,result_1};
  
  assign app_arg_1 = {{3'b000,128'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx}
                     ,registers};
  
  CPU1_writeRAM CPU1_writeRAM_app_arg_2
  (.result (app_arg_2)
  ,.ds (ram)
  ,.ds1 (ptr)
  ,.val (val));
  
  assign app_arg_3 = {{3'b101,128'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx}
                     ,registers};
  
  assign instr = activity[127:66];
  
  assign ram = ds[4095:0];
  
  assign app_arg_4 = {3'b001,app_arg_11,66'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx};
  
  assign app_arg_5 = case_alt_11;
  
  assign app_arg_6 = {app_arg_12
                     ,registers};
  
  assign app_arg_7 = {app_arg_13
                     ,registers};
  
  assign app_arg_8 = {{3'b000,128'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx}
                     ,app_arg_14};
  
  assign app_arg_9 = {{3'b000,128'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx}
                     ,app_arg_15};
  
  assign app_arg_10 = {app_arg_16
                      ,registers};
  
  assign ptr = activity[127:64];
  
  assign val = activity[63:0];
  
  assign registers = ds1[319:0];
  
  assign app_arg_11 = case_alt_12;
  
  assign case_alt_11 = {ds2
                       ,ds3
                       ,ds4
                       ,ds5
                       ,app_arg_17};
  
  assign app_arg_12 = {3'b010,app_arg_18,valReg,62'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx};
  
  assign app_arg_13 = {3'b011,app_arg_19,app_arg_20};
  
  assign app_arg_14 = case_alt_13;
  
  reg [319:0] app_arg_15_reg;
  always @(*) begin
    case(case_scrut)
      64'd0 : app_arg_15_reg = case_alt_14;
      default : app_arg_15_reg = registers;
    endcase
  end
  assign app_arg_15 = app_arg_15_reg;
  
  assign app_arg_16 = {3'b100,app_arg_21,64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx};
  
  CPU1_writeRegister CPU1_writeRegister_result_1
  (.result (result_1)
  ,.regs (registers)
  ,.reg_r (writeRegisterOut_app_arg)
  ,.word (writeRegisterOut_app_arg_0));
  
  CPU1_decodeInstruction CPU1_decodeInstruction_case_alt_12
  (.result (case_alt_12)
  ,.ds (app_arg_22));
  
  assign app_arg_17 = ds6 + 64'd1;
  
  assign ds2 = registers[319:256];
  
  assign ds3 = registers[255:192];
  
  assign ds4 = registers[191:128];
  
  assign ds5 = registers[127:64];
  
  assign app_arg_18 = case_alt_15;
  
  assign app_arg_19 = case_alt_16;
  
  assign app_arg_20 = case_alt_17;
  
  assign case_alt_13 = {ds2
                       ,ds3
                       ,ds4
                       ,ds5
                       ,app_arg_23};
  
  assign case_scrut = case_alt_18;
  
  assign case_alt_14 = case_alt_19;
  
  assign app_arg_21 = case_alt_20;
  
  assign valReg = instr[57:56];
  
  assign writeRegisterOut_app_arg = sel;
  
  assign writeRegisterOut_app_arg_0 = sel_0;
  
  assign app_arg_22 = result_2;
  
  assign ds6 = registers[63:0];
  
  reg [63:0] case_alt_15_reg;
  always @(*) begin
    case(ptrReg)
      2'b00 : case_alt_15_reg = ds2;
      2'b01 : case_alt_15_reg = ds3;
      2'b10 : case_alt_15_reg = ds4;
      default : case_alt_15_reg = ds5;
    endcase
  end
  assign case_alt_15 = case_alt_15_reg;
  
  reg [63:0] case_alt_16_reg;
  always @(*) begin
    case(ptrReg_0)
      2'b00 : case_alt_16_reg = ds2;
      2'b01 : case_alt_16_reg = ds3;
      2'b10 : case_alt_16_reg = ds4;
      default : case_alt_16_reg = ds5;
    endcase
  end
  assign case_alt_16 = case_alt_16_reg;
  
  reg [63:0] case_alt_17_reg;
  always @(*) begin
    case(valReg_0)
      2'b00 : case_alt_17_reg = ds2;
      2'b01 : case_alt_17_reg = ds3;
      2'b10 : case_alt_17_reg = ds4;
      default : case_alt_17_reg = ds5;
    endcase
  end
  assign case_alt_17 = case_alt_17_reg;
  
  reg [63:0] app_arg_23_reg;
  always @(*) begin
    case(destReg)
      2'b00 : app_arg_23_reg = ds2;
      2'b01 : app_arg_23_reg = ds3;
      2'b10 : app_arg_23_reg = ds4;
      default : app_arg_23_reg = ds5;
    endcase
  end
  assign app_arg_23 = app_arg_23_reg;
  
  reg [63:0] case_alt_18_reg;
  always @(*) begin
    case(zeroReg)
      2'b00 : case_alt_18_reg = ds2;
      2'b01 : case_alt_18_reg = ds3;
      2'b10 : case_alt_18_reg = ds4;
      default : case_alt_18_reg = ds5;
    endcase
  end
  assign case_alt_18 = case_alt_18_reg;
  
  assign case_alt_19 = {ds2
                       ,ds3
                       ,ds4
                       ,ds5
                       ,app_arg_24};
  
  reg [63:0] case_alt_20_reg;
  always @(*) begin
    case(reg_r)
      2'b00 : case_alt_20_reg = ds2;
      2'b01 : case_alt_20_reg = ds3;
      2'b10 : case_alt_20_reg = ds4;
      default : case_alt_20_reg = ds5;
    endcase
  end
  assign case_alt_20 = case_alt_20_reg;
  
  reg [65:0] tupIn_reg;
  always @(*) begin
    case(activity[130:128])
      3'b001 : tupIn_reg = tupIn_case_alt;
      default : tupIn_reg = tupIn_case_alt_0;
    endcase
  end
  assign tupIn = tupIn_reg;
  
  // indexVec begin
  wire [63:0] vec [0:64-1];
  
  wire [4095:0] vecflat;
  assign vecflat = contents;
  genvar i;
  generate
  for (i=0; i < 64; i=i+1) begin : mk_array
    assign vec[(64-1)-i] = vecflat[i*64+:64];
  end
  endgenerate
  
  assign result_2 = vec[app_arg_25];
  // indexVec end
  
  reg [63:0] app_arg_24_reg;
  always @(*) begin
    case(destReg_0)
      2'b00 : app_arg_24_reg = ds2;
      2'b01 : app_arg_24_reg = ds3;
      2'b10 : app_arg_24_reg = ds4;
      default : app_arg_24_reg = ds5;
    endcase
  end
  assign app_arg_24 = app_arg_24_reg;
  
  assign ptrReg = instr[55:54];
  
  assign valReg_0 = instr[57:56];
  
  assign ptrReg_0 = instr[55:54];
  
  assign destReg = instr[57:56];
  
  assign zeroReg = instr[57:56];
  
  assign reg_r = instr[57:56];
  
  assign sel = tupIn[65:64];
  
  assign sel_0 = tupIn[63:0];
  
  reg [65:0] tupIn_case_alt_reg;
  always @(*) begin
    case(instr[61:58])
      4'b0000 : tupIn_case_alt_reg = tupIn_case_alt_1;
      4'b0001 : tupIn_case_alt_reg = tupIn_case_alt_2;
      4'b0010 : tupIn_case_alt_reg = tupIn_case_alt_3;
      default : tupIn_case_alt_reg = tupIn_case_alt_4;
    endcase
  end
  assign tupIn_case_alt = tupIn_case_alt_reg;
  
  assign tupIn_case_alt_0 = {reg_r_0
                            ,tupIn_app_arg};
  
  assign app_arg_25 = wild1;
  
  assign contents = ram;
  
  assign destReg_0 = instr[55:54];
  
  assign tupIn_case_alt_1 = {reg_r_1
                            ,tupIn_app_arg_0};
  
  assign tupIn_case_alt_2 = {d
                            ,tupIn_app_arg_1};
  
  assign tupIn_case_alt_3 = {d_0
                            ,tupIn_app_arg_2};
  
  assign tupIn_case_alt_4 = {d_1
                            ,tupIn_app_arg_3};
  
  assign tupIn_app_arg = result_3;
  
  assign reg_r_0 = activity[63:62];
  
  assign wild1 = $signed(wild1_app_arg);
  
  assign tupIn_app_arg_0 = $unsigned(val_0);
  
  assign tupIn_app_arg_1 = tupIn_app_arg_4 + tupIn_app_arg_5;
  
  assign tupIn_app_arg_2 = tupIn_app_arg_6 - tupIn_app_arg_7;
  
  assign tupIn_app_arg_3 = tupIn_app_arg_8 * tupIn_app_arg_9;
  
  assign reg_r_1 = instr[57:56];
  
  assign d = instr[53:52];
  
  assign d_0 = instr[53:52];
  
  assign d_1 = instr[53:52];
  
  // indexVec begin
  wire [63:0] vec_0 [0:64-1];
  
  wire [4095:0] vecflat_0;
  assign vecflat_0 = contents;
  genvar i_0;
  generate
  for (i_0=0; i_0 < 64; i_0=i_0+1) begin : mk_array_0
    assign vec_0[(64-1)-i_0] = vecflat_0[i_0*64+:64];
  end
  endgenerate
  
  assign result_3 = vec_0[tupIn_app_arg_10];
  // indexVec end
  
  assign wild1_app_arg = $unsigned(ds6);
  
  assign tupIn_app_arg_4 = tupIn_case_alt_5;
  
  assign tupIn_app_arg_5 = tupIn_case_alt_6;
  
  assign tupIn_app_arg_6 = tupIn_case_alt_7;
  
  assign tupIn_app_arg_7 = tupIn_case_alt_8;
  
  assign tupIn_app_arg_8 = tupIn_case_alt_9;
  
  assign tupIn_app_arg_9 = tupIn_case_alt_10;
  
  assign val_0 = instr[55:0];
  
  assign tupIn_app_arg_10 = wild1_0;
  
  reg [63:0] tupIn_case_alt_5_reg;
  always @(*) begin
    case(a)
      2'b00 : tupIn_case_alt_5_reg = ds2;
      2'b01 : tupIn_case_alt_5_reg = ds3;
      2'b10 : tupIn_case_alt_5_reg = ds4;
      default : tupIn_case_alt_5_reg = ds5;
    endcase
  end
  assign tupIn_case_alt_5 = tupIn_case_alt_5_reg;
  
  reg [63:0] tupIn_case_alt_6_reg;
  always @(*) begin
    case(b)
      2'b00 : tupIn_case_alt_6_reg = ds2;
      2'b01 : tupIn_case_alt_6_reg = ds3;
      2'b10 : tupIn_case_alt_6_reg = ds4;
      default : tupIn_case_alt_6_reg = ds5;
    endcase
  end
  assign tupIn_case_alt_6 = tupIn_case_alt_6_reg;
  
  reg [63:0] tupIn_case_alt_7_reg;
  always @(*) begin
    case(a_0)
      2'b00 : tupIn_case_alt_7_reg = ds2;
      2'b01 : tupIn_case_alt_7_reg = ds3;
      2'b10 : tupIn_case_alt_7_reg = ds4;
      default : tupIn_case_alt_7_reg = ds5;
    endcase
  end
  assign tupIn_case_alt_7 = tupIn_case_alt_7_reg;
  
  reg [63:0] tupIn_case_alt_8_reg;
  always @(*) begin
    case(b_0)
      2'b00 : tupIn_case_alt_8_reg = ds2;
      2'b01 : tupIn_case_alt_8_reg = ds3;
      2'b10 : tupIn_case_alt_8_reg = ds4;
      default : tupIn_case_alt_8_reg = ds5;
    endcase
  end
  assign tupIn_case_alt_8 = tupIn_case_alt_8_reg;
  
  reg [63:0] tupIn_case_alt_9_reg;
  always @(*) begin
    case(a_1)
      2'b00 : tupIn_case_alt_9_reg = ds2;
      2'b01 : tupIn_case_alt_9_reg = ds3;
      2'b10 : tupIn_case_alt_9_reg = ds4;
      default : tupIn_case_alt_9_reg = ds5;
    endcase
  end
  assign tupIn_case_alt_9 = tupIn_case_alt_9_reg;
  
  reg [63:0] tupIn_case_alt_10_reg;
  always @(*) begin
    case(b_1)
      2'b00 : tupIn_case_alt_10_reg = ds2;
      2'b01 : tupIn_case_alt_10_reg = ds3;
      2'b10 : tupIn_case_alt_10_reg = ds4;
      default : tupIn_case_alt_10_reg = ds5;
    endcase
  end
  assign tupIn_case_alt_10 = tupIn_case_alt_10_reg;
  
  assign wild1_0 = $signed(wild1_app_arg_0);
  
  assign a = instr[57:56];
  
  assign b = instr[55:54];
  
  assign a_0 = instr[57:56];
  
  assign b_0 = instr[55:54];
  
  assign a_1 = instr[57:56];
  
  assign b_1 = instr[55:54];
  
  assign wild1_app_arg_0 = $unsigned(ptr_0);
  
  assign ptr_0 = activity[127:64];
  
  assign result = case_alt;
endmodule