mux.vhdl

entity MUX1 is
	port(E0, E1, E2, E3 : in bit;
		SEL : in bit_vector(1 downto 0);
		S : out bit);
end MUX1;

architecture COMPOR_MUX1 of MUX1 is
begin
	process
	begin
		case SEL is
			when "00" => S <= E0;
			when "01" => S <= E1;
			when "10" => S <= E2;
			when "11" => S <= E3;
		end case;
		wait on SEL, E0, E1, E2, E3;
	end process;
end COMPOR_MUX1;

mux_tb.vhdl

entity mux_tb is
end mux_tb;

architecture behaviour of mux_tb is
	component mux1
		port(E0, E1, E2, E3 : in bit;
			SEL : in bit_vector(1 downto 0);
			S : out bit);
	end component;

    for mux_0 : mux1 use entity work.MUX1;
	signal E0, E1, E2, E3, S : bit; 
    signal SEL : bit_vector(1 downto 0);
begin
	mux_0 : mux1 port map(
                            E0 => E0,
                            E1 => E1,
                            E2 => E2,
                            E3 => E3,
                            SEL => SEL,
                            S => S
                        );

	process
        type pattern_type is record
            sel : bit_vector(1 downto 0); 	-- selection vector
            e0, e1, e2, e3 : bit; 		    -- inputs
            s : bit;        	            -- output
        end record;
        type pattern_array is array (natural range <>) of pattern_type;
        constant patterns : pattern_array :=
            (("00",'0','0','0','0','0'),
             ("00",'1','0','0','0','1'),
             ("01",'0','0','0','0','0'),
             ("01",'0','1','0','0','1'),
             ("10",'0','0','0','0','0'),
             ("10",'0','0','1','0','1'),
             ("11",'0','0','0','0','0'),
             ("11",'0','0','0','1','1'));
	begin
		for i in patterns'range loop
			-- set inputs
            E0 <= patterns(i).e0;
            E1 <= patterns(i).e1;
            E2 <= patterns(i).e2;
            E3 <= patterns(i).e3;
            SEL <= patterns(i).sel;

            wait for 1 ns;

            -- check outputs
            assert S = patterns(i).s
                report "bad output" severity error;
        end loop;
	assert false report "end of test" severity note;
        wait;
    end process;
end behaviour;