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matthijskooijman/gist:e0268c9d222aa72001f0

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gistfile1.asm
bootloader.elf: file format elf32-avr
Disassembly of section .text:
0003e000 <__vectors>:
3e000: 99 c0 rjmp .+306 ; 0x3e134 <__ctors_end>
3e002: 00 00 nop
3e004: aa c0 rjmp .+340 ; 0x3e15a <__bad_interrupt>
3e006: 00 00 nop
3e008: a8 c0 rjmp .+336 ; 0x3e15a <__bad_interrupt>
3e00a: 00 00 nop
3e00c: a6 c0 rjmp .+332 ; 0x3e15a <__bad_interrupt>
3e00e: 00 00 nop
3e010: a4 c0 rjmp .+328 ; 0x3e15a <__bad_interrupt>
3e012: 00 00 nop
3e014: a2 c0 rjmp .+324 ; 0x3e15a <__bad_interrupt>
3e016: 00 00 nop
3e018: a0 c0 rjmp .+320 ; 0x3e15a <__bad_interrupt>
3e01a: 00 00 nop
3e01c: 9e c0 rjmp .+316 ; 0x3e15a <__bad_interrupt>
3e01e: 00 00 nop
3e020: 9c c0 rjmp .+312 ; 0x3e15a <__bad_interrupt>
3e022: 00 00 nop
3e024: 9a c0 rjmp .+308 ; 0x3e15a <__bad_interrupt>
3e026: 00 00 nop
3e028: 98 c0 rjmp .+304 ; 0x3e15a <__bad_interrupt>
3e02a: 00 00 nop
3e02c: 96 c0 rjmp .+300 ; 0x3e15a <__bad_interrupt>
3e02e: 00 00 nop
3e030: 94 c0 rjmp .+296 ; 0x3e15a <__bad_interrupt>
3e032: 00 00 nop
3e034: 92 c0 rjmp .+292 ; 0x3e15a <__bad_interrupt>
3e036: 00 00 nop
3e038: 90 c0 rjmp .+288 ; 0x3e15a <__bad_interrupt>
3e03a: 00 00 nop
3e03c: 8e c0 rjmp .+284 ; 0x3e15a <__bad_interrupt>
3e03e: 00 00 nop
3e040: 8c c0 rjmp .+280 ; 0x3e15a <__bad_interrupt>
3e042: 00 00 nop
3e044: 8a c0 rjmp .+276 ; 0x3e15a <__bad_interrupt>
3e046: 00 00 nop
3e048: 88 c0 rjmp .+272 ; 0x3e15a <__bad_interrupt>
3e04a: 00 00 nop
3e04c: 86 c0 rjmp .+268 ; 0x3e15a <__bad_interrupt>
3e04e: 00 00 nop
3e050: 84 c0 rjmp .+264 ; 0x3e15a <__bad_interrupt>
3e052: 00 00 nop
3e054: 82 c0 rjmp .+260 ; 0x3e15a <__bad_interrupt>
3e056: 00 00 nop
3e058: 80 c0 rjmp .+256 ; 0x3e15a <__bad_interrupt>
3e05a: 00 00 nop
3e05c: 7e c0 rjmp .+252 ; 0x3e15a <__bad_interrupt>
3e05e: 00 00 nop
3e060: 7c c0 rjmp .+248 ; 0x3e15a <__bad_interrupt>
3e062: 00 00 nop
3e064: 7a c0 rjmp .+244 ; 0x3e15a <__bad_interrupt>
3e066: 00 00 nop
3e068: 78 c0 rjmp .+240 ; 0x3e15a <__bad_interrupt>
3e06a: 00 00 nop
3e06c: 76 c0 rjmp .+236 ; 0x3e15a <__bad_interrupt>
3e06e: 00 00 nop
3e070: 74 c0 rjmp .+232 ; 0x3e15a <__bad_interrupt>
3e072: 00 00 nop
3e074: 72 c0 rjmp .+228 ; 0x3e15a <__bad_interrupt>
3e076: 00 00 nop
3e078: 70 c0 rjmp .+224 ; 0x3e15a <__bad_interrupt>
3e07a: 00 00 nop
3e07c: 6e c0 rjmp .+220 ; 0x3e15a <__bad_interrupt>
3e07e: 00 00 nop
3e080: 6c c0 rjmp .+216 ; 0x3e15a <__bad_interrupt>
3e082: 00 00 nop
3e084: 6a c0 rjmp .+212 ; 0x3e15a <__bad_interrupt>
3e086: 00 00 nop
3e088: 68 c0 rjmp .+208 ; 0x3e15a <__bad_interrupt>
3e08a: 00 00 nop
3e08c: 66 c0 rjmp .+204 ; 0x3e15a <__bad_interrupt>
3e08e: 00 00 nop
3e090: 64 c0 rjmp .+200 ; 0x3e15a <__bad_interrupt>
3e092: 00 00 nop
3e094: 62 c0 rjmp .+196 ; 0x3e15a <__bad_interrupt>
3e096: 00 00 nop
3e098: 60 c0 rjmp .+192 ; 0x3e15a <__bad_interrupt>
3e09a: 00 00 nop
3e09c: 5e c0 rjmp .+188 ; 0x3e15a <__bad_interrupt>
3e09e: 00 00 nop
3e0a0: 5c c0 rjmp .+184 ; 0x3e15a <__bad_interrupt>
3e0a2: 00 00 nop
3e0a4: 5a c0 rjmp .+180 ; 0x3e15a <__bad_interrupt>
3e0a6: 00 00 nop
3e0a8: 58 c0 rjmp .+176 ; 0x3e15a <__bad_interrupt>
3e0aa: 00 00 nop
3e0ac: 56 c0 rjmp .+172 ; 0x3e15a <__bad_interrupt>
3e0ae: 00 00 nop
3e0b0: 54 c0 rjmp .+168 ; 0x3e15a <__bad_interrupt>
3e0b2: 00 00 nop
3e0b4: 52 c0 rjmp .+164 ; 0x3e15a <__bad_interrupt>
3e0b6: 00 00 nop
3e0b8: 50 c0 rjmp .+160 ; 0x3e15a <__bad_interrupt>
3e0ba: 00 00 nop
3e0bc: 4e c0 rjmp .+156 ; 0x3e15a <__bad_interrupt>
3e0be: 00 00 nop
3e0c0: 4c c0 rjmp .+152 ; 0x3e15a <__bad_interrupt>
3e0c2: 00 00 nop
3e0c4: 4a c0 rjmp .+148 ; 0x3e15a <__bad_interrupt>
3e0c6: 00 00 nop
3e0c8: 48 c0 rjmp .+144 ; 0x3e15a <__bad_interrupt>
3e0ca: 00 00 nop
3e0cc: 46 c0 rjmp .+140 ; 0x3e15a <__bad_interrupt>
3e0ce: 00 00 nop
3e0d0: 44 c0 rjmp .+136 ; 0x3e15a <__bad_interrupt>
3e0d2: 00 00 nop
3e0d4: 42 c0 rjmp .+132 ; 0x3e15a <__bad_interrupt>
3e0d6: 00 00 nop
3e0d8: 40 c0 rjmp .+128 ; 0x3e15a <__bad_interrupt>
3e0da: 00 00 nop
3e0dc: 3e c0 rjmp .+124 ; 0x3e15a <__bad_interrupt>
3e0de: 00 00 nop
3e0e0: 3c c0 rjmp .+120 ; 0x3e15a <__bad_interrupt>
3e0e2: 00 00 nop
3e0e4: 3a c0 rjmp .+116 ; 0x3e15a <__bad_interrupt>
3e0e6: 00 00 nop
3e0e8: 38 c0 rjmp .+112 ; 0x3e15a <__bad_interrupt>
3e0ea: 00 00 nop
3e0ec: 36 c0 rjmp .+108 ; 0x3e15a <__bad_interrupt>
3e0ee: 00 00 nop
3e0f0: 34 c0 rjmp .+104 ; 0x3e15a <__bad_interrupt>
3e0f2: 00 00 nop
3e0f4: 32 c0 rjmp .+100 ; 0x3e15a <__bad_interrupt>
3e0f6: 00 00 nop
3e0f8: 30 c0 rjmp .+96 ; 0x3e15a <__bad_interrupt>
3e0fa: 00 00 nop
3e0fc: 2e c0 rjmp .+92 ; 0x3e15a <__bad_interrupt>
3e0fe: 00 00 nop
3e100: 2c c0 rjmp .+88 ; 0x3e15a <__bad_interrupt>
3e102: 00 00 nop
3e104: 2a c0 rjmp .+84 ; 0x3e15a <__bad_interrupt>
3e106: 00 00 nop
3e108: 28 c0 rjmp .+80 ; 0x3e15a <__bad_interrupt>
3e10a: 00 00 nop
3e10c: 26 c0 rjmp .+76 ; 0x3e15a <__bad_interrupt>
3e10e: 00 00 nop
3e110: 24 c0 rjmp .+72 ; 0x3e15a <__bad_interrupt>
3e112: 00 00 nop
3e114: 22 c0 rjmp .+68 ; 0x3e15a <__bad_interrupt>
3e116: 00 00 nop
3e118: 20 c0 rjmp .+64 ; 0x3e15a <__bad_interrupt>
3e11a: 00 00 nop
3e11c: 1e c0 rjmp .+60 ; 0x3e15a <__bad_interrupt>
3e11e: 00 00 nop
3e120: 1c c0 rjmp .+56 ; 0x3e15a <__bad_interrupt>
3e122: 00 00 nop
3e124: 1a c0 rjmp .+52 ; 0x3e15a <__bad_interrupt>
3e126: 00 00 nop
3e128: 18 c0 rjmp .+48 ; 0x3e15a <__bad_interrupt>
3e12a: 00 00 nop
3e12c: 16 c0 rjmp .+44 ; 0x3e15a <__bad_interrupt>
3e12e: 00 00 nop
3e130: 14 c0 rjmp .+40 ; 0x3e15a <__bad_interrupt>
...
0003e134 <__ctors_end>:
3e134: 11 24 eor r1, r1
3e136: 1f be out 0x3f, r1 ; 63
3e138: cf ef ldi r28, 0xFF ; 255
3e13a: d1 e8 ldi r29, 0x81 ; 129
3e13c: de bf out 0x3e, r29 ; 62
3e13e: cd bf out 0x3d, r28 ; 61
3e140: 01 e0 ldi r16, 0x01 ; 1
3e142: 0c bf out 0x3c, r16 ; 60
3e144: 0b d0 rcall .+22 ; 0x3e15c <main>
3e146: 65 c0 rjmp .+202 ; 0x3e212 <_exit>
0003e148 <__jumpMain>:
asm volatile ( ".set __stack, %0" :: "i" (RAMEND) );
// set stack pointer to top of RAM
asm volatile ( "ldi 16, %0" :: "i" (RAMEND >> 8) );
3e148: 01 e8 ldi r16, 0x81 ; 129
asm volatile ( "out %0,16" :: "i" (AVR_STACK_POINTER_HI_ADDR) );
3e14a: 0e bf out 0x3e, r16 ; 62
asm volatile ( "ldi 16, %0" :: "i" (RAMEND & 0x0ff) );
3e14c: 0f ef ldi r16, 0xFF ; 255
asm volatile ( "out %0,16" :: "i" (AVR_STACK_POINTER_LO_ADDR) );
3e14e: 0d bf out 0x3d, r16 ; 61
asm volatile ( "clr __zero_reg__" ); // GCC depends on register r1 set to 0
3e150: 11 24 eor r1, r1
asm volatile ( "out %0, __zero_reg__" :: "I" (_SFR_IO_ADDR(SREG)) ); // set SREG to 0
3e152: 1f be out 0x3f, r1 ; 63
asm volatile ( "jmp main"); // jump to main()
3e154: 03 c0 rjmp .+6 ; 0x3e15c <main>
asm volatile ( "jmp 0x3e000"); // jump to main()
3e156: 0d 94 00 f0 jmp 0x3e000 ; 0x3e000 <__vectors>
0003e15a <__bad_interrupt>:
}
3e15a: 52 cf rjmp .-348 ; 0x3e000 <__vectors>
0003e15c <main>:
//*****************************************************************************/
int main(void)
{
// Setup some pins as outputs. PORTB has active low leds, PORTE is for
// logic analyzer outputs
DDRB |= (1 << PB4) | (1 << PB5) | (1 << PB6);
3e15c: 84 b1 in r24, 0x04 ; 4
3e15e: 80 67 ori r24, 0x70 ; 112
3e160: 84 b9 out 0x04, r24 ; 4
DDRE |= (1 << PE2) | (1 << PE3) | (1 << PE4) | (1 << PE5) | (1 << PE6);
3e162: 8d b1 in r24, 0x0d ; 13
3e164: 8c 67 ori r24, 0x7C ; 124
3e166: 8d b9 out 0x0d, r24 ; 13
if (!MCUSR) {
3e168: 84 b7 in r24, 0x34 ; 52
3e16a: 81 11 cpse r24, r1
3e16c: 03 c0 rjmp .+6 ; 0x3e174 <main+0x18>
// If we get here, we "reset" without a proper hardware reset. This
// should never happen.
PORTB &= ~(1 << PB6);
3e16e: 2e 98 cbi 0x05, 6 ; 5
PORTE |= (1 << PE3);
3e170: 73 9a sbi 0x0e, 3 ; 14
3e172: ff cf rjmp .-2 ; 0x3e172 <main+0x16>
while(1);
} else {
// Normal startup: Turn off leds (active low), provide trigger to
// analyzer
PORTB |= (1 << PB4) | (1 << PB5) | (1 << PB6);
3e174: 85 b1 in r24, 0x05 ; 5
3e176: 80 67 ori r24, 0x70 ; 112
3e178: 85 b9 out 0x05, r24 ; 5
PORTE |= (1 << PE2);
3e17a: 72 9a sbi 0x0e, 2 ; 14
}
MCUSR = 0;
3e17c: 14 be out 0x34, r1 ; 52
// Write fixed data to the second half of flash
uint32_t address = (FLASHEND + 1) / 2;
3e17e: 80 e0 ldi r24, 0x00 ; 0
3e180: 90 e0 ldi r25, 0x00 ; 0
3e182: a2 e0 ldi r26, 0x02 ; 2
3e184: b0 e0 ldi r27, 0x00 ; 0
for(;;) {
// Erase
PORTB &= ~(1 << PB4);
PORTE &= ~(1 << PE4);
boot_page_erase(address); // Perform page erase
3e186: 13 e0 ldi r17, 0x03 ; 3
uint32_t tempAddress = address;
unsigned int size = SPM_PAGESIZE;
do {
//uint8_t data = 0xcfff; // rjmp .-2
uint8_t data = 0x0000; // nop
boot_page_fill(tempAddress,data);
3e188: 01 e0 ldi r16, 0x01 ; 1
3e18a: 20 e0 ldi r18, 0x00 ; 0
3e18c: 30 e0 ldi r19, 0x00 ; 0
size -= 2; // Reduce number of bytes to write by two
} while (size); // Loop until all bytes written
PORTE &= ~(1 << PE5);
PORTB &= ~(1 << PB5);
boot_page_write(address);
3e18e: 45 e0 ldi r20, 0x05 ; 5
3e190: f4 2e mov r15, r20
// Write fixed data to the second half of flash
uint32_t address = (FLASHEND + 1) / 2;
for(;;) {
// Erase
PORTB &= ~(1 << PB4);
3e192: 2c 98 cbi 0x05, 4 ; 5
PORTE &= ~(1 << PE4);
3e194: 74 98 cbi 0x0e, 4 ; 14
boot_page_erase(address); // Perform page erase
3e196: fc 01 movw r30, r24
3e198: a0 93 5b 00 sts 0x005B, r26
3e19c: 10 93 57 00 sts 0x0057, r17
3e1a0: e8 95 spm
boot_spm_busy_wait(); // Wait until the memory is erased.
3e1a2: 07 b6 in r0, 0x37 ; 55
3e1a4: 00 fc sbrc r0, 0
3e1a6: fd cf rjmp .-6 ; 0x3e1a2 <main+0x46>
PORTE |= (1 << PE4);
3e1a8: 74 9a sbi 0x0e, 4 ; 14
PORTB |= (1 << PB4);
3e1aa: 2c 9a sbi 0x05, 4 ; 5
3e1ac: ac 01 movw r20, r24
3e1ae: bd 01 movw r22, r26
// Write
uint32_t tempAddress = address;
unsigned int size = SPM_PAGESIZE;
3e1b0: c0 e0 ldi r28, 0x00 ; 0
3e1b2: d1 e0 ldi r29, 0x01 ; 1
do {
//uint8_t data = 0xcfff; // rjmp .-2
uint8_t data = 0x0000; // nop
boot_page_fill(tempAddress,data);
3e1b4: 09 01 movw r0, r18
3e1b6: fa 01 movw r30, r20
3e1b8: 60 93 5b 00 sts 0x005B, r22
3e1bc: 00 93 57 00 sts 0x0057, r16
3e1c0: e8 95 spm
3e1c2: 11 24 eor r1, r1
tempAddress = tempAddress + 2; // Select next word in memory
3e1c4: 4e 5f subi r20, 0xFE ; 254
3e1c6: 5f 4f sbci r21, 0xFF ; 255
3e1c8: 6f 4f sbci r22, 0xFF ; 255
3e1ca: 7f 4f sbci r23, 0xFF ; 255
size -= 2; // Reduce number of bytes to write by two
3e1cc: 22 97 sbiw r28, 0x02 ; 2
} while (size); // Loop until all bytes written
3e1ce: 20 97 sbiw r28, 0x00 ; 0
3e1d0: 89 f7 brne .-30 ; 0x3e1b4 <main+0x58>
PORTE &= ~(1 << PE5);
3e1d2: 75 98 cbi 0x0e, 5 ; 14
PORTB &= ~(1 << PB5);
3e1d4: 2d 98 cbi 0x05, 5 ; 5
boot_page_write(address);
3e1d6: fc 01 movw r30, r24
3e1d8: a0 93 5b 00 sts 0x005B, r26
3e1dc: f0 92 57 00 sts 0x0057, r15
3e1e0: e8 95 spm
boot_spm_busy_wait();
3e1e2: 07 b6 in r0, 0x37 ; 55
3e1e4: 00 fc sbrc r0, 0
3e1e6: fd cf rjmp .-6 ; 0x3e1e2 <main+0x86>
PORTE |= (1 << PE5);
3e1e8: 75 9a sbi 0x0e, 5 ; 14
PORTB |= (1 << PB5);
3e1ea: 2d 9a sbi 0x05, 5 ; 5
// Wrap around from APP_END to halfway
// FLASHEND
address += SPM_PAGESIZE;
if (address + SPM_PAGESIZE > APP_END + 1)
3e1ec: ac 01 movw r20, r24
3e1ee: bd 01 movw r22, r26
3e1f0: 5e 5f subi r21, 0xFE ; 254
3e1f2: 6f 4f sbci r22, 0xFF ; 255
3e1f4: 7f 4f sbci r23, 0xFF ; 255
3e1f6: 42 30 cpi r20, 0x02 ; 2
3e1f8: 50 4e sbci r21, 0xE0 ; 224
3e1fa: 63 40 sbci r22, 0x03 ; 3
3e1fc: 71 05 cpc r23, r1
3e1fe: 20 f4 brcc .+8 ; 0x3e208 <main+0xac>
PORTE |= (1 << PE5);
PORTB |= (1 << PB5);
// Wrap around from APP_END to halfway
// FLASHEND
address += SPM_PAGESIZE;
3e200: 9f 5f subi r25, 0xFF ; 255
3e202: af 4f sbci r26, 0xFF ; 255
3e204: bf 4f sbci r27, 0xFF ; 255
3e206: c5 cf rjmp .-118 ; 0x3e192 <main+0x36>
if (address + SPM_PAGESIZE > APP_END + 1)
address = (FLASHEND + 1) / 2;
3e208: 80 e0 ldi r24, 0x00 ; 0
3e20a: 90 e0 ldi r25, 0x00 ; 0
3e20c: a2 e0 ldi r26, 0x02 ; 2
3e20e: b0 e0 ldi r27, 0x00 ; 0
3e210: c0 cf rjmp .-128 ; 0x3e192 <main+0x36>
0003e212 <_exit>:
3e212: f8 94 cli
0003e214 <__stop_program>:
3e214: ff cf rjmp .-2 ; 0x3e214 <__stop_program>
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