half_adder SystemVerilog

half_adder.sv

module half_adder(
    input clk,
    a,
    b,
    output reg sum,
    carry
);
    always @(posedge clk)
        begin
            sum <= a ^ b;
            carry <= a & b;
        end
endmodule

module test_half_adder;
    reg clk = 0;
    always #1 clk = !clk;

    wire a = 0,
         b = 0;
    reg  sum = 0,
         carry = 0;

    half_adder ha(clk, a, b, sum, carry);

    initial
        $monitor(
            "Time: %t, clk: %0d, a: %0d, b: %0d, sum: %0d, carry: %0d",
            $time,
            clk,
            a,
            b,
            sum,
            carry
        );
endmodule

Basing my source from an iverilog tutorial.

https://iverilog.fandom.com/wiki/Getting_Started