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@melsov
Created April 9, 2018 11:47
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module mojo_top (
input clk, // 50MHz clock
input rst_n, // reset button (active low)
output led [8], // 8 user controllable LEDs
input cclk, // configuration clock, AVR ready when high
output spi_miso, // AVR SPI MISO
input spi_ss, // AVR SPI Slave Select
input spi_mosi, // AVR SPI MOSI
input spi_sck, // AVR SPI Clock
output spi_channel [4], // AVR general purpose pins (used by default to select ADC channel)
input avr_tx, // AVR TX (FPGA RX)
output avr_rx, // AVR RX (FPGA TX)
input avr_rx_busy, // AVR RX buffer full
inout hdmi1_sda,
input hdmi1_scl,
output hdmi1_tmds[4],
output hdmi1_tmdsb[4]
//output hdmi2_tmds[4],
//output hdmi2_tmdsb[4]
) {
sig rst; // reset signal
clk_gen clk_gen(.CLK_IN(clk));
hdmi_encoder hdmi (.clk(clk_gen.CLK_OUT), .rst(rst));
.clk(hdmi.pclk) {
// The reset conditioner is used to synchronize the reset signal to the FPGA
// clock. This ensures the entire FPGA comes out of reset at the same time.
reset_conditioner reset_cond;
.rst(rst){
// the avr_interface module is used to talk to the AVR for access to the USB port and analog pins
avr_interface avr;
edid_rom edid_rom(.sda(hdmi1_sda), .scl(hdmi1_scl));
dff ctr[64];
}
}
always {
reset_cond.in = ~rst_n; // input raw inverted reset signal
rst = reset_cond.out; // conditioned reset
// connect inputs of avr
avr.cclk = cclk;
avr.spi_ss = spi_ss;
avr.spi_mosi = spi_mosi;
avr.spi_sck = spi_sck;
avr.rx = avr_tx;
avr.channel = hf; // ADC is unused so disable
avr.tx_block = avr_rx_busy; // block TX when AVR is busy
// connect outputs of avr
spi_miso = avr.spi_miso;
spi_channel = avr.spi_channel;
avr_rx = avr.tx;
avr.tx_data = 8hx;
avr.new_tx_data = 0;
led = 0; // turn off the LEDs
hdmi.red = hdmi.x[7:0] + ctr.q;
hdmi.blue = hdmi.y[7:0] + (ctr.q << 1);
hdmi.green = hdmi.x[7:0] + hdmi.y[7:0];
hdmi1_tmds = hdmi.tmds;
hdmi1_tmdsb = hdmi.tmdsb;
if(hdmi.x == 1279 && hdmi.y == 719 && hdmi.active) {
ctr.d = ctr.q + 1;
}
}
}
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