trying to break 2 dds card system to produce AUX_DAC mismatch

dds_lockup.py

from artiq.experiment import *


class SetDDSProfile(object):
    def __init__(self, device, frequency, amplitude, phase, switch_state):
        self._device = device
        self._ftw = self._device.frequency_to_ftw(frequency)
        self._asf = self._device.amplitude_to_asf(amplitude)
        self._pow = self._device.turns_to_pow(phase)
        self._sw = switch_state
        # self._attenuator = attenuator

    @kernel
    def run(self):
        self._device.set_mu(self._ftw, pow_=self._pow, asf=self._asf)
        self._device.sw.set_o(self._sw)
        # delay(10*us)
        # TODO: add attenuator setting
        # self._device.set_att(self._attenuator)


class LED(EnvExperiment):
    def build(self):
        self.setattr_device("core")
        self.setattr_device("ttl4")
        self.dds_runners = []
        cycles = 100
        for cycle in range(cycles+1):
            self.dds_runners.append([])
        for card in range(2):
            self.setattr_device("urukul{}_cpld".format(card))
            for channel in range(4):
                ch_name = "urukul{}_ch{}".format(card, channel)
                self.setattr_device(ch_name)
                for cycle in range(cycles):
                    self.dds_runners[cycle].append(SetDDSProfile(
                        getattr(self, ch_name),
                        100*MHz,
                        (cycle)/(cycles-1),
                        0.0,
                        channel < 2  # only turn on the first 2 channel for each card because these are hooked up
                    ))
                self.dds_runners[-1].append(SetDDSProfile(
                        getattr(self, ch_name),
                        100*MHz,
                        0.1,
                        0.0,
                        channel < 2  # only turn on the first 2 channel for each card because these are hooked up
                    ))

    @kernel
    def run(self):
        self.core.break_realtime()
        delay(1*ms)


        self.urukul1_cpld.init()
        self.urukul1_ch0.init()
        self.urukul1_ch1.init()
        self.urukul1_ch2.init()
        self.urukul1_ch3.init()
        self.urukul0_cpld.init()
        self.urukul0_ch0.init()
        self.urukul0_ch1.init()
        self.urukul0_ch2.init()
        self.urukul0_ch3.init()

        self.ttl4.pulse(1*ms)

        delay(1 * ms)

        self.urukul0_ch0.set_att(10.0)
        self.urukul1_ch0.set_att(10.0)
        self.urukul0_ch1.set_att(10.0)
        self.urukul1_ch1.set_att(10.0)
        self.urukul0_ch2.set_att(10.0)
        self.urukul1_ch2.set_att(10.0)
        self.urukul0_ch3.set_att(10.0)
        self.urukul1_ch3.set_att(10.0)

        for runner_list in self.dds_runners:
            for runner in runner_list:
                runner.run()
            delay(0.075*ms)

        delay(60*ms)

        self.urukul0_ch0.sw.off()
        self.urukul0_ch1.sw.off()
        self.urukul1_ch0.sw.off()
        self.urukul1_ch1.sw.off()