Sample RISC-V instruction decoding notation

sample-riscv-decoding-notation

u     : { [31:12],                            [11:7] } -> { simm[31:12],                                  rd[4:0] }
uj    : { [31:12],                            [11:7] } -> { simm[20|10:1|11|19:12],                       rd[4:0] }
i     : { [31:20],          [19:15],          [11:7] } -> { simm[11:0],                rs1[4:0],          rd[4:0] }
i_sh5 : { [24:20],          [19:15],          [11:7] } -> { imm[4:0],                  rs1[4:0],          rd[4:0] }
i_sh6 : { [25:20],          [19:15],          [11:7] } -> { imm[5:0],                  rs1[4:0],          rd[4:0] }
i_sh7 : { [26:20],          [19:15],          [11:7] } -> { imm[6:0],                  rs1[4:0],          rd[4:0] }
i_csr : { [31:20],          [19:15],          [11:7] } -> { imm[11:0],                 rs1[4:0],          rd[4:0] }
s     : {          [24:20], [19:15],          [11:7] } -> { simm[11:5],     rs2[4:0],  rs1[4:0],        simm[4:0] }
sb    : {          [24:20], [19:15],          [11:7] } -> { simm[12|10:5],  rs2[4:0],  rs1[4:0],     simm[4:1|11] }
r     : {          [24:20], [19:15],          [11:7] } -> {                 rs2[4:0],  rs1[4:0],          rd[4:0] }
r_m   : {          [24:20], [19:15], [14:12], [11:7] } -> {                 rs2[4:0],  rs1[4:0], rm[2:0], rd[4:0] }
r4_m  : { [31:27], [24:20], [19:15], [14:12], [11:7] } -> { rs3[4:0],       rs2[4:0],  rs1[4:0], rm[2:0], rd[4:0] }
r_a   : { [26:25], [24:20], [19:15],          [11:7] } -> { aqrl[1:0],      rs2[4:0],  rs1[4:0],          rd[4:0] }
r_l   : { [26:25],          [19:15],          [11:7] } -> { aqrl[1:0],      rs1[4:0],                     rd[4:0] }
r_f   : { [27:24], [23:20]                           } -> { pred[3:0], succ[3:0]                                  }