Makefile

Makefile

# Use gcc to compile
CC = gcc
# wildcard allows you to use * to select multiple files on a directory
# $(wildcard gen/logic/*.c) will sellect all files inside gen/logic/ that end with .c
SOURCE_FILES := $(wildcard gen/logic/*.c) $(wildcard gen/display/*.c) $(wildcard man/*.c)

# Now, all object files are stored right where source files are.
# This prevents having trouble when multiple files have the same name but they
# are in different directories. Resulting with .o files with the same name
# inside the obj/ directory.
# Recreation of that error:
#	gen/display
#		source1.cpp <- "gen/display/source1.cpp" -> "source1.o"
#		source2.cpp
#	gen/logic
#		source1.cpp <- "gen/logic/source1.cpp" -> "source1.o" Error, source.o exists
OBJ_FILES := $(SOURCE_FILES:.c=.o)
# Having .o files inside obj/ directory also made that making a change in only one .c file
# makes the whole project to compile again. Because of what is explained in the
# previous error where names are mistaken and can't be linked to the original source file

LD_FLAGS := -Llib -lgdi32 -lglut32 -loglx -lopengl32
CC_FLAGS := -Igen/display -Igen/logic -Iman -Ilib/include
# executable name. I prefer using variables, so when you have to change something, you do
# here, and not in the compilation code
EXE = win32/demo.exe

all: $(EXE)

# to compile the executable we need our object files
$(EXE) : $(OBJ_FILES)
	# this basically translates to:
	# (gcc) (-Igen/display -Igen/logic -Iman -Ilib/include) -o (win32/demo.exe) (All object files) (-Llib -lgdi32 -lglut32 -loglx -lopengl32)
	$(CC) $(CC_FLAGS) -o $(EXE) $(OBJ_FILES) $(LD_FLAGS)

%.o : %.c
	$(CC) $(CC_FLAGS) -c -o "$@" "$<"

# This deletes all .o files and deletes the compiled executable
# Usefull so when you are editing you don't have multiple .o files here and there
# to execute this command type: "make clean" in command-line
clean:
	rm $(OBJ_FILES) $(EXE)