misodengaku

import subprocess
import sys
import os
import json
from datetime import datetime, timedelta
from pprint import pprint

output = subprocess.run(["lsdvd", "-x", "-Oy", sys.argv[1]], capture_output=True, text=True).stdout
lsdvd = {}
exec(output)

misodengaku

import subprocess
from pprint import pprint
import re
import os
import json
import humanize

cfg = subprocess.run(
    ["sudo", "megacli", "-CfgDsply", "-a0"], capture_output=True, text=True)
# print(cfg)

misodengaku

Text("Lap1:" .. string.format("%02d", math.floor(((time-comp.RenderStart)/3600)))  .. ":" .. string.format("%02d",math.floor(((time-comp.RenderStart)/60)%60)) .. "." .. string.format("%02d",((((time-comp.RenderStart)/60)%60)-math.floor(((time-comp.RenderStart)/60)%60))*100))

misodengaku

from minmaxcheck import MinMaxCheck
import sys
import struct
import matplotlib
import numpy as np
from mpl_toolkits.mplot3d import Axes3D

matplotlib.use('TKagg')

import matplotlib.pyplot as plt

misodengaku

setws workspace
platform create -name super_project_name_wrapper_platform_0 -hw ../pl_system/super_project_name/super_project_name_wrapper.xsa -arch {32-bit}
domain create -name {domain_embedded_system_microblaze_0} -display-name {domain_embedded_system_microblaze_0} -os {standalone} -proc {embedded_system_microblaze_0} -runtime {cpp} -arch {32-bit} -support-app {empty_application}
app create -name embedded_mcu -platform super_project_name_wrapper_platform_0 -domain domain_embedded_system_microblaze_0 -proc embedded_system_microblaze_0 -template "Empty Application"
importsources -name embedded_mcu -path src
app build -name embedded_mcu
exec updatemem -force \
    -meminfo workspace/super_project_name_wrapper_platform_0/hw/super_project_name_wrapper.mmi \
    -bit workspace/super_project_name_wrapper_platform_0/hw/super_project_name_wrapper.bit \
    -data workspace/embedded_mcu/Debug/embedded_mcu.elf \

misodengaku

# set params
set JOBS_NUM 16
set PROJ_NAME super_project_name
set BD_NAME super_project_name
set BD_FILE "${PROJ_NAME}.srcs/sources_1/bd/${BD_NAME}/${BD_NAME}.bd"

# open project and bd file
open_project "./${PROJ_NAME}.xpr"
open_bd_design "./${BD_FILE}"
update_compile_order -fileset sources_1

misodengaku

#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.bd
!*.edif
#*.xci(www.spiritconsortium.org)
!*.xci

*.ip_user_files/
.Xil/

misodengaku

import binascii
import hashlib
import argparse

parser = argparse.ArgumentParser(description='Xilinx COE file generator', formatter_class=argparse.ArgumentDefaultsHelpFormatter)
parser.add_argument('input', metavar='input_file', type=str, help='input file path')
parser.add_argument('output', metavar='output_file', type=str, help='output file path')
parser.add_argument('--width', type=int, help='Memory width (bits)', default=32, choices=[32, 64, 128, 256, 512, 1024, 2048, 4096])
args = parser.parse_args()

misodengaku

ISO-10303-21;
HEADER;
/* Generated by software containing ST-Developer
 * from STEP Tools, Inc. (www.steptools.com) 
 */
/* OPTION: using custom renumber hook */

FILE_DESCRIPTION(
/* description */ (''),
/* implementation_level */ '2;1');

misodengaku