nextpnr output.txt

***************************************************************************
WARNING: the following submodules do not match expected commit:

+ea895e01466431bd75c1b7f8f74f3f0dd54b6a09 third_party/valentyusb (heads/master)

If you are not developing in submodules you may need to run:

git submodule update --init --recursive

manually to bring everything back in sync with upstream
***************************************************************************

mkdir -p build/tinyfpga_bx_usb_lm32.lite/
time python -u ./make.py --platform=tinyfpga_bx --target=usb --cpu-type=lm32 --iprange=192.168.100   --cpu-variant=lite --cpu-variant=lite  \
	2>&1 | tee -a /home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite//output.20181215-135911.log; (exit ${PIPESTATUS[0]})
[('libcompiler_rt',
  '/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/software/libcompiler_rt'),
 ('libbase',
  '/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/software/libbase'),
 ('libnet',
  '/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/software/libnet'),
 ('bios',
  '/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/software/bios')]
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/libcompiler_rt'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/libcompiler_rt'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/libbase'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/libbase'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/libnet'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/libnet'
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/bios'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usb_lm32.lite/software/bios'

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2018  Clifford Wolf <[email protected]>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.8+2 (git sha1 debc0d35, x86_64-conda_cos6-linux-gnu-gcc 1.23.0.449-a04d0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -fdebug-prefix-map=/tmp/really-really-really-really-really-really-really-really-really-really-really-really-really-long-path/conda/conda-bld/yosys_1539704241291/work=/usr/local/src/conda/yosys-0.8_0022_gdebc0d35 -fdebug-prefix-map=/home/tansell/github/timvideos/litex-buildenv/build/conda=/usr/local/src/conda-prefix -fPIC -Os)


-- Executing script file `top.ys' --

1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v' to AST representation.
Generating RTLIL representation for module `\lm32_decoder'.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:341: Warning: Identifier `\op_add' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:342: Warning: Identifier `\op_and' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:343: Warning: Identifier `\op_andhi' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:344: Warning: Identifier `\op_b' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:345: Warning: Identifier `\op_bi' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:346: Warning: Identifier `\op_be' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:347: Warning: Identifier `\op_bg' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:348: Warning: Identifier `\op_bge' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:349: Warning: Identifier `\op_bgeu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:350: Warning: Identifier `\op_bgu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:351: Warning: Identifier `\op_bne' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:352: Warning: Identifier `\op_call' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:353: Warning: Identifier `\op_calli' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:354: Warning: Identifier `\op_cmpe' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:355: Warning: Identifier `\op_cmpg' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:356: Warning: Identifier `\op_cmpge' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:357: Warning: Identifier `\op_cmpgeu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:358: Warning: Identifier `\op_cmpgu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:359: Warning: Identifier `\op_cmpne' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:361: Warning: Identifier `\op_divu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:363: Warning: Identifier `\op_lb' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:364: Warning: Identifier `\op_lbu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:365: Warning: Identifier `\op_lh' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:366: Warning: Identifier `\op_lhu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:367: Warning: Identifier `\op_lw' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:369: Warning: Identifier `\op_modu' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:372: Warning: Identifier `\op_mul' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:374: Warning: Identifier `\op_nor' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:375: Warning: Identifier `\op_or' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:376: Warning: Identifier `\op_orhi' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:377: Warning: Identifier `\op_raise' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:378: Warning: Identifier `\op_rcsr' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:379: Warning: Identifier `\op_sb' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:381: Warning: Identifier `\op_sextb' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:382: Warning: Identifier `\op_sexth' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:384: Warning: Identifier `\op_sh' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:386: Warning: Identifier `\op_sl' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:388: Warning: Identifier `\op_sr' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:389: Warning: Identifier `\op_sru' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:390: Warning: Identifier `\op_sub' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:391: Warning: Identifier `\op_sw' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:392: Warning: Identifier `\op_user' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:393: Warning: Identifier `\op_wcsr' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:394: Warning: Identifier `\op_xnor' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:395: Warning: Identifier `\op_xor' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:398: Warning: Identifier `\arith' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:399: Warning: Identifier `\logical' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:400: Warning: Identifier `\cmp' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:403: Warning: Identifier `\bra' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:404: Warning: Identifier `\call' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:406: Warning: Identifier `\shift' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:416: Warning: Identifier `\sext' is implicitly declared.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v' to AST representation.
Generating RTLIL representation for module `\lm32_interrupt'.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:166: Warning: Identifier `\ie_csr_read_data' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:175: Warning: Identifier `\ip_csr_read_data' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:176: Warning: Identifier `\im_csr_read_data' is implicitly declared.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_adder.v' to AST representation.
Generating RTLIL representation for module `\lm32_adder'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dtlb.v' to AST representation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_itlb.v' to AST representation.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v' to AST representation.
Warning: Literal has a width of 3 bit, but value requires 4 bit. (/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2310)
Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.
Yosys does support them but it is recommended to use `ifdef constructs instead!
Generating RTLIL representation for module `\lm32_cpu'.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1060: Warning: Identifier `\load_q_m' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1061: Warning: Identifier `\store_q_m' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1219: Warning: Identifier `\eret_k_q_x' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1225: Warning: Identifier `\csr_write_enable_k_q_x' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079: Warning: Identifier `\q_d' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128: Warning: Identifier `\q_m' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v' to AST representation.
Generating RTLIL representation for module `\lm32_mc_arithmetic'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v' to AST representation.
Generating RTLIL representation for module `\lm32_load_store_unit'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dp_ram.v' to AST representation.
Generating RTLIL representation for module `\lm32_dp_ram'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_dcache.v' to AST representation.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_debug.v' to AST representation.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_shifter.v' to AST representation.
Generating RTLIL representation for module `\lm32_shifter'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v' to AST representation.
Generating RTLIL representation for module `\lm32_ram'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v' to AST representation.
Generating RTLIL representation for module `\lm32_addsub'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_logic_op.v' to AST representation.
Generating RTLIL representation for module `\lm32_logic_op'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend.
Parsing Verilog input from `top.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v' to AST representation.
Generating RTLIL representation for module `\lm32_icache'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v' to AST representation.
Generating RTLIL representation for module `\lm32_instruction_unit'.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:802: Warning: System task `$display' outside initial block is unsupported.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_multiplier.v' to AST representation.
Generating RTLIL representation for module `\lm32_multiplier'.
Successfully finished Verilog frontend.

20. Executing ATTRMAP pass (move or copy attributes).

21. Executing SYNTH_ICE40 pass.

21.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/home/tansell/github/timvideos/litex-buildenv/build/conda/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Successfully finished Verilog frontend.

21.2. Executing HIERARCHY pass (managing design hierarchy).

21.2.1. Analyzing design hierarchy..
Top module:  \top
Used module:     \lm32_cpu
Used module:         \lm32_interrupt
Used module:         \lm32_mc_arithmetic
Used module:         \lm32_logic_op
Used module:         \lm32_adder
Used module:             \lm32_addsub
Used module:         \lm32_load_store_unit
Used module:         \lm32_decoder
Used module:         \lm32_instruction_unit
Used module:             \lm32_icache
Used module:                 \lm32_ram

21.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_load_store_unit'.
Parameter \associativity = 1
Parameter \sets = 512
Parameter \bytes_per_line = 16
Parameter \base_address = 0
Parameter \limit = 0
Generating RTLIL representation for module `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit'.

21.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_instruction_unit'.
Parameter \eba_reset = 0
Parameter \associativity = 1
Parameter \sets = 128
Parameter \bytes_per_line = 16
Parameter \base_address = 0
Parameter \limit = 2147483647
Generating RTLIL representation for module `$paramod$7c24d6011bbb65756584a8733532ecb225c46e2e\lm32_instruction_unit'.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:802: Warning: System task `$display' outside initial block is unsupported.

21.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_icache'.
Parameter \associativity = 1
Parameter \sets = 512
Parameter \bytes_per_line = 16
Parameter \base_address = 0
Parameter \limit = 0
Generating RTLIL representation for module `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_icache'.

21.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_cpu'.
Parameter \eba_reset = 537198592
Generating RTLIL representation for module `$paramod\lm32_cpu\eba_reset=537198592'.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1060: Warning: Identifier `\load_q_m' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1061: Warning: Identifier `\store_q_m' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1219: Warning: Identifier `\eret_k_q_x' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1225: Warning: Identifier `\csr_write_enable_k_q_x' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079: Warning: Identifier `\q_d' is implicitly declared.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128: Warning: Identifier `\q_m' is implicitly declared.

21.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_ram'.
Parameter \data_width = 20
Parameter \address_width = 9
Generating RTLIL representation for module `$paramod\lm32_ram\data_width=20\address_width=9'.

21.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_ram'.
Parameter \data_width = 32
Parameter \address_width = 11
Generating RTLIL representation for module `$paramod\lm32_ram\data_width=32\address_width=11'.

21.2.8. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\lm32_cpu\eba_reset=537198592
Used module:         \lm32_interrupt
Used module:         \lm32_mc_arithmetic
Used module:         \lm32_logic_op
Used module:         \lm32_adder
Used module:             \lm32_addsub
Used module:         \lm32_load_store_unit
Used module:         \lm32_decoder
Used module:         \lm32_instruction_unit
Used module:             $paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_icache
Used module:                 \lm32_ram

21.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_ram'.
Parameter \data_width = 20
Parameter \address_width = 9
Found cached RTLIL representation for module `$paramod\lm32_ram\data_width=20\address_width=9'.

21.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_ram'.
Parameter \data_width = 32
Parameter \address_width = 11
Found cached RTLIL representation for module `$paramod\lm32_ram\data_width=32\address_width=11'.

21.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_load_store_unit'.
Parameter \associativity = 1
Parameter \sets = 512
Parameter \bytes_per_line = 16
Parameter \base_address = 0
Parameter \limit = 0
Found cached RTLIL representation for module `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit'.

21.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_instruction_unit'.
Parameter \eba_reset = 537198592
Parameter \associativity = 1
Parameter \sets = 128
Parameter \bytes_per_line = 16
Parameter \base_address = 0
Parameter \limit = 2147483647
Generating RTLIL representation for module `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit'.
/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:802: Warning: System task `$display' outside initial block is unsupported.

21.2.13. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\lm32_cpu\eba_reset=537198592
Used module:         \lm32_interrupt
Used module:         \lm32_mc_arithmetic
Used module:         \lm32_logic_op
Used module:         \lm32_adder
Used module:             \lm32_addsub
Used module:         $paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit
Used module:         \lm32_decoder
Used module:         $paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit
Used module:             \lm32_icache
Used module:                 $paramod\lm32_ram\data_width=20\address_width=9
Used module:                 $paramod\lm32_ram\data_width=32\address_width=11

21.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_icache'.
Parameter \associativity = 1
Parameter \sets = 128
Parameter \bytes_per_line = 16
Parameter \base_address = 0
Parameter \limit = 2147483647
Generating RTLIL representation for module `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache'.

21.2.15. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\lm32_cpu\eba_reset=537198592
Used module:         \lm32_interrupt
Used module:         \lm32_mc_arithmetic
Used module:         \lm32_logic_op
Used module:         \lm32_adder
Used module:             \lm32_addsub
Used module:         $paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit
Used module:         \lm32_decoder
Used module:         $paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit
Used module:             $paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache
Used module:                 \lm32_ram

21.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_ram'.
Parameter \data_width = 22
Parameter \address_width = 7
Generating RTLIL representation for module `$paramod\lm32_ram\data_width=22\address_width=7'.

21.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\lm32_ram'.
Parameter \data_width = 32
Parameter \address_width = 9
Generating RTLIL representation for module `$paramod\lm32_ram\data_width=32\address_width=9'.

21.2.18. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\lm32_cpu\eba_reset=537198592
Used module:         \lm32_interrupt
Used module:         \lm32_mc_arithmetic
Used module:         \lm32_logic_op
Used module:         \lm32_adder
Used module:             \lm32_addsub
Used module:         $paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit
Used module:         \lm32_decoder
Used module:         $paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit
Used module:             $paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache
Used module:                 $paramod\lm32_ram\data_width=22\address_width=7
Used module:                 $paramod\lm32_ram\data_width=32\address_width=9

21.2.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\lm32_cpu\eba_reset=537198592
Used module:         \lm32_interrupt
Used module:         \lm32_mc_arithmetic
Used module:         \lm32_logic_op
Used module:         \lm32_adder
Used module:             \lm32_addsub
Used module:         $paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit
Used module:         \lm32_decoder
Used module:         $paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit
Used module:             $paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache
Used module:                 $paramod\lm32_ram\data_width=22\address_width=7
Used module:                 $paramod\lm32_ram\data_width=32\address_width=9
Removing unused module `$paramod\lm32_ram\data_width=32\address_width=11'.
Removing unused module `$paramod\lm32_ram\data_width=20\address_width=9'.
Removing unused module `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_icache'.
Removing unused module `$paramod$7c24d6011bbb65756584a8733532ecb225c46e2e\lm32_instruction_unit'.
Removing unused module `\lm32_multiplier'.
Removing unused module `\lm32_instruction_unit'.
Removing unused module `\lm32_icache'.
Removing unused module `\lm32_ram'.
Removing unused module `\lm32_shifter'.
Removing unused module `\lm32_dp_ram'.
Removing unused module `\lm32_load_store_unit'.
Removing unused module `\lm32_cpu'.
Removed 12 unused modules.

21.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_IO'.
Parameter \PIN_TYPE = 6'101001
Parameter \PULLUP = 1'0
Generating RTLIL representation for module `$paramod\SB_IO\PIN_TYPE=6'101001\PULLUP=1'0'.

21.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_IO'.
Parameter \PIN_TYPE = 6'101001
Parameter \PULLUP = 1'0
Found cached RTLIL representation for module `$paramod\SB_IO\PIN_TYPE=6'101001\PULLUP=1'0'.

21.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_PLL40_CORE'.
Parameter \FEEDBACK_PATH = 48'010100110100100101001101010100000100110001000101
Parameter \DELAY_ADJUSTMENT_MODE_FEEDBACK = 40'0100011001001001010110000100010101000100
Parameter \DELAY_ADJUSTMENT_MODE_RELATIVE = 40'0100011001001001010110000100010101000100
Parameter \SHIFTREG_DIV_MODE = 1'0
Parameter \FDA_FEEDBACK = 1'0
Parameter \FDA_RELATIVE = 1'0
Parameter \PLLOUT_SELECT = 48'010001110100010101001110010000110100110001001011
Parameter \DIVR = 1'0
Parameter \DIVF = 6'101111
Parameter \DIVQ = 3'100
Parameter \FILTER_RANGE = 1'1
Parameter \ENABLE_ICEGATE = 1'0
Generating RTLIL representation for module `$paramod$6fd8a003fe234fb77199d79118f388627c7e9558\SB_PLL40_CORE'.

21.3. Executing PROC pass (convert processes to netlists).

21.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$top.v:4759$2201'.
Found and cleaned up 2 empty switches in `\top.$proc$top.v:3156$1470'.
Cleaned up 2 empty switches.

21.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed 1 dead cases from process $proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2290$2697 in module $paramod\lm32_cpu\eba_reset=537198592.
Removed 1 dead cases from process $proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1615$2477 in module $paramod\lm32_cpu\eba_reset=537198592.
Removed 2 dead cases from process $proc$top.v:3156$1470 in module top.
Removed 1 dead cases from process $proc$top.v:2073$902 in module top.
Removed 1 dead cases from process $proc$top.v:1527$852 in module top.
Removed a total of 6 dead cases.

21.3.3. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$top.v:1180$2200'.
  Set init value: \multiregimpl13_regs1 = 1'0
Found init rule in `\top.$proc$top.v:1179$2199'.
  Set init value: \multiregimpl13_regs0 = 1'0
Found init rule in `\top.$proc$top.v:1178$2198'.
  Set init value: \multiregimpl12_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1177$2197'.
  Set init value: \multiregimpl12_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1176$2196'.
  Set init value: \multiregimpl11_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1175$2195'.
  Set init value: \multiregimpl11_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1174$2194'.
  Set init value: \multiregimpl10_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1173$2193'.
  Set init value: \multiregimpl10_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1172$2192'.
  Set init value: \multiregimpl9_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1171$2191'.
  Set init value: \multiregimpl9_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1170$2190'.
  Set init value: \multiregimpl8_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1169$2189'.
  Set init value: \multiregimpl8_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1168$2188'.
  Set init value: \multiregimpl7_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1167$2187'.
  Set init value: \multiregimpl7_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1166$2186'.
  Set init value: \multiregimpl6_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1165$2185'.
  Set init value: \multiregimpl6_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1164$2184'.
  Set init value: \multiregimpl5_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1163$2183'.
  Set init value: \multiregimpl5_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1162$2182'.
  Set init value: \multiregimpl4_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1161$2181'.
  Set init value: \multiregimpl4_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1160$2180'.
  Set init value: \multiregimpl3_regs1 = 10'0000000000
Found init rule in `\top.$proc$top.v:1159$2179'.
  Set init value: \multiregimpl3_regs0 = 10'0000000000
Found init rule in `\top.$proc$top.v:1158$2178'.
  Set init value: \multiregimpl2_regs2 = 1'0
Found init rule in `\top.$proc$top.v:1157$2177'.
  Set init value: \multiregimpl2_regs1 = 1'0
Found init rule in `\top.$proc$top.v:1156$2176'.
  Set init value: \multiregimpl2_regs0 = 1'0
Found init rule in `\top.$proc$top.v:1155$2175'.
  Set init value: \multiregimpl1_regs2 = 1'0
Found init rule in `\top.$proc$top.v:1154$2174'.
  Set init value: \multiregimpl1_regs1 = 1'0
Found init rule in `\top.$proc$top.v:1153$2173'.
  Set init value: \multiregimpl1_regs0 = 1'0
Found init rule in `\top.$proc$top.v:1151$2172'.
  Set init value: \multiregimpl0_regs1 = 1'0
Found init rule in `\top.$proc$top.v:1150$2171'.
  Set init value: \multiregimpl0_regs0 = 1'0
Found init rule in `\top.$proc$top.v:1149$2170'.
  Set init value: \array_muxed = 2'00
Found init rule in `\top.$proc$top.v:1148$2169'.
  Set init value: \rhs_array_muxed12 = 2'00
Found init rule in `\top.$proc$top.v:1147$2168'.
  Set init value: \rhs_array_muxed11 = 3'000
Found init rule in `\top.$proc$top.v:1146$2167'.
  Set init value: \rhs_array_muxed10 = 1'0
Found init rule in `\top.$proc$top.v:1145$2166'.
  Set init value: \rhs_array_muxed9 = 1'0
Found init rule in `\top.$proc$top.v:1144$2165'.
  Set init value: \rhs_array_muxed8 = 1'0
Found init rule in `\top.$proc$top.v:1143$2164'.
  Set init value: \rhs_array_muxed7 = 4'0000
Found init rule in `\top.$proc$top.v:1142$2163'.
  Set init value: \rhs_array_muxed6 = 0
Found init rule in `\top.$proc$top.v:1141$2162'.
  Set init value: \rhs_array_muxed5 = 30'000000000000000000000000000000
Found init rule in `\top.$proc$top.v:1139$2161'.
  Set init value: \rhs_array_muxed4 = 8'00000000
Found init rule in `\top.$proc$top.v:1138$2160'.
  Set init value: \rhs_array_muxed3 = 1'0
Found init rule in `\top.$proc$top.v:1135$2159'.
  Set init value: \rhs_array_muxed2 = 1'0
Found init rule in `\top.$proc$top.v:1134$2158'.
  Set init value: \rhs_array_muxed1 = 1'0
Found init rule in `\top.$proc$top.v:1133$2157'.
  Set init value: \lhs_array_muxed0 = 1'0
Found init rule in `\top.$proc$top.v:1132$2156'.
  Set init value: \rhs_array_muxed0 = 2'00
Found init rule in `\top.$proc$top.v:1098$2155'.
  Set init value: \interface6_bank_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:1081$2154'.
  Set init value: \interface5_bank_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:1070$2153'.
  Set init value: \interface4_bank_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:1026$2152'.
  Set init value: \interface3_bank_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:1012$2151'.
  Set init value: \interface2_bank_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:899$2150'.
  Set init value: \interface1_bank_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:895$2149'.
  Set init value: \sel_r = 1'0
Found init rule in `\top.$proc$top.v:891$2148'.
  Set init value: \sram_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:862$2147'.
  Set init value: \interface0_bank_bus_dat_r = 8'00000000
Found init rule in `\top.$proc$top.v:858$2146'.
  Set init value: \count = 17'10000000000000000
Found init rule in `\top.$proc$top.v:855$2145'.
  Set init value: \error = 1'0
Found init rule in `\top.$proc$top.v:854$2144'.
  Set init value: \slave_sel_r = 3'000
Found init rule in `\top.$proc$top.v:853$2143'.
  Set init value: \slave_sel = 3'000
Found init rule in `\top.$proc$top.v:852$2142'.
  Set init value: \grant = 1'0
Found init rule in `\top.$proc$top.v:846$2141'.
  Set init value: \shared_ack = 1'0
Found init rule in `\top.$proc$top.v:842$2140'.
  Set init value: \shared_dat_r = 0
Found init rule in `\top.$proc$top.v:809$2139'.
  Set init value: \usb_response_pid_next_value_ce2 = 1'0
Found init rule in `\top.$proc$top.v:808$2138'.
  Set init value: \usb_response_pid_next_value2 = 4'0000
Found init rule in `\top.$proc$top.v:807$2137'.
  Set init value: \usb_transfer_tok_next_value_ce1 = 1'0
Found init rule in `\top.$proc$top.v:806$2136'.
  Set init value: \usb_transfer_tok_next_value1 = 2'00
Found init rule in `\top.$proc$top.v:805$2135'.
  Set init value: \usb_ep_addr_next_value_ce0 = 1'0
Found init rule in `\top.$proc$top.v:804$2134'.
  Set init value: \usb_ep_addr_next_value0 = 5'00000
Found init rule in `\top.$proc$top.v:803$2133'.
  Set init value: \next_state = 3'000
Found init rule in `\top.$proc$top.v:802$2132'.
  Set init value: \state = 3'001
Found init rule in `\top.$proc$top.v:801$2131'.
  Set init value: \usbfstx_txnrziencoder_next_state = 3'000
Found init rule in `\top.$proc$top.v:800$2130'.
  Set init value: \usbfstx_txnrziencoder_state = 3'000
Found init rule in `\top.$proc$top.v:799$2129'.
  Set init value: \usbfstx_txbitstuffer_next_state = 3'000
Found init rule in `\top.$proc$top.v:798$2128'.
  Set init value: \usbfstx_txbitstuffer_state = 3'000
Found init rule in `\top.$proc$top.v:797$2127'.
  Set init value: \usbfstx_fsm_next_state = 3'000
Found init rule in `\top.$proc$top.v:796$2126'.
  Set init value: \usbfstx_fsm_state = 3'000
Found init rule in `\top.$proc$top.v:795$2125'.
  Set init value: \usbfsrx_fsm_next_state = 3'000
Found init rule in `\top.$proc$top.v:794$2124'.
  Set init value: \usbfsrx_fsm_state = 3'000
Found init rule in `\top.$proc$top.v:793$2123'.
  Set init value: \usbfsrx_rxpacketdetect_next_state = 3'000
Found init rule in `\top.$proc$top.v:792$2122'.
  Set init value: \usbfsrx_rxpacketdetect_state = 3'000
Found init rule in `\top.$proc$top.v:791$2121'.
  Set init value: \usbfsrx_rxbitstuffremover_next_state = 3'000
Found init rule in `\top.$proc$top.v:790$2120'.
  Set init value: \usbfsrx_rxbitstuffremover_state = 3'000
Found init rule in `\top.$proc$top.v:789$2119'.
  Set init value: \usbfsrx_rxnrzidecoder_next_state = 1'0
Found init rule in `\top.$proc$top.v:788$2118'.
  Set init value: \usbfsrx_rxnrzidecoder_state = 1'0
Found init rule in `\top.$proc$top.v:787$2117'.
  Set init value: \usbfsrx_rxclockdatarecovery_next_state = 3'000
Found init rule in `\top.$proc$top.v:786$2116'.
  Set init value: \usbfsrx_rxclockdatarecovery_state = 3'000
Found init rule in `\top.$proc$top.v:780$2115'.
  Set init value: \usb_endpointin2_we = 1'1
Found init rule in `\top.$proc$top.v:778$2113'.
  Set init value: \usb_endpointin2_din = 8'00000000
Found init rule in `\top.$proc$top.v:765$2111'.
  Set init value: \usb_endpointin2_graycounter5_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:764$2110'.
  Set init value: \usb_endpointin2_graycounter5_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:762$2109'.
  Set init value: \usb_endpointin2_graycounter5_q = 10'0000000000
Found init rule in `\top.$proc$top.v:760$2108'.
  Set init value: \usb_endpointin2_graycounter4_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:759$2107'.
  Set init value: \usb_endpointin2_graycounter4_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:757$2106'.
  Set init value: \usb_endpointin2_graycounter4_q = 10'0000000000
Found init rule in `\top.$proc$top.v:749$2105'.
  Set init value: \usb_endpointin2_dout = 8'00000000
Found init rule in `\top.$proc$top.v:748$2104'.
  Set init value: \usb_endpointin2_readable = 1'0
Found init rule in `\top.$proc$top.v:747$2103'.
  Set init value: \usb_endpointin2_re = 1'0
Found init rule in `\top.$proc$top.v:746$2102'.
  Set init value: \usb_endpointin2_toggle = 1'0
Found init rule in `\top.$proc$top.v:744$2101'.
  Set init value: \usb_endpointin2_dtb_we = 1'0
Found init rule in `\top.$proc$top.v:743$2100'.
  Set init value: \usb_endpointin2_dtb_re = 1'0
Found init rule in `\top.$proc$top.v:741$2099'.
  Set init value: \usb_endpointin2_dtb_storage_full = 1'0
Found init rule in `\top.$proc$top.v:736$2097'.
  Set init value: \usb_endpointin2_respond_re = 1'0
Found init rule in `\top.$proc$top.v:734$2096'.
  Set init value: \usb_endpointin2_respond_storage_full = 2'00
Found init rule in `\top.$proc$top.v:733$2095'.
  Set init value: \usb_endpointin2_last_tok_status = 2'00
Found init rule in `\top.$proc$top.v:729$2094'.
  Set init value: \usb_endpointin2_eventmanager2_re = 1'0
Found init rule in `\top.$proc$top.v:727$2093'.
  Set init value: \usb_endpointin2_eventmanager2_storage_full = 2'00
Found init rule in `\top.$proc$top.v:726$2092'.
  Set init value: \usb_endpointin2_eventmanager2_pending_w = 2'00
Found init rule in `\top.$proc$top.v:723$2091'.
  Set init value: \usb_endpointin2_eventmanager2_status_w = 2'00
Found init rule in `\top.$proc$top.v:720$2090'.
  Set init value: \usb_endpointin2_packet_clear = 1'0
Found init rule in `\top.$proc$top.v:719$2089'.
  Set init value: \usb_endpointin2_packet_trigger = 1'0
Found init rule in `\top.$proc$top.v:718$2088'.
  Set init value: \usb_endpointin2_packet_pending = 1'0
Found init rule in `\top.$proc$top.v:716$2087'.
  Set init value: \usb_endpointin2_error_clear = 1'0
Found init rule in `\top.$proc$top.v:714$2085'.
  Set init value: \usb_endpointin2_error_pending = 1'0
Found init rule in `\top.$proc$top.v:711$2084'.
  Set init value: \usb_endpointout1_ibuf_re = 1'1
Found init rule in `\top.$proc$top.v:696$2081'.
  Set init value: \usb_endpointout1_outbuf_graycounter3_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:695$2080'.
  Set init value: \usb_endpointout1_outbuf_graycounter3_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:693$2079'.
  Set init value: \usb_endpointout1_outbuf_graycounter3_q = 10'0000000000
Found init rule in `\top.$proc$top.v:691$2078'.
  Set init value: \usb_endpointout1_outbuf_graycounter2_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:690$2077'.
  Set init value: \usb_endpointout1_outbuf_graycounter2_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:688$2076'.
  Set init value: \usb_endpointout1_outbuf_graycounter2_q = 10'0000000000
Found init rule in `\top.$proc$top.v:685$2075'.
  Set init value: \usb_endpointout1_outbuf_asyncfifo1_din = 8'00000000
Found init rule in `\top.$proc$top.v:681$2074'.
  Set init value: \usb_endpointout1_outbuf_asyncfifo1_we = 1'0
Found init rule in `\top.$proc$top.v:680$2073'.
  Set init value: \usb_endpointout1_outbuf_dout = 8'00000000
Found init rule in `\top.$proc$top.v:679$2072'.
  Set init value: \usb_endpointout1_outbuf_readable = 1'0
Found init rule in `\top.$proc$top.v:677$2071'.
  Set init value: \usb_endpointout1_toggle = 1'0
Found init rule in `\top.$proc$top.v:675$2070'.
  Set init value: \usb_endpointout1_dtb_we = 1'0
Found init rule in `\top.$proc$top.v:674$2069'.
  Set init value: \usb_endpointout1_dtb_re = 1'0
Found init rule in `\top.$proc$top.v:672$2068'.
  Set init value: \usb_endpointout1_dtb_storage_full = 1'0
Found init rule in `\top.$proc$top.v:667$2066'.
  Set init value: \usb_endpointout1_respond_re = 1'0
Found init rule in `\top.$proc$top.v:665$2065'.
  Set init value: \usb_endpointout1_respond_storage_full = 2'00
Found init rule in `\top.$proc$top.v:664$2064'.
  Set init value: \usb_endpointout1_last_tok_status = 2'00
Found init rule in `\top.$proc$top.v:660$2063'.
  Set init value: \usb_endpointout1_eventmanager1_re = 1'0
Found init rule in `\top.$proc$top.v:658$2062'.
  Set init value: \usb_endpointout1_eventmanager1_storage_full = 2'00
Found init rule in `\top.$proc$top.v:657$2061'.
  Set init value: \usb_endpointout1_eventmanager1_pending_w = 2'00
Found init rule in `\top.$proc$top.v:654$2060'.
  Set init value: \usb_endpointout1_eventmanager1_status_w = 2'00
Found init rule in `\top.$proc$top.v:651$2059'.
  Set init value: \usb_endpointout1_packet_clear = 1'0
Found init rule in `\top.$proc$top.v:650$2058'.
  Set init value: \usb_endpointout1_packet_trigger = 1'0
Found init rule in `\top.$proc$top.v:649$2057'.
  Set init value: \usb_endpointout1_packet_pending = 1'0
Found init rule in `\top.$proc$top.v:647$2056'.
  Set init value: \usb_endpointout1_error_clear = 1'0
Found init rule in `\top.$proc$top.v:645$2054'.
  Set init value: \usb_endpointout1_error_pending = 1'0
Found init rule in `\top.$proc$top.v:642$2053'.
  Set init value: \usb_endpointin1_we = 1'1
Found init rule in `\top.$proc$top.v:640$2051'.
  Set init value: \usb_endpointin1_din = 8'00000000
Found init rule in `\top.$proc$top.v:627$2049'.
  Set init value: \usb_endpointin1_graycounter3_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:626$2048'.
  Set init value: \usb_endpointin1_graycounter3_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:624$2047'.
  Set init value: \usb_endpointin1_graycounter3_q = 10'0000000000
Found init rule in `\top.$proc$top.v:622$2046'.
  Set init value: \usb_endpointin1_graycounter2_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:621$2045'.
  Set init value: \usb_endpointin1_graycounter2_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:619$2044'.
  Set init value: \usb_endpointin1_graycounter2_q = 10'0000000000
Found init rule in `\top.$proc$top.v:611$2043'.
  Set init value: \usb_endpointin1_dout = 8'00000000
Found init rule in `\top.$proc$top.v:610$2042'.
  Set init value: \usb_endpointin1_readable = 1'0
Found init rule in `\top.$proc$top.v:609$2041'.
  Set init value: \usb_endpointin1_re = 1'0
Found init rule in `\top.$proc$top.v:608$2040'.
  Set init value: \usb_endpointin1_toggle = 1'0
Found init rule in `\top.$proc$top.v:606$2039'.
  Set init value: \usb_endpointin1_dtb_we = 1'0
Found init rule in `\top.$proc$top.v:605$2038'.
  Set init value: \usb_endpointin1_dtb_re = 1'0
Found init rule in `\top.$proc$top.v:603$2037'.
  Set init value: \usb_endpointin1_dtb_storage_full = 1'0
Found init rule in `\top.$proc$top.v:598$2035'.
  Set init value: \usb_endpointin1_respond_re = 1'0
Found init rule in `\top.$proc$top.v:596$2034'.
  Set init value: \usb_endpointin1_respond_storage_full = 2'00
Found init rule in `\top.$proc$top.v:595$2033'.
  Set init value: \usb_endpointin1_last_tok_status = 2'00
Found init rule in `\top.$proc$top.v:591$2032'.
  Set init value: \usb_endpointin1_eventmanager1_re = 1'0
Found init rule in `\top.$proc$top.v:589$2031'.
  Set init value: \usb_endpointin1_eventmanager1_storage_full = 2'00
Found init rule in `\top.$proc$top.v:588$2030'.
  Set init value: \usb_endpointin1_eventmanager1_pending_w = 2'00
Found init rule in `\top.$proc$top.v:585$2029'.
  Set init value: \usb_endpointin1_eventmanager1_status_w = 2'00
Found init rule in `\top.$proc$top.v:582$2028'.
  Set init value: \usb_endpointin1_packet_clear = 1'0
Found init rule in `\top.$proc$top.v:581$2027'.
  Set init value: \usb_endpointin1_packet_trigger = 1'0
Found init rule in `\top.$proc$top.v:580$2026'.
  Set init value: \usb_endpointin1_packet_pending = 1'0
Found init rule in `\top.$proc$top.v:578$2025'.
  Set init value: \usb_endpointin1_error_clear = 1'0
Found init rule in `\top.$proc$top.v:576$2023'.
  Set init value: \usb_endpointin1_error_pending = 1'0
Found init rule in `\top.$proc$top.v:572$2021'.
  Set init value: \usb_oep_status = 2'00
Found init rule in `\top.$proc$top.v:571$2020'.
  Set init value: \usb_oep_trigger = 1'0
Found init rule in `\top.$proc$top.v:569$2018'.
  Set init value: \usb_oep_we = 1'1
Found init rule in `\top.$proc$top.v:567$2016'.
  Set init value: \usb_oep_din = 8'00000000
Found init rule in `\top.$proc$top.v:566$2015'.
  Set init value: \usb_oep_re = 1'1
Found init rule in `\top.$proc$top.v:563$2012'.
  Set init value: \usb_endpointin0_we = 1'1
Found init rule in `\top.$proc$top.v:561$2010'.
  Set init value: \usb_endpointin0_din = 8'00000000
Found init rule in `\top.$proc$top.v:548$2008'.
  Set init value: \usb_endpointin0_graycounter1_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:547$2007'.
  Set init value: \usb_endpointin0_graycounter1_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:545$2006'.
  Set init value: \usb_endpointin0_graycounter1_q = 10'0000000000
Found init rule in `\top.$proc$top.v:543$2005'.
  Set init value: \usb_endpointin0_graycounter0_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:542$2004'.
  Set init value: \usb_endpointin0_graycounter0_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:540$2003'.
  Set init value: \usb_endpointin0_graycounter0_q = 10'0000000000
Found init rule in `\top.$proc$top.v:532$2002'.
  Set init value: \usb_endpointin0_dout = 8'00000000
Found init rule in `\top.$proc$top.v:531$2001'.
  Set init value: \usb_endpointin0_readable = 1'0
Found init rule in `\top.$proc$top.v:530$2000'.
  Set init value: \usb_endpointin0_re = 1'0
Found init rule in `\top.$proc$top.v:529$1999'.
  Set init value: \usb_endpointin0_toggle = 1'0
Found init rule in `\top.$proc$top.v:527$1998'.
  Set init value: \usb_endpointin0_dtb_we = 1'0
Found init rule in `\top.$proc$top.v:526$1997'.
  Set init value: \usb_endpointin0_dtb_re = 1'0
Found init rule in `\top.$proc$top.v:524$1996'.
  Set init value: \usb_endpointin0_dtb_storage_full = 1'0
Found init rule in `\top.$proc$top.v:519$1995'.
  Set init value: \usb_endpointin0_respond_re = 1'0
Found init rule in `\top.$proc$top.v:517$1994'.
  Set init value: \usb_endpointin0_respond_storage_full = 2'00
Found init rule in `\top.$proc$top.v:516$1993'.
  Set init value: \usb_endpointin0_last_tok_status = 2'00
Found init rule in `\top.$proc$top.v:512$1992'.
  Set init value: \usb_endpointin0_eventmanager0_re = 1'0
Found init rule in `\top.$proc$top.v:510$1991'.
  Set init value: \usb_endpointin0_eventmanager0_storage_full = 2'00
Found init rule in `\top.$proc$top.v:509$1990'.
  Set init value: \usb_endpointin0_eventmanager0_pending_w = 2'00
Found init rule in `\top.$proc$top.v:506$1989'.
  Set init value: \usb_endpointin0_eventmanager0_status_w = 2'00
Found init rule in `\top.$proc$top.v:503$1988'.
  Set init value: \usb_endpointin0_packet_clear = 1'0
Found init rule in `\top.$proc$top.v:502$1987'.
  Set init value: \usb_endpointin0_packet_trigger = 1'0
Found init rule in `\top.$proc$top.v:501$1986'.
  Set init value: \usb_endpointin0_packet_pending = 1'0
Found init rule in `\top.$proc$top.v:499$1985'.
  Set init value: \usb_endpointin0_error_clear = 1'0
Found init rule in `\top.$proc$top.v:497$1983'.
  Set init value: \usb_endpointin0_error_pending = 1'0
Found init rule in `\top.$proc$top.v:494$1982'.
  Set init value: \usb_endpointout0_ibuf_re = 1'1
Found init rule in `\top.$proc$top.v:479$1979'.
  Set init value: \usb_endpointout0_outbuf_graycounter1_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:478$1978'.
  Set init value: \usb_endpointout0_outbuf_graycounter1_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:476$1977'.
  Set init value: \usb_endpointout0_outbuf_graycounter1_q = 10'0000000000
Found init rule in `\top.$proc$top.v:474$1976'.
  Set init value: \usb_endpointout0_outbuf_graycounter0_q_next_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:473$1975'.
  Set init value: \usb_endpointout0_outbuf_graycounter0_q_binary = 10'0000000000
Found init rule in `\top.$proc$top.v:471$1974'.
  Set init value: \usb_endpointout0_outbuf_graycounter0_q = 10'0000000000
Found init rule in `\top.$proc$top.v:468$1973'.
  Set init value: \usb_endpointout0_outbuf_asyncfifo0_din = 8'00000000
Found init rule in `\top.$proc$top.v:464$1972'.
  Set init value: \usb_endpointout0_outbuf_asyncfifo0_we = 1'0
Found init rule in `\top.$proc$top.v:463$1971'.
  Set init value: \usb_endpointout0_outbuf_dout = 8'00000000
Found init rule in `\top.$proc$top.v:462$1970'.
  Set init value: \usb_endpointout0_outbuf_readable = 1'0
Found init rule in `\top.$proc$top.v:460$1969'.
  Set init value: \usb_endpointout0_toggle = 1'0
Found init rule in `\top.$proc$top.v:458$1968'.
  Set init value: \usb_endpointout0_dtb_we = 1'0
Found init rule in `\top.$proc$top.v:457$1967'.
  Set init value: \usb_endpointout0_dtb_re = 1'0
Found init rule in `\top.$proc$top.v:455$1966'.
  Set init value: \usb_endpointout0_dtb_storage_full = 1'0
Found init rule in `\top.$proc$top.v:450$1965'.
  Set init value: \usb_endpointout0_respond_re = 1'0
Found init rule in `\top.$proc$top.v:448$1964'.
  Set init value: \usb_endpointout0_respond_storage_full = 2'00
Found init rule in `\top.$proc$top.v:447$1963'.
  Set init value: \usb_endpointout0_last_tok_status = 2'00
Found init rule in `\top.$proc$top.v:443$1962'.
  Set init value: \usb_endpointout0_eventmanager0_re = 1'0
Found init rule in `\top.$proc$top.v:441$1961'.
  Set init value: \usb_endpointout0_eventmanager0_storage_full = 2'00
Found init rule in `\top.$proc$top.v:440$1960'.
  Set init value: \usb_endpointout0_eventmanager0_pending_w = 2'00
Found init rule in `\top.$proc$top.v:437$1959'.
  Set init value: \usb_endpointout0_eventmanager0_status_w = 2'00
Found init rule in `\top.$proc$top.v:434$1958'.
  Set init value: \usb_endpointout0_packet_clear = 1'0
Found init rule in `\top.$proc$top.v:433$1957'.
  Set init value: \usb_endpointout0_packet_trigger = 1'0
Found init rule in `\top.$proc$top.v:432$1956'.
  Set init value: \usb_endpointout0_packet_pending = 1'0
Found init rule in `\top.$proc$top.v:430$1955'.
  Set init value: \usb_endpointout0_error_clear = 1'0
Found init rule in `\top.$proc$top.v:428$1953'.
  Set init value: \usb_endpointout0_error_pending = 1'0
Found init rule in `\top.$proc$top.v:424$1952'.
  Set init value: \usb_signal_is_el1 = 1'0
Found init rule in `\top.$proc$top.v:422$1951'.
  Set init value: \usb_signal_is_el0 = 1'0
Found init rule in `\top.$proc$top.v:421$1950'.
  Set init value: \usb_response_pid = 4'0000
Found init rule in `\top.$proc$top.v:419$1949'.
  Set init value: \usb_data_toggle_bit = 1'0
Found init rule in `\top.$proc$top.v:416$1948'.
  Set init value: \usb_data_send_get = 1'0
Found init rule in `\top.$proc$top.v:413$1947'.
  Set init value: \usb_data_recv_put = 1'0
Found init rule in `\top.$proc$top.v:411$1946'.
  Set init value: \usb_ep_addr = 5'00000
Found init rule in `\top.$proc$top.v:406$1945'.
  Set init value: \usb_transfer_abort = 1'0
Found init rule in `\top.$proc$top.v:405$1944'.
  Set init value: \usb_transfer_commit0 = 1'0
Found init rule in `\top.$proc$top.v:404$1943'.
  Set init value: \usb_transfer_setup = 1'0
Found init rule in `\top.$proc$top.v:403$1942'.
  Set init value: \usb_transfer_tok = 2'00
Found init rule in `\top.$proc$top.v:402$1941'.
  Set init value: \usb_transfer_start = 1'0
Found init rule in `\top.$proc$top.v:400$1939'.
  Set init value: \usb_tx_o_oe = 1'0
Found init rule in `\top.$proc$top.v:399$1938'.
  Set init value: \usb_tx_o_usbn = 1'0
Found init rule in `\top.$proc$top.v:398$1937'.
  Set init value: \usb_tx_o_usbp = 1'0
Found init rule in `\top.$proc$top.v:397$1936'.
  Set init value: \usb_tx_o_pkt_end = 1'0
Found init rule in `\top.$proc$top.v:396$1935'.
  Set init value: \usb_tx_o_data_get = 1'0
Found init rule in `\top.$proc$top.v:395$1934'.
  Set init value: \usb_tx_nrzi_o_oe = 1'0
Found init rule in `\top.$proc$top.v:394$1933'.
  Set init value: \usb_tx_nrzi_o_usbn = 1'0
Found init rule in `\top.$proc$top.v:393$1932'.
  Set init value: \usb_tx_nrzi_o_usbp = 1'0
Found init rule in `\top.$proc$top.v:392$1931'.
  Set init value: \usb_tx_nrzi_oe = 1'0
Found init rule in `\top.$proc$top.v:391$1930'.
  Set init value: \usb_tx_nrzi_usbn = 1'0
Found init rule in `\top.$proc$top.v:390$1929'.
  Set init value: \usb_tx_nrzi_usbp = 1'0
Found init rule in `\top.$proc$top.v:389$1928'.
  Set init value: \usb_tx_bitstuffer_o_oe = 1'0
Found init rule in `\top.$proc$top.v:388$1927'.
  Set init value: \usb_tx_bitstuffer_o_se0 = 1'0
Found init rule in `\top.$proc$top.v:387$1926'.
  Set init value: \usb_tx_bitstuffer_o_data = 1'0
Found init rule in `\top.$proc$top.v:385$1925'.
  Set init value: \usb_tx_bitstuffer_stuff_bit = 1'0
Found init rule in `\top.$proc$top.v:384$1924'.
  Set init value: \usb_tx_mux_stuff_bit_strobe = 1'0
Found init rule in `\top.$proc$top.v:383$1923'.
  Set init value: \usb_tx_mux_stuff_se0 = 1'0
Found init rule in `\top.$proc$top.v:382$1922'.
  Set init value: \usb_tx_mux_stuff_data = 1'0
Found init rule in `\top.$proc$top.v:381$1921'.
  Set init value: \usb_tx_mux_stuff_oe = 1'0
Found init rule in `\top.$proc$top.v:380$1920'.
  Set init value: \usb_tx_pid_is_data = 1'0
Found init rule in `\top.$proc$top.v:379$1919'.
  Set init value: \usb_tx_crc16_shifter_not_empty = 1'0
Found init rule in `\top.$proc$top.v:376$1918'.
  Set init value: \usb_tx_crc16_shifter_shifter = 17'00000000000000000
Found init rule in `\top.$proc$top.v:375$1917'.
  Set init value: \usb_tx_o_crc = 16'0000000000000000
Found init rule in `\top.$proc$top.v:373$1916'.
  Set init value: \usb_tx_crc = 16'0000000000000000
Found init rule in `\top.$proc$top.v:372$1915'.
  Set init value: \usb_tx_data_shifter_not_empty = 1'0
Found init rule in `\top.$proc$top.v:369$1914'.
  Set init value: \usb_tx_data_shifter_shifter = 9'000000000
Found init rule in `\top.$proc$top.v:368$1913'.
  Set init value: \usb_tx_pid_shifter_not_empty = 1'0
Found init rule in `\top.$proc$top.v:365$1912'.
  Set init value: \usb_tx_pid_shifter_shifter = 9'000000000
Found init rule in `\top.$proc$top.v:364$1911'.
  Set init value: \usb_tx_sync_shifter_not_empty = 1'0
Found init rule in `\top.$proc$top.v:361$1910'.
  Set init value: \usb_tx_sync_shifter_shifter = 9'000000000
Found init rule in `\top.$proc$top.v:360$1909'.
  Set init value: \usb_tx_pkt_end = 1'0
Found init rule in `\top.$proc$top.v:359$1908'.
  Set init value: \usb_tx_shift_crc16 = 1'0
Found init rule in `\top.$proc$top.v:358$1907'.
  Set init value: \usb_tx_load_crc16 = 1'0
Found init rule in `\top.$proc$top.v:357$1906'.
  Set init value: \usb_tx_shift_data = 1'0
Found init rule in `\top.$proc$top.v:356$1905'.
  Set init value: \usb_tx_load_data = 1'0
Found init rule in `\top.$proc$top.v:355$1904'.
  Set init value: \usb_tx_shift_eop = 1'0
Found init rule in `\top.$proc$top.v:354$1903'.
  Set init value: \usb_tx_shift_pid = 1'0
Found init rule in `\top.$proc$top.v:353$1902'.
  Set init value: \usb_tx_shift_sync = 1'0
Found init rule in `\top.$proc$top.v:352$1901'.
  Set init value: \usb_tx_pkt_active = 1'0
Found init rule in `\top.$proc$top.v:348$1900'.
  Set init value: \usb_tx_i_pid = 4'0000
Found init rule in `\top.$proc$top.v:347$1899'.
  Set init value: \usb_tx_i_pkt_start = 1'0
Found init rule in `\top.$proc$top.v:346$1898'.
  Set init value: \usb_rx_o_ep = 4'0000
Found init rule in `\top.$proc$top.v:345$1897'.
  Set init value: \usb_rx_o_addr = 7'0000000
Found init rule in `\top.$proc$top.v:344$1896'.
  Set init value: \usb_rx_o_pid = 4'0000
Found init rule in `\top.$proc$top.v:343$1895'.
  Set init value: \usb_rx_data_n1 = 8'00000000
Found init rule in `\top.$proc$top.v:342$1894'.
  Set init value: \usb_rx_data_n0 = 8'00000000
Found init rule in `\top.$proc$top.v:341$1893'.
  Set init value: \usb_rx_end_data = 1'0
Found init rule in `\top.$proc$top.v:340$1892'.
  Set init value: \usb_rx_put_data = 1'0
Found init rule in `\top.$proc$top.v:339$1891'.
  Set init value: \usb_rx_start_data = 1'0
Found init rule in `\top.$proc$top.v:338$1890'.
  Set init value: \usb_rx_end_token = 1'0
Found init rule in `\top.$proc$top.v:337$1889'.
  Set init value: \usb_rx_start_token = 1'0
Found init rule in `\top.$proc$top.v:336$1888'.
  Set init value: \usb_rx_end_handshake = 1'0
Found init rule in `\top.$proc$top.v:335$1887'.
  Set init value: \usb_rx_end_pid = 1'0
Found init rule in `\top.$proc$top.v:334$1886'.
  Set init value: \usb_rx_start_tok = 1'0
Found init rule in `\top.$proc$top.v:333$1885'.
  Set init value: \usb_rx_o_put = 1'0
Found init rule in `\top.$proc$top.v:330$1884'.
  Set init value: \usb_rx_shift_reg = 9'000000000
Found init rule in `\top.$proc$top.v:329$1883'.
  Set init value: \usb_rx_i_reset = 1'0
Found init rule in `\top.$proc$top.v:328$1882'.
  Set init value: \usb_rx_pkt_end1 = 1'0
Found init rule in `\top.$proc$top.v:327$1881'.
  Set init value: \usb_rx_pkt_active1 = 1'0
Found init rule in `\top.$proc$top.v:326$1880'.
  Set init value: \usb_rx_o_pkt_end = 1'0
Found init rule in `\top.$proc$top.v:325$1879'.
  Set init value: \usb_rx_o_pkt_active = 1'0
Found init rule in `\top.$proc$top.v:324$1878'.
  Set init value: \usb_rx_o_pkt_start = 1'0
Found init rule in `\top.$proc$top.v:323$1877'.
  Set init value: \usb_rx_pkt_end0 = 1'0
Found init rule in `\top.$proc$top.v:322$1876'.
  Set init value: \usb_rx_pkt_active0 = 1'0
Found init rule in `\top.$proc$top.v:321$1875'.
  Set init value: \usb_rx_pkt_start = 1'0
Found init rule in `\top.$proc$top.v:320$1874'.
  Set init value: \usb_rx_bitstuff_error = 1'0
Found init rule in `\top.$proc$top.v:319$1873'.
  Set init value: \usb_rx_se0 = 1'0
Found init rule in `\top.$proc$top.v:318$1872'.
  Set init value: \usb_rx_data = 1'0
Found init rule in `\top.$proc$top.v:317$1871'.
  Set init value: \usb_rx_valid = 1'0
Found init rule in `\top.$proc$top.v:316$1870'.
  Set init value: \usb_rx_bitstuff_o_bitstuff_error = 1'0
Found init rule in `\top.$proc$top.v:315$1869'.
  Set init value: \usb_rx_bitstuff_o_se0 = 1'0
Found init rule in `\top.$proc$top.v:314$1868'.
  Set init value: \usb_rx_bitstuff_o_data = 1'0
Found init rule in `\top.$proc$top.v:313$1867'.
  Set init value: \usb_rx_bitstuff_o_valid = 1'0
Found init rule in `\top.$proc$top.v:312$1866'.
  Set init value: \usb_rx_bitstuff_drop_bit = 1'0
Found init rule in `\top.$proc$top.v:311$1865'.
  Set init value: \usb_rx_nrzi_o_se0 = 1'0
Found init rule in `\top.$proc$top.v:310$1864'.
  Set init value: \usb_rx_nrzi_o_data1 = 1'0
Found init rule in `\top.$proc$top.v:309$1863'.
  Set init value: \usb_rx_nrzi_o_valid1 = 1'0
Found init rule in `\top.$proc$top.v:308$1862'.
  Set init value: \usb_rx_nrzi_o_data0 = 1'0
Found init rule in `\top.$proc$top.v:307$1861'.
  Set init value: \usb_rx_nrzi_o_valid0 = 1'0
Found init rule in `\top.$proc$top.v:306$1860'.
  Set init value: \usb_rx_line_state_se11 = 1'0
Found init rule in `\top.$proc$top.v:305$1859'.
  Set init value: \usb_rx_line_state_se01 = 1'0
Found init rule in `\top.$proc$top.v:304$1858'.
  Set init value: \usb_rx_line_state_dk1 = 1'0
Found init rule in `\top.$proc$top.v:303$1857'.
  Set init value: \usb_rx_line_state_dj1 = 1'0
Found init rule in `\top.$proc$top.v:302$1856'.
  Set init value: \usb_rx_line_state_valid = 1'0
Found init rule in `\top.$proc$top.v:301$1855'.
  Set init value: \usb_rx_line_state_phase = 2'00
Found init rule in `\top.$proc$top.v:300$1854'.
  Set init value: \usb_rx_line_state_se10 = 1'0
Found init rule in `\top.$proc$top.v:299$1853'.
  Set init value: \usb_rx_line_state_se00 = 1'0
Found init rule in `\top.$proc$top.v:298$1852'.
  Set init value: \usb_rx_line_state_dk0 = 1'0
Found init rule in `\top.$proc$top.v:297$1851'.
  Set init value: \usb_rx_line_state_dj0 = 1'0
Found init rule in `\top.$proc$top.v:296$1850'.
  Set init value: \usb_rx_line_state_dt = 1'0
Found init rule in `\top.$proc$top.v:292$1849'.
  Set init value: \usb_pullup_re = 1'0
Found init rule in `\top.$proc$top.v:290$1848'.
  Set init value: \usb_pullup_storage_full = 1'0
Found init rule in `\top.$proc$top.v:286$1847'.
  Set init value: \usb_iobuf_usb_n_rx = 1'0
Found init rule in `\top.$proc$top.v:285$1846'.
  Set init value: \usb_iobuf_usb_p_rx = 1'0
Found init rule in `\top.$proc$top.v:281$1845'.
  Set init value: \usbsoc_spiflash_counter = 8'00000000
Found init rule in `\top.$proc$top.v:280$1844'.
  Set init value: \usbsoc_spiflash_miso1 = 1'0
Found init rule in `\top.$proc$top.v:279$1843'.
  Set init value: \usbsoc_spiflash_i = 1'0
Found init rule in `\top.$proc$top.v:278$1842'.
  Set init value: \usbsoc_spiflash_sr = 0
Found init rule in `\top.$proc$top.v:277$1841'.
  Set init value: \usbsoc_spiflash_clk1 = 1'0
Found init rule in `\top.$proc$top.v:276$1840'.
  Set init value: \usbsoc_spiflash_cs_n1 = 1'1
Found init rule in `\top.$proc$top.v:275$1839'.
  Set init value: \usbsoc_spiflash_bitbang_en_re = 1'0
Found init rule in `\top.$proc$top.v:273$1838'.
  Set init value: \usbsoc_spiflash_bitbang_en_storage_full = 1'0
Found init rule in `\top.$proc$top.v:272$1837'.
  Set init value: \usbsoc_spiflash_miso_status = 1'0
Found init rule in `\top.$proc$top.v:271$1836'.
  Set init value: \usbsoc_spiflash_bitbang_re = 1'0
Found init rule in `\top.$proc$top.v:269$1835'.
  Set init value: \usbsoc_spiflash_bitbang_storage_full = 4'0000
Found init rule in `\top.$proc$top.v:264$1833'.
  Set init value: \usbsoc_spiflash_bus_ack = 1'0
Found init rule in `\top.$proc$top.v:254$1832'.
  Set init value: \usbsoc_reset_delay = 12'111111111111
Found init rule in `\top.$proc$top.v:246$1829'.
  Set init value: \usbsoc_usbsoc_timer0_value = 0
Found init rule in `\top.$proc$top.v:242$1828'.
  Set init value: \usbsoc_usbsoc_timer0_eventmanager_re = 1'0
Found init rule in `\top.$proc$top.v:240$1827'.
  Set init value: \usbsoc_usbsoc_timer0_eventmanager_storage_full = 1'0
Found init rule in `\top.$proc$top.v:233$1826'.
  Set init value: \usbsoc_usbsoc_timer0_zero_old_trigger = 1'0
Found init rule in `\top.$proc$top.v:232$1825'.
  Set init value: \usbsoc_usbsoc_timer0_zero_clear = 1'0
Found init rule in `\top.$proc$top.v:230$1824'.
  Set init value: \usbsoc_usbsoc_timer0_zero_pending = 1'0
Found init rule in `\top.$proc$top.v:227$1823'.
  Set init value: \usbsoc_usbsoc_timer0_value_status = 0
Found init rule in `\top.$proc$top.v:223$1821'.
  Set init value: \usbsoc_usbsoc_timer0_en_re = 1'0
Found init rule in `\top.$proc$top.v:221$1820'.
  Set init value: \usbsoc_usbsoc_timer0_en_storage_full = 1'0
Found init rule in `\top.$proc$top.v:220$1819'.
  Set init value: \usbsoc_usbsoc_timer0_reload_re = 1'0
Found init rule in `\top.$proc$top.v:218$1818'.
  Set init value: \usbsoc_usbsoc_timer0_reload_storage_full = 0
Found init rule in `\top.$proc$top.v:217$1817'.
  Set init value: \usbsoc_usbsoc_timer0_load_re = 1'0
Found init rule in `\top.$proc$top.v:215$1816'.
  Set init value: \usbsoc_usbsoc_timer0_load_storage_full = 0
Found init rule in `\top.$proc$top.v:199$1814'.
  Set init value: \usbsoc_usbsoc_uart_rx_fifo_wrport_adr = 4'0000
Found init rule in `\top.$proc$top.v:198$1813'.
  Set init value: \usbsoc_usbsoc_uart_rx_fifo_consume = 4'0000
Found init rule in `\top.$proc$top.v:197$1812'.
  Set init value: \usbsoc_usbsoc_uart_rx_fifo_produce = 4'0000
Found init rule in `\top.$proc$top.v:195$1810'.
  Set init value: \usbsoc_usbsoc_uart_rx_fifo_level0 = 5'00000
Found init rule in `\top.$proc$top.v:188$1809'.
  Set init value: \usbsoc_usbsoc_uart_rx_fifo_readable = 1'0
Found init rule in `\top.$proc$top.v:162$1808'.
  Set init value: \usbsoc_usbsoc_uart_tx_fifo_wrport_adr = 4'0000
Found init rule in `\top.$proc$top.v:161$1807'.
  Set init value: \usbsoc_usbsoc_uart_tx_fifo_consume = 4'0000
Found init rule in `\top.$proc$top.v:160$1806'.
  Set init value: \usbsoc_usbsoc_uart_tx_fifo_produce = 4'0000
Found init rule in `\top.$proc$top.v:158$1804'.
  Set init value: \usbsoc_usbsoc_uart_tx_fifo_level0 = 5'00000
Found init rule in `\top.$proc$top.v:151$1803'.
  Set init value: \usbsoc_usbsoc_uart_tx_fifo_readable = 1'0
Found init rule in `\top.$proc$top.v:136$1800'.
  Set init value: \usbsoc_usbsoc_uart_eventmanager_re = 1'0
Found init rule in `\top.$proc$top.v:134$1799'.
  Set init value: \usbsoc_usbsoc_uart_eventmanager_storage_full = 2'00
Found init rule in `\top.$proc$top.v:133$1798'.
  Set init value: \usbsoc_usbsoc_uart_eventmanager_pending_w = 2'00
Found init rule in `\top.$proc$top.v:130$1797'.
  Set init value: \usbsoc_usbsoc_uart_eventmanager_status_w = 2'00
Found init rule in `\top.$proc$top.v:127$1796'.
  Set init value: \usbsoc_usbsoc_uart_rx_old_trigger = 1'0
Found init rule in `\top.$proc$top.v:126$1795'.
  Set init value: \usbsoc_usbsoc_uart_rx_clear = 1'0
Found init rule in `\top.$proc$top.v:124$1794'.
  Set init value: \usbsoc_usbsoc_uart_rx_pending = 1'0
Found init rule in `\top.$proc$top.v:122$1793'.
  Set init value: \usbsoc_usbsoc_uart_tx_old_trigger = 1'0
Found init rule in `\top.$proc$top.v:121$1792'.
  Set init value: \usbsoc_usbsoc_uart_tx_clear = 1'0
Found init rule in `\top.$proc$top.v:119$1791'.
  Set init value: \usbsoc_usbsoc_uart_tx_pending = 1'0
Found init rule in `\top.$proc$top.v:111$1790'.
  Set init value: \usbsoc_usbsoc_uart_phy_rx_busy = 1'0
Found init rule in `\top.$proc$top.v:110$1789'.
  Set init value: \usbsoc_usbsoc_uart_phy_rx_bitcount = 4'0000
Found init rule in `\top.$proc$top.v:109$1788'.
  Set init value: \usbsoc_usbsoc_uart_phy_rx_reg = 8'00000000
Found init rule in `\top.$proc$top.v:108$1787'.
  Set init value: \usbsoc_usbsoc_uart_phy_rx_r = 1'0
Found init rule in `\top.$proc$top.v:106$1786'.
  Set init value: \usbsoc_usbsoc_uart_phy_phase_accumulator_rx = 0
Found init rule in `\top.$proc$top.v:105$1785'.
  Set init value: \usbsoc_usbsoc_uart_phy_uart_clk_rxen = 1'0
Found init rule in `\top.$proc$top.v:104$1784'.
  Set init value: \usbsoc_usbsoc_uart_phy_source_payload_data = 8'00000000
Found init rule in `\top.$proc$top.v:100$1781'.
  Set init value: \usbsoc_usbsoc_uart_phy_source_valid = 1'0
Found init rule in `\top.$proc$top.v:99$1780'.
  Set init value: \usbsoc_usbsoc_uart_phy_tx_busy = 1'0
Found init rule in `\top.$proc$top.v:98$1779'.
  Set init value: \usbsoc_usbsoc_uart_phy_tx_bitcount = 4'0000
Found init rule in `\top.$proc$top.v:97$1778'.
  Set init value: \usbsoc_usbsoc_uart_phy_tx_reg = 8'00000000
Found init rule in `\top.$proc$top.v:96$1777'.
  Set init value: \usbsoc_usbsoc_uart_phy_phase_accumulator_tx = 0
Found init rule in `\top.$proc$top.v:95$1776'.
  Set init value: \usbsoc_usbsoc_uart_phy_uart_clk_txen = 1'0
Found init rule in `\top.$proc$top.v:91$1775'.
  Set init value: \usbsoc_usbsoc_uart_phy_sink_ready = 1'0
Found init rule in `\top.$proc$top.v:89$1774'.
  Set init value: \usbsoc_usbsoc_uart_phy_re = 1'0
Found init rule in `\top.$proc$top.v:87$1773'.
  Set init value: \usbsoc_usbsoc_uart_phy_storage_full = 30923764
Found init rule in `\top.$proc$top.v:86$1772'.
  Set init value: \usbsoc_usbsoc_counter = 2'00
Found init rule in `\top.$proc$top.v:81$1770'.
  Set init value: \usbsoc_usbsoc_bus_wishbone_ack = 1'0
Found init rule in `\top.$proc$top.v:77$1769'.
  Set init value: \usbsoc_usbsoc_bus_wishbone_dat_r = 0
Found init rule in `\top.$proc$top.v:73$1768'.
  Set init value: \usbsoc_usbsoc_interface_dat_w = 8'00000000
Found init rule in `\top.$proc$top.v:72$1767'.
  Set init value: \usbsoc_usbsoc_interface_we = 1'0
Found init rule in `\top.$proc$top.v:71$1766'.
  Set init value: \usbsoc_usbsoc_interface_adr = 14'00000000000000
Found init rule in `\top.$proc$top.v:69$1765'.
  Set init value: \usbsoc_usbsoc_sram_we = 4'0000
Found init rule in `\top.$proc$top.v:62$1763'.
  Set init value: \usbsoc_usbsoc_sram_bus_ack = 1'0
Found init rule in `\top.$proc$top.v:53$1762'.
  Set init value: \usbsoc_usbsoc_lm32_interrupt = 0
Found init rule in `\top.$proc$top.v:29$1761'.
  Set init value: \usbsoc_usbsoc_ctrl_bus_errors = 0
Found init rule in `\top.$proc$top.v:25$1760'.
  Set init value: \usbsoc_usbsoc_ctrl_re = 1'0
Found init rule in `\top.$proc$top.v:23$1759'.
  Set init value: \usbsoc_usbsoc_ctrl_storage_full = 305419896

21.3.4. Executing PROC_ARST pass (detect async resets in processes).

21.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2908'.
     1/1: $0\ra[8:0]
Creating decoders for process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2901'.
     1/3: $0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904
     2/3: $0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_DATA[31:0]$2903
     3/3: $0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_ADDR[8:0]$2902
Creating decoders for process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2897'.
     1/1: $0\ra[6:0]
Creating decoders for process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2890'.
     1/3: $0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893
     2/3: $0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_DATA[21:0]$2892
     3/3: $0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_ADDR[6:0]$2891
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3033$2774'.
     1/3: $0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777
     2/3: $0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_DATA[31:0]$2776
     3/3: $0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_ADDR[4:0]$2775
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
     1/53: $0\exception_w[0:0]
     2/53: $0\exception_m[0:0]
     3/53: $0\condition_met_m[0:0]
     4/53: $0\logic_op_x[3:0]
     5/53: $0\operand_w[31:0]
     6/53: $0\operand_m[31:0]
     7/53: $0\store_operand_x[31:0]
     8/53: $0\memop_pc_w[29:0]
     9/53: $0\data_bus_error_exception_m[0:0]
    10/53: $0\bus_error_x[0:0]
    11/53: $0\csr_write_enable_x[0:0]
    12/53: $0\eret_m[0:0]
    13/53: $0\eret_x[0:0]
    14/53: $0\scall_x[0:0]
    15/53: $0\condition_x[2:0]
    16/53: $0\csr_x[2:0]
    17/53: $0\write_idx_w[4:0]
    18/53: $0\write_idx_m[4:0]
    19/53: $0\write_idx_x[4:0]
    20/53: $0\write_enable_w[0:0]
    21/53: $0\write_enable_m[0:0]
    22/53: $0\write_enable_x[0:0]
    23/53: $0\sign_extend_x[0:0]
    24/53: $0\m_bypass_enable_m[0:0]
    25/53: $0\m_bypass_enable_x[0:0]
    26/53: $0\x_bypass_enable_x[0:0]
    27/53: $0\w_result_sel_load_w[0:0]
    28/53: $0\w_result_sel_load_m[0:0]
    29/53: $0\w_result_sel_load_x[0:0]
    30/53: $0\m_result_sel_compare_m[0:0]
    31/53: $0\m_result_sel_compare_x[0:0]
    32/53: $0\x_result_sel_add_x[0:0]
    33/53: $0\x_result_sel_logic_x[0:0]
    34/53: $0\x_result_sel_sext_x[0:0]
    35/53: $0\x_result_sel_mc_arith_x[0:0]
    36/53: $0\x_result_sel_csr_x[0:0]
    37/53: $0\branch_target_m[29:0]
    38/53: $0\branch_target_x[29:0]
    39/53: $0\branch_predict_taken_m[0:0]
    40/53: $0\branch_predict_m[0:0]
    41/53: $0\branch_m[0:0]
    42/53: $0\branch_predict_taken_x[0:0]
    43/53: $0\branch_predict_x[0:0]
    44/53: $0\branch_x[0:0]
    45/53: $0\size_x[1:0]
    46/53: $0\store_m[0:0]
    47/53: $0\store_x[0:0]
    48/53: $0\load_m[0:0]
    49/53: $0\load_x[0:0]
    50/53: $0\operand_1_x[31:0]
    51/53: $0\operand_0_x[31:0]
    52/53: $0\adder_op_x_n[0:0]
    53/53: $0\adder_op_x[0:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
     1/5: $0\valid_w[0:0]
     2/5: $0\valid_m[0:0]
     3/5: $0\valid_x[0:0]
     4/5: $0\valid_d[0:0]
     5/5: $0\valid_f[0:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2604$2716'.
     1/3: $2\valid_a[0:0]
     2/3: $1\valid_a[0:0]
     3/3: $0\valid_a[0:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2555$2708'.
     1/1: $0\data_bus_error_seen[0:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2544$2705'.
     1/1: $0\cc[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2509$2698'.
     1/1: $0\eba[22:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2290$2697'.
     1/2: $1\csr_read_data_x[31:0]
     2/2: $0\csr_read_data_x[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1892$2563'.
     1/5: $4\eid_x[3:0]
     2/5: $3\eid_x[3:0]
     3/5: $2\eid_x[3:0]
     4/5: $1\eid_x[3:0]
     5/5: $0\eid_x[3:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1661$2492'.
     1/1: $0\w_result[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1651$2490'.
     1/1: $0\m_result[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1631$2485'.
     1/1: $0\x_result[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1615$2477'.
     1/2: $1\condition_met_x[0:0]
     2/2: $0\condition_met_x[0:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1581$2472'.
     1/3: $1\d_result_1[31:0]
     2/3: $0\d_result_1[31:0]
     3/3: $0\d_result_0[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1551$2463'.
     1/4: $3\bypass_data_1[31:0]
     2/4: $2\bypass_data_1[31:0]
     3/4: $1\bypass_data_1[31:0]
     4/4: $0\bypass_data_1[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1538$2459'.
     1/4: $3\bypass_data_0[31:0]
     2/4: $2\bypass_data_0[31:0]
     3/4: $1\bypass_data_0[31:0]
     4/4: $0\bypass_data_0[31:0]
Creating decoders for process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1519$2439'.
     1/2: $1\interlock[0:0]
     2/2: $0\interlock[0:0]
Creating decoders for process `\top.$proc$top.v:1180$2200'.
     1/1: $1\multiregimpl13_regs1[0:0]
Creating decoders for process `\top.$proc$top.v:1179$2199'.
     1/1: $1\multiregimpl13_regs0[0:0]
Creating decoders for process `\top.$proc$top.v:1178$2198'.
     1/1: $1\multiregimpl12_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1177$2197'.
     1/1: $1\multiregimpl12_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1176$2196'.
     1/1: $1\multiregimpl11_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1175$2195'.
     1/1: $1\multiregimpl11_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1174$2194'.
     1/1: $1\multiregimpl10_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1173$2193'.
     1/1: $1\multiregimpl10_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1172$2192'.
     1/1: $1\multiregimpl9_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1171$2191'.
     1/1: $1\multiregimpl9_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1170$2190'.
     1/1: $1\multiregimpl8_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1169$2189'.
     1/1: $1\multiregimpl8_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1168$2188'.
     1/1: $1\multiregimpl7_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1167$2187'.
     1/1: $1\multiregimpl7_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1166$2186'.
     1/1: $1\multiregimpl6_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1165$2185'.
     1/1: $1\multiregimpl6_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1164$2184'.
     1/1: $1\multiregimpl5_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1163$2183'.
     1/1: $1\multiregimpl5_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1162$2182'.
     1/1: $1\multiregimpl4_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1161$2181'.
     1/1: $1\multiregimpl4_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1160$2180'.
     1/1: $1\multiregimpl3_regs1[9:0]
Creating decoders for process `\top.$proc$top.v:1159$2179'.
     1/1: $1\multiregimpl3_regs0[9:0]
Creating decoders for process `\top.$proc$top.v:1158$2178'.
     1/1: $1\multiregimpl2_regs2[0:0]
Creating decoders for process `\top.$proc$top.v:1157$2177'.
     1/1: $1\multiregimpl2_regs1[0:0]
Creating decoders for process `\top.$proc$top.v:1156$2176'.
     1/1: $1\multiregimpl2_regs0[0:0]
Creating decoders for process `\top.$proc$top.v:1155$2175'.
     1/1: $1\multiregimpl1_regs2[0:0]
Creating decoders for process `\top.$proc$top.v:1154$2174'.
     1/1: $1\multiregimpl1_regs1[0:0]
Creating decoders for process `\top.$proc$top.v:1153$2173'.
     1/1: $1\multiregimpl1_regs0[0:0]
Creating decoders for process `\top.$proc$top.v:1151$2172'.
     1/1: $1\multiregimpl0_regs1[0:0]
Creating decoders for process `\top.$proc$top.v:1150$2171'.
     1/1: $1\multiregimpl0_regs0[0:0]
Creating decoders for process `\top.$proc$top.v:1149$2170'.
     1/1: $2\array_muxed[1:0]
Creating decoders for process `\top.$proc$top.v:1148$2169'.
     1/1: $1\rhs_array_muxed12[1:0]
Creating decoders for process `\top.$proc$top.v:1147$2168'.
     1/1: $1\rhs_array_muxed11[2:0]
Creating decoders for process `\top.$proc$top.v:1146$2167'.
     1/1: $1\rhs_array_muxed10[0:0]
Creating decoders for process `\top.$proc$top.v:1145$2166'.
     1/1: $1\rhs_array_muxed9[0:0]
Creating decoders for process `\top.$proc$top.v:1144$2165'.
     1/1: $1\rhs_array_muxed8[0:0]
Creating decoders for process `\top.$proc$top.v:1143$2164'.
     1/1: $1\rhs_array_muxed7[3:0]
Creating decoders for process `\top.$proc$top.v:1142$2163'.
     1/1: $1\rhs_array_muxed6[31:0]
Creating decoders for process `\top.$proc$top.v:1141$2162'.
     1/1: $1\rhs_array_muxed5[29:0]
Creating decoders for process `\top.$proc$top.v:1139$2161'.
     1/1: $1\rhs_array_muxed4[7:0]
Creating decoders for process `\top.$proc$top.v:1138$2160'.
     1/1: $1\rhs_array_muxed3[0:0]
Creating decoders for process `\top.$proc$top.v:1135$2159'.
     1/1: $1\rhs_array_muxed2[0:0]
Creating decoders for process `\top.$proc$top.v:1134$2158'.
     1/1: $1\rhs_array_muxed1[0:0]
Creating decoders for process `\top.$proc$top.v:1133$2157'.
     1/1: $1\lhs_array_muxed0[0:0]
Creating decoders for process `\top.$proc$top.v:1132$2156'.
     1/1: $1\rhs_array_muxed0[1:0]
Creating decoders for process `\top.$proc$top.v:1098$2155'.
     1/1: $1\interface6_bank_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:1081$2154'.
     1/1: $1\interface5_bank_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:1070$2153'.
     1/1: $1\interface4_bank_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:1026$2152'.
     1/1: $1\interface3_bank_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:1012$2151'.
     1/1: $1\interface2_bank_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:899$2150'.
     1/1: $1\interface1_bank_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:895$2149'.
     1/1: $1\sel_r[0:0]
Creating decoders for process `\top.$proc$top.v:891$2148'.
     1/1: $1\sram_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:862$2147'.
     1/1: $1\interface0_bank_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:858$2146'.
     1/1: $1\count[16:0]
Creating decoders for process `\top.$proc$top.v:855$2145'.
     1/1: $1\error[0:0]
Creating decoders for process `\top.$proc$top.v:854$2144'.
     1/1: $1\slave_sel_r[2:0]
Creating decoders for process `\top.$proc$top.v:853$2143'.
     1/1: $1\slave_sel[2:0]
Creating decoders for process `\top.$proc$top.v:852$2142'.
     1/1: $1\grant[0:0]
Creating decoders for process `\top.$proc$top.v:846$2141'.
     1/1: $1\shared_ack[0:0]
Creating decoders for process `\top.$proc$top.v:842$2140'.
     1/1: $1\shared_dat_r[31:0]
Creating decoders for process `\top.$proc$top.v:809$2139'.
     1/1: $1\usb_response_pid_next_value_ce2[0:0]
Creating decoders for process `\top.$proc$top.v:808$2138'.
     1/1: $1\usb_response_pid_next_value2[3:0]
Creating decoders for process `\top.$proc$top.v:807$2137'.
     1/1: $1\usb_transfer_tok_next_value_ce1[0:0]
Creating decoders for process `\top.$proc$top.v:806$2136'.
     1/1: $1\usb_transfer_tok_next_value1[1:0]
Creating decoders for process `\top.$proc$top.v:805$2135'.
     1/1: $1\usb_ep_addr_next_value_ce0[0:0]
Creating decoders for process `\top.$proc$top.v:804$2134'.
     1/1: $1\usb_ep_addr_next_value0[4:0]
Creating decoders for process `\top.$proc$top.v:803$2133'.
     1/1: $1\next_state[2:0]
Creating decoders for process `\top.$proc$top.v:802$2132'.
     1/1: $1\state[2:0]
Creating decoders for process `\top.$proc$top.v:801$2131'.
     1/1: $1\usbfstx_txnrziencoder_next_state[2:0]
Creating decoders for process `\top.$proc$top.v:800$2130'.
     1/1: $1\usbfstx_txnrziencoder_state[2:0]
Creating decoders for process `\top.$proc$top.v:799$2129'.
     1/1: $1\usbfstx_txbitstuffer_next_state[2:0]
Creating decoders for process `\top.$proc$top.v:798$2128'.
     1/1: $1\usbfstx_txbitstuffer_state[2:0]
Creating decoders for process `\top.$proc$top.v:797$2127'.
     1/1: $1\usbfstx_fsm_next_state[2:0]
Creating decoders for process `\top.$proc$top.v:796$2126'.
     1/1: $1\usbfstx_fsm_state[2:0]
Creating decoders for process `\top.$proc$top.v:795$2125'.
     1/1: $1\usbfsrx_fsm_next_state[2:0]
Creating decoders for process `\top.$proc$top.v:794$2124'.
     1/1: $1\usbfsrx_fsm_state[2:0]
Creating decoders for process `\top.$proc$top.v:793$2123'.
     1/1: $1\usbfsrx_rxpacketdetect_next_state[2:0]
Creating decoders for process `\top.$proc$top.v:792$2122'.
     1/1: $1\usbfsrx_rxpacketdetect_state[2:0]
Creating decoders for process `\top.$proc$top.v:791$2121'.
     1/1: $1\usbfsrx_rxbitstuffremover_next_state[2:0]
Creating decoders for process `\top.$proc$top.v:790$2120'.
     1/1: $1\usbfsrx_rxbitstuffremover_state[2:0]
Creating decoders for process `\top.$proc$top.v:789$2119'.
     1/1: $1\usbfsrx_rxnrzidecoder_next_state[0:0]
Creating decoders for process `\top.$proc$top.v:788$2118'.
     1/1: $1\usbfsrx_rxnrzidecoder_state[0:0]
Creating decoders for process `\top.$proc$top.v:787$2117'.
     1/1: $1\usbfsrx_rxclockdatarecovery_next_state[2:0]
Creating decoders for process `\top.$proc$top.v:786$2116'.
     1/1: $1\usbfsrx_rxclockdatarecovery_state[2:0]
Creating decoders for process `\top.$proc$top.v:780$2115'.
     1/1: $1\usb_endpointin2_we[0:0]
Creating decoders for process `\top.$proc$top.v:779$2114'.
     1/1: $0\usb_endpointin2_writable[0:0]
Creating decoders for process `\top.$proc$top.v:778$2113'.
     1/1: $1\usb_endpointin2_din[7:0]
Creating decoders for process `\top.$proc$top.v:776$2112'.
     1/1: $0\usb_endpointin2_ibuf_head_w[7:0]
Creating decoders for process `\top.$proc$top.v:765$2111'.
     1/1: $1\usb_endpointin2_graycounter5_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:764$2110'.
     1/1: $1\usb_endpointin2_graycounter5_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:762$2109'.
     1/1: $1\usb_endpointin2_graycounter5_q[9:0]
Creating decoders for process `\top.$proc$top.v:760$2108'.
     1/1: $1\usb_endpointin2_graycounter4_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:759$2107'.
     1/1: $1\usb_endpointin2_graycounter4_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:757$2106'.
     1/1: $1\usb_endpointin2_graycounter4_q[9:0]
Creating decoders for process `\top.$proc$top.v:749$2105'.
     1/1: $1\usb_endpointin2_dout[7:0]
Creating decoders for process `\top.$proc$top.v:748$2104'.
     1/1: $1\usb_endpointin2_readable[0:0]
Creating decoders for process `\top.$proc$top.v:747$2103'.
     1/1: $1\usb_endpointin2_re[0:0]
Creating decoders for process `\top.$proc$top.v:746$2102'.
     1/1: $1\usb_endpointin2_toggle[0:0]
Creating decoders for process `\top.$proc$top.v:744$2101'.
     1/1: $1\usb_endpointin2_dtb_we[0:0]
Creating decoders for process `\top.$proc$top.v:743$2100'.
     1/1: $1\usb_endpointin2_dtb_re[0:0]
Creating decoders for process `\top.$proc$top.v:741$2099'.
     1/1: $1\usb_endpointin2_dtb_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:740$2098'.
     1/1: $0\usb_endpointin2_reset[0:0]
Creating decoders for process `\top.$proc$top.v:736$2097'.
     1/1: $1\usb_endpointin2_respond_re[0:0]
Creating decoders for process `\top.$proc$top.v:734$2096'.
     1/1: $1\usb_endpointin2_respond_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:733$2095'.
     1/1: $1\usb_endpointin2_last_tok_status[1:0]
Creating decoders for process `\top.$proc$top.v:729$2094'.
     1/1: $1\usb_endpointin2_eventmanager2_re[0:0]
Creating decoders for process `\top.$proc$top.v:727$2093'.
     1/1: $1\usb_endpointin2_eventmanager2_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:726$2092'.
     1/1: $1\usb_endpointin2_eventmanager2_pending_w[1:0]
Creating decoders for process `\top.$proc$top.v:723$2091'.
     1/1: $1\usb_endpointin2_eventmanager2_status_w[1:0]
Creating decoders for process `\top.$proc$top.v:720$2090'.
     1/1: $1\usb_endpointin2_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:719$2089'.
     1/1: $1\usb_endpointin2_packet_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:718$2088'.
     1/1: $1\usb_endpointin2_packet_pending[0:0]
Creating decoders for process `\top.$proc$top.v:716$2087'.
     1/1: $1\usb_endpointin2_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:715$2086'.
     1/1: $0\usb_endpointin2_error_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:714$2085'.
     1/1: $1\usb_endpointin2_error_pending[0:0]
Creating decoders for process `\top.$proc$top.v:711$2084'.
     1/1: $1\usb_endpointout1_ibuf_re[0:0]
Creating decoders for process `\top.$proc$top.v:710$2083'.
     1/1: $0\usb_endpointout1_ibuf_readable[0:0]
Creating decoders for process `\top.$proc$top.v:709$2082'.
     1/1: $0\usb_endpointout1_ibuf_dout[7:0]
Creating decoders for process `\top.$proc$top.v:696$2081'.
     1/1: $1\usb_endpointout1_outbuf_graycounter3_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:695$2080'.
     1/1: $1\usb_endpointout1_outbuf_graycounter3_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:693$2079'.
     1/1: $1\usb_endpointout1_outbuf_graycounter3_q[9:0]
Creating decoders for process `\top.$proc$top.v:691$2078'.
     1/1: $1\usb_endpointout1_outbuf_graycounter2_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:690$2077'.
     1/1: $1\usb_endpointout1_outbuf_graycounter2_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:688$2076'.
     1/1: $1\usb_endpointout1_outbuf_graycounter2_q[9:0]
Creating decoders for process `\top.$proc$top.v:685$2075'.
     1/1: $1\usb_endpointout1_outbuf_asyncfifo1_din[7:0]
Creating decoders for process `\top.$proc$top.v:681$2074'.
     1/1: $1\usb_endpointout1_outbuf_asyncfifo1_we[0:0]
Creating decoders for process `\top.$proc$top.v:680$2073'.
     1/1: $1\usb_endpointout1_outbuf_dout[7:0]
Creating decoders for process `\top.$proc$top.v:679$2072'.
     1/1: $1\usb_endpointout1_outbuf_readable[0:0]
Creating decoders for process `\top.$proc$top.v:677$2071'.
     1/1: $1\usb_endpointout1_toggle[0:0]
Creating decoders for process `\top.$proc$top.v:675$2070'.
     1/1: $1\usb_endpointout1_dtb_we[0:0]
Creating decoders for process `\top.$proc$top.v:674$2069'.
     1/1: $1\usb_endpointout1_dtb_re[0:0]
Creating decoders for process `\top.$proc$top.v:672$2068'.
     1/1: $1\usb_endpointout1_dtb_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:671$2067'.
     1/1: $0\usb_endpointout1_reset[0:0]
Creating decoders for process `\top.$proc$top.v:667$2066'.
     1/1: $1\usb_endpointout1_respond_re[0:0]
Creating decoders for process `\top.$proc$top.v:665$2065'.
     1/1: $1\usb_endpointout1_respond_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:664$2064'.
     1/1: $1\usb_endpointout1_last_tok_status[1:0]
Creating decoders for process `\top.$proc$top.v:660$2063'.
     1/1: $1\usb_endpointout1_eventmanager1_re[0:0]
Creating decoders for process `\top.$proc$top.v:658$2062'.
     1/1: $1\usb_endpointout1_eventmanager1_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:657$2061'.
     1/1: $1\usb_endpointout1_eventmanager1_pending_w[1:0]
Creating decoders for process `\top.$proc$top.v:654$2060'.
     1/1: $1\usb_endpointout1_eventmanager1_status_w[1:0]
Creating decoders for process `\top.$proc$top.v:651$2059'.
     1/1: $1\usb_endpointout1_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:650$2058'.
     1/1: $1\usb_endpointout1_packet_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:649$2057'.
     1/1: $1\usb_endpointout1_packet_pending[0:0]
Creating decoders for process `\top.$proc$top.v:647$2056'.
     1/1: $1\usb_endpointout1_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:646$2055'.
     1/1: $0\usb_endpointout1_error_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:645$2054'.
     1/1: $1\usb_endpointout1_error_pending[0:0]
Creating decoders for process `\top.$proc$top.v:642$2053'.
     1/1: $1\usb_endpointin1_we[0:0]
Creating decoders for process `\top.$proc$top.v:641$2052'.
     1/1: $0\usb_endpointin1_writable[0:0]
Creating decoders for process `\top.$proc$top.v:640$2051'.
     1/1: $1\usb_endpointin1_din[7:0]
Creating decoders for process `\top.$proc$top.v:638$2050'.
     1/1: $0\usb_endpointin1_ibuf_head_w[7:0]
Creating decoders for process `\top.$proc$top.v:627$2049'.
     1/1: $1\usb_endpointin1_graycounter3_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:626$2048'.
     1/1: $1\usb_endpointin1_graycounter3_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:624$2047'.
     1/1: $1\usb_endpointin1_graycounter3_q[9:0]
Creating decoders for process `\top.$proc$top.v:622$2046'.
     1/1: $1\usb_endpointin1_graycounter2_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:621$2045'.
     1/1: $1\usb_endpointin1_graycounter2_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:619$2044'.
     1/1: $1\usb_endpointin1_graycounter2_q[9:0]
Creating decoders for process `\top.$proc$top.v:611$2043'.
     1/1: $1\usb_endpointin1_dout[7:0]
Creating decoders for process `\top.$proc$top.v:610$2042'.
     1/1: $1\usb_endpointin1_readable[0:0]
Creating decoders for process `\top.$proc$top.v:609$2041'.
     1/1: $1\usb_endpointin1_re[0:0]
Creating decoders for process `\top.$proc$top.v:608$2040'.
     1/1: $1\usb_endpointin1_toggle[0:0]
Creating decoders for process `\top.$proc$top.v:606$2039'.
     1/1: $1\usb_endpointin1_dtb_we[0:0]
Creating decoders for process `\top.$proc$top.v:605$2038'.
     1/1: $1\usb_endpointin1_dtb_re[0:0]
Creating decoders for process `\top.$proc$top.v:603$2037'.
     1/1: $1\usb_endpointin1_dtb_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:602$2036'.
     1/1: $0\usb_endpointin1_reset[0:0]
Creating decoders for process `\top.$proc$top.v:598$2035'.
     1/1: $1\usb_endpointin1_respond_re[0:0]
Creating decoders for process `\top.$proc$top.v:596$2034'.
     1/1: $1\usb_endpointin1_respond_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:595$2033'.
     1/1: $1\usb_endpointin1_last_tok_status[1:0]
Creating decoders for process `\top.$proc$top.v:591$2032'.
     1/1: $1\usb_endpointin1_eventmanager1_re[0:0]
Creating decoders for process `\top.$proc$top.v:589$2031'.
     1/1: $1\usb_endpointin1_eventmanager1_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:588$2030'.
     1/1: $1\usb_endpointin1_eventmanager1_pending_w[1:0]
Creating decoders for process `\top.$proc$top.v:585$2029'.
     1/1: $1\usb_endpointin1_eventmanager1_status_w[1:0]
Creating decoders for process `\top.$proc$top.v:582$2028'.
     1/1: $1\usb_endpointin1_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:581$2027'.
     1/1: $1\usb_endpointin1_packet_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:580$2026'.
     1/1: $1\usb_endpointin1_packet_pending[0:0]
Creating decoders for process `\top.$proc$top.v:578$2025'.
     1/1: $1\usb_endpointin1_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:577$2024'.
     1/1: $0\usb_endpointin1_error_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:576$2023'.
     1/1: $1\usb_endpointin1_error_pending[0:0]
Creating decoders for process `\top.$proc$top.v:573$2022'.
     1/1: $0\usb_oep_storage[0:0]
Creating decoders for process `\top.$proc$top.v:572$2021'.
     1/1: $1\usb_oep_status[1:0]
Creating decoders for process `\top.$proc$top.v:571$2020'.
     1/1: $1\usb_oep_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:570$2019'.
     1/1: $0\usb_oep_response[0:0]
Creating decoders for process `\top.$proc$top.v:569$2018'.
     1/1: $1\usb_oep_we[0:0]
Creating decoders for process `\top.$proc$top.v:568$2017'.
     1/1: $0\usb_oep_writable[0:0]
Creating decoders for process `\top.$proc$top.v:567$2016'.
     1/1: $1\usb_oep_din[7:0]
Creating decoders for process `\top.$proc$top.v:566$2015'.
     1/1: $1\usb_oep_re[0:0]
Creating decoders for process `\top.$proc$top.v:565$2014'.
     1/1: $0\usb_oep_readable[0:0]
Creating decoders for process `\top.$proc$top.v:564$2013'.
     1/1: $0\usb_oep_dout[7:0]
Creating decoders for process `\top.$proc$top.v:563$2012'.
     1/1: $1\usb_endpointin0_we[0:0]
Creating decoders for process `\top.$proc$top.v:562$2011'.
     1/1: $0\usb_endpointin0_writable[0:0]
Creating decoders for process `\top.$proc$top.v:561$2010'.
     1/1: $1\usb_endpointin0_din[7:0]
Creating decoders for process `\top.$proc$top.v:559$2009'.
     1/1: $0\usb_endpointin0_ibuf_head_w[7:0]
Creating decoders for process `\top.$proc$top.v:548$2008'.
     1/1: $1\usb_endpointin0_graycounter1_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:547$2007'.
     1/1: $1\usb_endpointin0_graycounter1_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:545$2006'.
     1/1: $1\usb_endpointin0_graycounter1_q[9:0]
Creating decoders for process `\top.$proc$top.v:543$2005'.
     1/1: $1\usb_endpointin0_graycounter0_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:542$2004'.
     1/1: $1\usb_endpointin0_graycounter0_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:540$2003'.
     1/1: $1\usb_endpointin0_graycounter0_q[9:0]
Creating decoders for process `\top.$proc$top.v:532$2002'.
     1/1: $1\usb_endpointin0_dout[7:0]
Creating decoders for process `\top.$proc$top.v:531$2001'.
     1/1: $1\usb_endpointin0_readable[0:0]
Creating decoders for process `\top.$proc$top.v:530$2000'.
     1/1: $1\usb_endpointin0_re[0:0]
Creating decoders for process `\top.$proc$top.v:529$1999'.
     1/1: $1\usb_endpointin0_toggle[0:0]
Creating decoders for process `\top.$proc$top.v:527$1998'.
     1/1: $1\usb_endpointin0_dtb_we[0:0]
Creating decoders for process `\top.$proc$top.v:526$1997'.
     1/1: $1\usb_endpointin0_dtb_re[0:0]
Creating decoders for process `\top.$proc$top.v:524$1996'.
     1/1: $1\usb_endpointin0_dtb_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:519$1995'.
     1/1: $1\usb_endpointin0_respond_re[0:0]
Creating decoders for process `\top.$proc$top.v:517$1994'.
     1/1: $1\usb_endpointin0_respond_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:516$1993'.
     1/1: $1\usb_endpointin0_last_tok_status[1:0]
Creating decoders for process `\top.$proc$top.v:512$1992'.
     1/1: $1\usb_endpointin0_eventmanager0_re[0:0]
Creating decoders for process `\top.$proc$top.v:510$1991'.
     1/1: $1\usb_endpointin0_eventmanager0_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:509$1990'.
     1/1: $1\usb_endpointin0_eventmanager0_pending_w[1:0]
Creating decoders for process `\top.$proc$top.v:506$1989'.
     1/1: $1\usb_endpointin0_eventmanager0_status_w[1:0]
Creating decoders for process `\top.$proc$top.v:503$1988'.
     1/1: $1\usb_endpointin0_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:502$1987'.
     1/1: $1\usb_endpointin0_packet_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:501$1986'.
     1/1: $1\usb_endpointin0_packet_pending[0:0]
Creating decoders for process `\top.$proc$top.v:499$1985'.
     1/1: $1\usb_endpointin0_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:498$1984'.
     1/1: $0\usb_endpointin0_error_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:497$1983'.
     1/1: $1\usb_endpointin0_error_pending[0:0]
Creating decoders for process `\top.$proc$top.v:494$1982'.
     1/1: $1\usb_endpointout0_ibuf_re[0:0]
Creating decoders for process `\top.$proc$top.v:493$1981'.
     1/1: $0\usb_endpointout0_ibuf_readable[0:0]
Creating decoders for process `\top.$proc$top.v:492$1980'.
     1/1: $0\usb_endpointout0_ibuf_dout[7:0]
Creating decoders for process `\top.$proc$top.v:479$1979'.
     1/1: $1\usb_endpointout0_outbuf_graycounter1_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:478$1978'.
     1/1: $1\usb_endpointout0_outbuf_graycounter1_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:476$1977'.
     1/1: $1\usb_endpointout0_outbuf_graycounter1_q[9:0]
Creating decoders for process `\top.$proc$top.v:474$1976'.
     1/1: $1\usb_endpointout0_outbuf_graycounter0_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:473$1975'.
     1/1: $1\usb_endpointout0_outbuf_graycounter0_q_binary[9:0]
Creating decoders for process `\top.$proc$top.v:471$1974'.
     1/1: $1\usb_endpointout0_outbuf_graycounter0_q[9:0]
Creating decoders for process `\top.$proc$top.v:468$1973'.
     1/1: $1\usb_endpointout0_outbuf_asyncfifo0_din[7:0]
Creating decoders for process `\top.$proc$top.v:464$1972'.
     1/1: $1\usb_endpointout0_outbuf_asyncfifo0_we[0:0]
Creating decoders for process `\top.$proc$top.v:463$1971'.
     1/1: $1\usb_endpointout0_outbuf_dout[7:0]
Creating decoders for process `\top.$proc$top.v:462$1970'.
     1/1: $1\usb_endpointout0_outbuf_readable[0:0]
Creating decoders for process `\top.$proc$top.v:460$1969'.
     1/1: $1\usb_endpointout0_toggle[0:0]
Creating decoders for process `\top.$proc$top.v:458$1968'.
     1/1: $1\usb_endpointout0_dtb_we[0:0]
Creating decoders for process `\top.$proc$top.v:457$1967'.
     1/1: $1\usb_endpointout0_dtb_re[0:0]
Creating decoders for process `\top.$proc$top.v:455$1966'.
     1/1: $1\usb_endpointout0_dtb_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:450$1965'.
     1/1: $1\usb_endpointout0_respond_re[0:0]
Creating decoders for process `\top.$proc$top.v:448$1964'.
     1/1: $1\usb_endpointout0_respond_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:447$1963'.
     1/1: $1\usb_endpointout0_last_tok_status[1:0]
Creating decoders for process `\top.$proc$top.v:443$1962'.
     1/1: $1\usb_endpointout0_eventmanager0_re[0:0]
Creating decoders for process `\top.$proc$top.v:441$1961'.
     1/1: $1\usb_endpointout0_eventmanager0_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:440$1960'.
     1/1: $1\usb_endpointout0_eventmanager0_pending_w[1:0]
Creating decoders for process `\top.$proc$top.v:437$1959'.
     1/1: $1\usb_endpointout0_eventmanager0_status_w[1:0]
Creating decoders for process `\top.$proc$top.v:434$1958'.
     1/1: $1\usb_endpointout0_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:433$1957'.
     1/1: $1\usb_endpointout0_packet_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:432$1956'.
     1/1: $1\usb_endpointout0_packet_pending[0:0]
Creating decoders for process `\top.$proc$top.v:430$1955'.
     1/1: $1\usb_endpointout0_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:429$1954'.
     1/1: $0\usb_endpointout0_error_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:428$1953'.
     1/1: $1\usb_endpointout0_error_pending[0:0]
Creating decoders for process `\top.$proc$top.v:424$1952'.
     1/1: $1\usb_signal_is_el1[0:0]
Creating decoders for process `\top.$proc$top.v:422$1951'.
     1/1: $1\usb_signal_is_el0[0:0]
Creating decoders for process `\top.$proc$top.v:421$1950'.
     1/1: $1\usb_response_pid[3:0]
Creating decoders for process `\top.$proc$top.v:419$1949'.
     1/1: $1\usb_data_toggle_bit[0:0]
Creating decoders for process `\top.$proc$top.v:416$1948'.
     1/1: $1\usb_data_send_get[0:0]
Creating decoders for process `\top.$proc$top.v:413$1947'.
     1/1: $1\usb_data_recv_put[0:0]
Creating decoders for process `\top.$proc$top.v:411$1946'.
     1/1: $1\usb_ep_addr[4:0]
Creating decoders for process `\top.$proc$top.v:406$1945'.
     1/1: $1\usb_transfer_abort[0:0]
Creating decoders for process `\top.$proc$top.v:405$1944'.
     1/1: $1\usb_transfer_commit0[0:0]
Creating decoders for process `\top.$proc$top.v:404$1943'.
     1/1: $1\usb_transfer_setup[0:0]
Creating decoders for process `\top.$proc$top.v:403$1942'.
     1/1: $1\usb_transfer_tok[1:0]
Creating decoders for process `\top.$proc$top.v:402$1941'.
     1/1: $1\usb_transfer_start[0:0]
Creating decoders for process `\top.$proc$top.v:401$1940'.
     1/1: $0\usb_reset[0:0]
Creating decoders for process `\top.$proc$top.v:400$1939'.
     1/1: $1\usb_tx_o_oe[0:0]
Creating decoders for process `\top.$proc$top.v:399$1938'.
     1/1: $1\usb_tx_o_usbn[0:0]
Creating decoders for process `\top.$proc$top.v:398$1937'.
     1/1: $1\usb_tx_o_usbp[0:0]
Creating decoders for process `\top.$proc$top.v:397$1936'.
     1/1: $1\usb_tx_o_pkt_end[0:0]
Creating decoders for process `\top.$proc$top.v:396$1935'.
     1/1: $1\usb_tx_o_data_get[0:0]
Creating decoders for process `\top.$proc$top.v:395$1934'.
     1/1: $1\usb_tx_nrzi_o_oe[0:0]
Creating decoders for process `\top.$proc$top.v:394$1933'.
     1/1: $1\usb_tx_nrzi_o_usbn[0:0]
Creating decoders for process `\top.$proc$top.v:393$1932'.
     1/1: $1\usb_tx_nrzi_o_usbp[0:0]
Creating decoders for process `\top.$proc$top.v:392$1931'.
     1/1: $1\usb_tx_nrzi_oe[0:0]
Creating decoders for process `\top.$proc$top.v:391$1930'.
     1/1: $1\usb_tx_nrzi_usbn[0:0]
Creating decoders for process `\top.$proc$top.v:390$1929'.
     1/1: $1\usb_tx_nrzi_usbp[0:0]
Creating decoders for process `\top.$proc$top.v:389$1928'.
     1/1: $1\usb_tx_bitstuffer_o_oe[0:0]
Creating decoders for process `\top.$proc$top.v:388$1927'.
     1/1: $1\usb_tx_bitstuffer_o_se0[0:0]
Creating decoders for process `\top.$proc$top.v:387$1926'.
     1/1: $1\usb_tx_bitstuffer_o_data[0:0]
Creating decoders for process `\top.$proc$top.v:385$1925'.
     1/1: $1\usb_tx_bitstuffer_stuff_bit[0:0]
Creating decoders for process `\top.$proc$top.v:384$1924'.
     1/1: $1\usb_tx_mux_stuff_bit_strobe[0:0]
Creating decoders for process `\top.$proc$top.v:383$1923'.
     1/1: $1\usb_tx_mux_stuff_se0[0:0]
Creating decoders for process `\top.$proc$top.v:382$1922'.
     1/1: $1\usb_tx_mux_stuff_data[0:0]
Creating decoders for process `\top.$proc$top.v:381$1921'.
     1/1: $1\usb_tx_mux_stuff_oe[0:0]
Creating decoders for process `\top.$proc$top.v:380$1920'.
     1/1: $1\usb_tx_pid_is_data[0:0]
Creating decoders for process `\top.$proc$top.v:379$1919'.
     1/1: $1\usb_tx_crc16_shifter_not_empty[0:0]
Creating decoders for process `\top.$proc$top.v:376$1918'.
     1/1: $1\usb_tx_crc16_shifter_shifter[16:0]
Creating decoders for process `\top.$proc$top.v:375$1917'.
     1/1: $1\usb_tx_o_crc[15:0]
Creating decoders for process `\top.$proc$top.v:373$1916'.
     1/1: $1\usb_tx_crc[15:0]
Creating decoders for process `\top.$proc$top.v:372$1915'.
     1/1: $1\usb_tx_data_shifter_not_empty[0:0]
Creating decoders for process `\top.$proc$top.v:369$1914'.
     1/1: $1\usb_tx_data_shifter_shifter[8:0]
Creating decoders for process `\top.$proc$top.v:368$1913'.
     1/1: $1\usb_tx_pid_shifter_not_empty[0:0]
Creating decoders for process `\top.$proc$top.v:365$1912'.
     1/1: $1\usb_tx_pid_shifter_shifter[8:0]
Creating decoders for process `\top.$proc$top.v:364$1911'.
     1/1: $1\usb_tx_sync_shifter_not_empty[0:0]
Creating decoders for process `\top.$proc$top.v:361$1910'.
     1/1: $1\usb_tx_sync_shifter_shifter[8:0]
Creating decoders for process `\top.$proc$top.v:360$1909'.
     1/1: $1\usb_tx_pkt_end[0:0]
Creating decoders for process `\top.$proc$top.v:359$1908'.
     1/1: $1\usb_tx_shift_crc16[0:0]
Creating decoders for process `\top.$proc$top.v:358$1907'.
     1/1: $1\usb_tx_load_crc16[0:0]
Creating decoders for process `\top.$proc$top.v:357$1906'.
     1/1: $1\usb_tx_shift_data[0:0]
Creating decoders for process `\top.$proc$top.v:356$1905'.
     1/1: $1\usb_tx_load_data[0:0]
Creating decoders for process `\top.$proc$top.v:355$1904'.
     1/1: $1\usb_tx_shift_eop[0:0]
Creating decoders for process `\top.$proc$top.v:354$1903'.
     1/1: $1\usb_tx_shift_pid[0:0]
Creating decoders for process `\top.$proc$top.v:353$1902'.
     1/1: $1\usb_tx_shift_sync[0:0]
Creating decoders for process `\top.$proc$top.v:352$1901'.
     1/1: $1\usb_tx_pkt_active[0:0]
Creating decoders for process `\top.$proc$top.v:348$1900'.
     1/1: $1\usb_tx_i_pid[3:0]
Creating decoders for process `\top.$proc$top.v:347$1899'.
     1/1: $1\usb_tx_i_pkt_start[0:0]
Creating decoders for process `\top.$proc$top.v:346$1898'.
     1/1: $1\usb_rx_o_ep[3:0]
Creating decoders for process `\top.$proc$top.v:345$1897'.
     1/1: $1\usb_rx_o_addr[6:0]
Creating decoders for process `\top.$proc$top.v:344$1896'.
     1/1: $1\usb_rx_o_pid[3:0]
Creating decoders for process `\top.$proc$top.v:343$1895'.
     1/1: $1\usb_rx_data_n1[7:0]
Creating decoders for process `\top.$proc$top.v:342$1894'.
     1/1: $1\usb_rx_data_n0[7:0]
Creating decoders for process `\top.$proc$top.v:341$1893'.
     1/1: $1\usb_rx_end_data[0:0]
Creating decoders for process `\top.$proc$top.v:340$1892'.
     1/1: $1\usb_rx_put_data[0:0]
Creating decoders for process `\top.$proc$top.v:339$1891'.
     1/1: $1\usb_rx_start_data[0:0]
Creating decoders for process `\top.$proc$top.v:338$1890'.
     1/1: $1\usb_rx_end_token[0:0]
Creating decoders for process `\top.$proc$top.v:337$1889'.
     1/1: $1\usb_rx_start_token[0:0]
Creating decoders for process `\top.$proc$top.v:336$1888'.
     1/1: $1\usb_rx_end_handshake[0:0]
Creating decoders for process `\top.$proc$top.v:335$1887'.
     1/1: $1\usb_rx_end_pid[0:0]
Creating decoders for process `\top.$proc$top.v:334$1886'.
     1/1: $1\usb_rx_start_tok[0:0]
Creating decoders for process `\top.$proc$top.v:333$1885'.
     1/1: $1\usb_rx_o_put[0:0]
Creating decoders for process `\top.$proc$top.v:330$1884'.
     1/1: $1\usb_rx_shift_reg[8:0]
Creating decoders for process `\top.$proc$top.v:329$1883'.
     1/1: $1\usb_rx_i_reset[0:0]
Creating decoders for process `\top.$proc$top.v:328$1882'.
     1/1: $1\usb_rx_pkt_end1[0:0]
Creating decoders for process `\top.$proc$top.v:327$1881'.
     1/1: $1\usb_rx_pkt_active1[0:0]
Creating decoders for process `\top.$proc$top.v:326$1880'.
     1/1: $1\usb_rx_o_pkt_end[0:0]
Creating decoders for process `\top.$proc$top.v:325$1879'.
     1/1: $1\usb_rx_o_pkt_active[0:0]
Creating decoders for process `\top.$proc$top.v:324$1878'.
     1/1: $1\usb_rx_o_pkt_start[0:0]
Creating decoders for process `\top.$proc$top.v:323$1877'.
     1/1: $1\usb_rx_pkt_end0[0:0]
Creating decoders for process `\top.$proc$top.v:322$1876'.
     1/1: $1\usb_rx_pkt_active0[0:0]
Creating decoders for process `\top.$proc$top.v:321$1875'.
     1/1: $1\usb_rx_pkt_start[0:0]
Creating decoders for process `\top.$proc$top.v:320$1874'.
     1/1: $1\usb_rx_bitstuff_error[0:0]
Creating decoders for process `\top.$proc$top.v:319$1873'.
     1/1: $1\usb_rx_se0[0:0]
Creating decoders for process `\top.$proc$top.v:318$1872'.
     1/1: $1\usb_rx_data[0:0]
Creating decoders for process `\top.$proc$top.v:317$1871'.
     1/1: $1\usb_rx_valid[0:0]
Creating decoders for process `\top.$proc$top.v:316$1870'.
     1/1: $1\usb_rx_bitstuff_o_bitstuff_error[0:0]
Creating decoders for process `\top.$proc$top.v:315$1869'.
     1/1: $1\usb_rx_bitstuff_o_se0[0:0]
Creating decoders for process `\top.$proc$top.v:314$1868'.
     1/1: $1\usb_rx_bitstuff_o_data[0:0]
Creating decoders for process `\top.$proc$top.v:313$1867'.
     1/1: $1\usb_rx_bitstuff_o_valid[0:0]
Creating decoders for process `\top.$proc$top.v:312$1866'.
     1/1: $1\usb_rx_bitstuff_drop_bit[0:0]
Creating decoders for process `\top.$proc$top.v:311$1865'.
     1/1: $1\usb_rx_nrzi_o_se0[0:0]
Creating decoders for process `\top.$proc$top.v:310$1864'.
     1/1: $1\usb_rx_nrzi_o_data1[0:0]
Creating decoders for process `\top.$proc$top.v:309$1863'.
     1/1: $1\usb_rx_nrzi_o_valid1[0:0]
Creating decoders for process `\top.$proc$top.v:308$1862'.
     1/1: $1\usb_rx_nrzi_o_data0[0:0]
Creating decoders for process `\top.$proc$top.v:307$1861'.
     1/1: $1\usb_rx_nrzi_o_valid0[0:0]
Creating decoders for process `\top.$proc$top.v:306$1860'.
     1/1: $1\usb_rx_line_state_se11[0:0]
Creating decoders for process `\top.$proc$top.v:305$1859'.
     1/1: $1\usb_rx_line_state_se01[0:0]
Creating decoders for process `\top.$proc$top.v:304$1858'.
     1/1: $1\usb_rx_line_state_dk1[0:0]
Creating decoders for process `\top.$proc$top.v:303$1857'.
     1/1: $1\usb_rx_line_state_dj1[0:0]
Creating decoders for process `\top.$proc$top.v:302$1856'.
     1/1: $1\usb_rx_line_state_valid[0:0]
Creating decoders for process `\top.$proc$top.v:301$1855'.
     1/1: $1\usb_rx_line_state_phase[1:0]
Creating decoders for process `\top.$proc$top.v:300$1854'.
     1/1: $1\usb_rx_line_state_se10[0:0]
Creating decoders for process `\top.$proc$top.v:299$1853'.
     1/1: $1\usb_rx_line_state_se00[0:0]
Creating decoders for process `\top.$proc$top.v:298$1852'.
     1/1: $1\usb_rx_line_state_dk0[0:0]
Creating decoders for process `\top.$proc$top.v:297$1851'.
     1/1: $1\usb_rx_line_state_dj0[0:0]
Creating decoders for process `\top.$proc$top.v:296$1850'.
     1/1: $1\usb_rx_line_state_dt[0:0]
Creating decoders for process `\top.$proc$top.v:292$1849'.
     1/1: $1\usb_pullup_re[0:0]
Creating decoders for process `\top.$proc$top.v:290$1848'.
     1/1: $1\usb_pullup_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:286$1847'.
     1/1: $1\usb_iobuf_usb_n_rx[0:0]
Creating decoders for process `\top.$proc$top.v:285$1846'.
     1/1: $1\usb_iobuf_usb_p_rx[0:0]
Creating decoders for process `\top.$proc$top.v:281$1845'.
     1/1: $1\usbsoc_spiflash_counter[7:0]
Creating decoders for process `\top.$proc$top.v:280$1844'.
     1/1: $1\usbsoc_spiflash_miso1[0:0]
Creating decoders for process `\top.$proc$top.v:279$1843'.
     1/1: $1\usbsoc_spiflash_i[0:0]
Creating decoders for process `\top.$proc$top.v:278$1842'.
     1/1: $1\usbsoc_spiflash_sr[31:0]
Creating decoders for process `\top.$proc$top.v:277$1841'.
     1/1: $1\usbsoc_spiflash_clk1[0:0]
Creating decoders for process `\top.$proc$top.v:276$1840'.
     1/1: $1\usbsoc_spiflash_cs_n1[0:0]
Creating decoders for process `\top.$proc$top.v:275$1839'.
     1/1: $1\usbsoc_spiflash_bitbang_en_re[0:0]
Creating decoders for process `\top.$proc$top.v:273$1838'.
     1/1: $1\usbsoc_spiflash_bitbang_en_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:272$1837'.
     1/1: $1\usbsoc_spiflash_miso_status[0:0]
Creating decoders for process `\top.$proc$top.v:271$1836'.
     1/1: $1\usbsoc_spiflash_bitbang_re[0:0]
Creating decoders for process `\top.$proc$top.v:269$1835'.
     1/1: $1\usbsoc_spiflash_bitbang_storage_full[3:0]
Creating decoders for process `\top.$proc$top.v:268$1834'.
     1/1: $0\usbsoc_spiflash_bus_err[0:0]
Creating decoders for process `\top.$proc$top.v:264$1833'.
     1/1: $1\usbsoc_spiflash_bus_ack[0:0]
Creating decoders for process `\top.$proc$top.v:254$1832'.
     1/1: $1\usbsoc_reset_delay[11:0]
Creating decoders for process `\top.$proc$top.v:251$1831'.
     1/1: $0\usbsoc_reset[0:0]
Creating decoders for process `\top.$proc$top.v:250$1830'.
     1/1: $0\usb_48_rst[0:0]
Creating decoders for process `\top.$proc$top.v:246$1829'.
     1/1: $1\usbsoc_usbsoc_timer0_value[31:0]
Creating decoders for process `\top.$proc$top.v:242$1828'.
     1/1: $1\usbsoc_usbsoc_timer0_eventmanager_re[0:0]
Creating decoders for process `\top.$proc$top.v:240$1827'.
     1/1: $1\usbsoc_usbsoc_timer0_eventmanager_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:233$1826'.
     1/1: $1\usbsoc_usbsoc_timer0_zero_old_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:232$1825'.
     1/1: $1\usbsoc_usbsoc_timer0_zero_clear[0:0]
Creating decoders for process `\top.$proc$top.v:230$1824'.
     1/1: $1\usbsoc_usbsoc_timer0_zero_pending[0:0]
Creating decoders for process `\top.$proc$top.v:227$1823'.
     1/1: $1\usbsoc_usbsoc_timer0_value_status[31:0]
Creating decoders for process `\top.$proc$top.v:226$1822'.
     1/1: $0\usbsoc_usbsoc_timer0_update_value_w[0:0]
Creating decoders for process `\top.$proc$top.v:223$1821'.
     1/1: $1\usbsoc_usbsoc_timer0_en_re[0:0]
Creating decoders for process `\top.$proc$top.v:221$1820'.
     1/1: $1\usbsoc_usbsoc_timer0_en_storage_full[0:0]
Creating decoders for process `\top.$proc$top.v:220$1819'.
     1/1: $1\usbsoc_usbsoc_timer0_reload_re[0:0]
Creating decoders for process `\top.$proc$top.v:218$1818'.
     1/1: $1\usbsoc_usbsoc_timer0_reload_storage_full[31:0]
Creating decoders for process `\top.$proc$top.v:217$1817'.
     1/1: $1\usbsoc_usbsoc_timer0_load_re[0:0]
Creating decoders for process `\top.$proc$top.v:215$1816'.
     1/1: $1\usbsoc_usbsoc_timer0_load_storage_full[31:0]
Creating decoders for process `\top.$proc$top.v:214$1815'.
     1/1: $0\usbsoc_usbsoc_uart_reset[0:0]
Creating decoders for process `\top.$proc$top.v:199$1814'.
     1/1: $1\usbsoc_usbsoc_uart_rx_fifo_wrport_adr[3:0]
Creating decoders for process `\top.$proc$top.v:198$1813'.
     1/1: $1\usbsoc_usbsoc_uart_rx_fifo_consume[3:0]
Creating decoders for process `\top.$proc$top.v:197$1812'.
     1/1: $1\usbsoc_usbsoc_uart_rx_fifo_produce[3:0]
Creating decoders for process `\top.$proc$top.v:196$1811'.
     1/1: $0\usbsoc_usbsoc_uart_rx_fifo_replace[0:0]
Creating decoders for process `\top.$proc$top.v:195$1810'.
     1/1: $1\usbsoc_usbsoc_uart_rx_fifo_level0[4:0]
Creating decoders for process `\top.$proc$top.v:188$1809'.
     1/1: $1\usbsoc_usbsoc_uart_rx_fifo_readable[0:0]
Creating decoders for process `\top.$proc$top.v:162$1808'.
     1/1: $1\usbsoc_usbsoc_uart_tx_fifo_wrport_adr[3:0]
Creating decoders for process `\top.$proc$top.v:161$1807'.
     1/1: $1\usbsoc_usbsoc_uart_tx_fifo_consume[3:0]
Creating decoders for process `\top.$proc$top.v:160$1806'.
     1/1: $1\usbsoc_usbsoc_uart_tx_fifo_produce[3:0]
Creating decoders for process `\top.$proc$top.v:159$1805'.
     1/1: $0\usbsoc_usbsoc_uart_tx_fifo_replace[0:0]
Creating decoders for process `\top.$proc$top.v:158$1804'.
     1/1: $1\usbsoc_usbsoc_uart_tx_fifo_level0[4:0]
Creating decoders for process `\top.$proc$top.v:151$1803'.
     1/1: $1\usbsoc_usbsoc_uart_tx_fifo_readable[0:0]
Creating decoders for process `\top.$proc$top.v:143$1802'.
     1/1: $0\usbsoc_usbsoc_uart_tx_fifo_sink_last[0:0]
Creating decoders for process `\top.$proc$top.v:142$1801'.
     1/1: $0\usbsoc_usbsoc_uart_tx_fifo_sink_first[0:0]
Creating decoders for process `\top.$proc$top.v:136$1800'.
     1/1: $1\usbsoc_usbsoc_uart_eventmanager_re[0:0]
Creating decoders for process `\top.$proc$top.v:134$1799'.
     1/1: $1\usbsoc_usbsoc_uart_eventmanager_storage_full[1:0]
Creating decoders for process `\top.$proc$top.v:133$1798'.
     1/1: $1\usbsoc_usbsoc_uart_eventmanager_pending_w[1:0]
Creating decoders for process `\top.$proc$top.v:130$1797'.
     1/1: $1\usbsoc_usbsoc_uart_eventmanager_status_w[1:0]
Creating decoders for process `\top.$proc$top.v:127$1796'.
     1/1: $1\usbsoc_usbsoc_uart_rx_old_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:126$1795'.
     1/1: $1\usbsoc_usbsoc_uart_rx_clear[0:0]
Creating decoders for process `\top.$proc$top.v:124$1794'.
     1/1: $1\usbsoc_usbsoc_uart_rx_pending[0:0]
Creating decoders for process `\top.$proc$top.v:122$1793'.
     1/1: $1\usbsoc_usbsoc_uart_tx_old_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:121$1792'.
     1/1: $1\usbsoc_usbsoc_uart_tx_clear[0:0]
Creating decoders for process `\top.$proc$top.v:119$1791'.
     1/1: $1\usbsoc_usbsoc_uart_tx_pending[0:0]
Creating decoders for process `\top.$proc$top.v:111$1790'.
     1/1: $1\usbsoc_usbsoc_uart_phy_rx_busy[0:0]
Creating decoders for process `\top.$proc$top.v:110$1789'.
     1/1: $1\usbsoc_usbsoc_uart_phy_rx_bitcount[3:0]
Creating decoders for process `\top.$proc$top.v:109$1788'.
     1/1: $1\usbsoc_usbsoc_uart_phy_rx_reg[7:0]
Creating decoders for process `\top.$proc$top.v:108$1787'.
     1/1: $1\usbsoc_usbsoc_uart_phy_rx_r[0:0]
Creating decoders for process `\top.$proc$top.v:106$1786'.
     1/1: $1\usbsoc_usbsoc_uart_phy_phase_accumulator_rx[31:0]
Creating decoders for process `\top.$proc$top.v:105$1785'.
     1/1: $1\usbsoc_usbsoc_uart_phy_uart_clk_rxen[0:0]
Creating decoders for process `\top.$proc$top.v:104$1784'.
     1/1: $1\usbsoc_usbsoc_uart_phy_source_payload_data[7:0]
Creating decoders for process `\top.$proc$top.v:103$1783'.
     1/1: $0\usbsoc_usbsoc_uart_phy_source_last[0:0]
Creating decoders for process `\top.$proc$top.v:102$1782'.
     1/1: $0\usbsoc_usbsoc_uart_phy_source_first[0:0]
Creating decoders for process `\top.$proc$top.v:100$1781'.
     1/1: $1\usbsoc_usbsoc_uart_phy_source_valid[0:0]
Creating decoders for process `\top.$proc$top.v:99$1780'.
     1/1: $1\usbsoc_usbsoc_uart_phy_tx_busy[0:0]
Creating decoders for process `\top.$proc$top.v:98$1779'.
     1/1: $1\usbsoc_usbsoc_uart_phy_tx_bitcount[3:0]
Creating decoders for process `\top.$proc$top.v:97$1778'.
     1/1: $1\usbsoc_usbsoc_uart_phy_tx_reg[7:0]
Creating decoders for process `\top.$proc$top.v:96$1777'.
     1/1: $1\usbsoc_usbsoc_uart_phy_phase_accumulator_tx[31:0]
Creating decoders for process `\top.$proc$top.v:95$1776'.
     1/1: $1\usbsoc_usbsoc_uart_phy_uart_clk_txen[0:0]
Creating decoders for process `\top.$proc$top.v:91$1775'.
     1/1: $1\usbsoc_usbsoc_uart_phy_sink_ready[0:0]
Creating decoders for process `\top.$proc$top.v:89$1774'.
     1/1: $1\usbsoc_usbsoc_uart_phy_re[0:0]
Creating decoders for process `\top.$proc$top.v:87$1773'.
     1/1: $1\usbsoc_usbsoc_uart_phy_storage_full[31:0]
Creating decoders for process `\top.$proc$top.v:86$1772'.
     1/1: $1\usbsoc_usbsoc_counter[1:0]
Creating decoders for process `\top.$proc$top.v:85$1771'.
     1/1: $0\usbsoc_usbsoc_bus_wishbone_err[0:0]
Creating decoders for process `\top.$proc$top.v:81$1770'.
     1/1: $1\usbsoc_usbsoc_bus_wishbone_ack[0:0]
Creating decoders for process `\top.$proc$top.v:77$1769'.
     1/1: $1\usbsoc_usbsoc_bus_wishbone_dat_r[31:0]
Creating decoders for process `\top.$proc$top.v:73$1768'.
     1/1: $1\usbsoc_usbsoc_interface_dat_w[7:0]
Creating decoders for process `\top.$proc$top.v:72$1767'.
     1/1: $1\usbsoc_usbsoc_interface_we[0:0]
Creating decoders for process `\top.$proc$top.v:71$1766'.
     1/1: $1\usbsoc_usbsoc_interface_adr[13:0]
Creating decoders for process `\top.$proc$top.v:69$1765'.
     1/1: $1\usbsoc_usbsoc_sram_we[3:0]
Creating decoders for process `\top.$proc$top.v:66$1764'.
     1/1: $0\usbsoc_usbsoc_sram_bus_err[0:0]
Creating decoders for process `\top.$proc$top.v:62$1763'.
     1/1: $1\usbsoc_usbsoc_sram_bus_ack[0:0]
Creating decoders for process `\top.$proc$top.v:53$1762'.
     1/1: $1\usbsoc_usbsoc_lm32_interrupt[31:0]
Creating decoders for process `\top.$proc$top.v:29$1761'.
     1/1: $1\usbsoc_usbsoc_ctrl_bus_errors[31:0]
Creating decoders for process `\top.$proc$top.v:25$1760'.
     1/1: $1\usbsoc_usbsoc_ctrl_re[0:0]
Creating decoders for process `\top.$proc$top.v:23$1759'.
     1/1: $1\usbsoc_usbsoc_ctrl_storage_full[31:0]
Creating decoders for process `\top.$proc$top.v:22$1758'.
     1/1: $0\usbsoc_usbsoc_ctrl_reset_reset_w[0:0]
Creating decoders for process `\top.$proc$top.v:4876$1743'.
     1/1: $0\memadr_11[8:0]
Creating decoders for process `\top.$proc$top.v:4870$1739'.
     1/4: $0\memadr_10[8:0]
     2/4: $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742
     3/4: $0$memwr$\storage_6$top.v:4872$786_DATA[7:0]$1741
     4/4: $0$memwr$\storage_6$top.v:4872$786_ADDR[8:0]$1740
Creating decoders for process `\top.$proc$top.v:4860$1736'.
     1/1: $0\memadr_9[8:0]
Creating decoders for process `\top.$proc$top.v:4854$1732'.
     1/4: $0\memadr_8[8:0]
     2/4: $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735
     3/4: $0$memwr$\storage_5$top.v:4856$785_DATA[7:0]$1734
     4/4: $0$memwr$\storage_5$top.v:4856$785_ADDR[8:0]$1733
Creating decoders for process `\top.$proc$top.v:4844$1729'.
     1/1: $0\memadr_7[8:0]
Creating decoders for process `\top.$proc$top.v:4838$1725'.
     1/4: $0\memadr_6[8:0]
     2/4: $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728
     3/4: $0$memwr$\storage_4$top.v:4840$784_DATA[7:0]$1727
     4/4: $0$memwr$\storage_4$top.v:4840$784_ADDR[8:0]$1726
Creating decoders for process `\top.$proc$top.v:4828$1722'.
     1/1: $0\memadr_5[8:0]
Creating decoders for process `\top.$proc$top.v:4822$1718'.
     1/4: $0\memadr_4[8:0]
     2/4: $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721
     3/4: $0$memwr$\storage_3$top.v:4824$783_DATA[7:0]$1720
     4/4: $0$memwr$\storage_3$top.v:4824$783_ADDR[8:0]$1719
Creating decoders for process `\top.$proc$top.v:4812$1715'.
     1/1: $0\memadr_3[8:0]
Creating decoders for process `\top.$proc$top.v:4806$1711'.
     1/4: $0\memadr_2[8:0]
     2/4: $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714
     3/4: $0$memwr$\storage_2$top.v:4808$782_DATA[7:0]$1713
     4/4: $0$memwr$\storage_2$top.v:4808$782_ADDR[8:0]$1712
Creating decoders for process `\top.$proc$top.v:4753$1709'.
     1/1: $0\memadr_1[2:0]
Creating decoders for process `\top.$proc$top.v:4743$1707'.
     1/1: $0\memdat_3[9:0]
Creating decoders for process `\top.$proc$top.v:4737$1702'.
     1/4: $0\memdat_2[9:0]
     2/4: $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705
     3/4: $0$memwr$\storage_1$top.v:4739$781_DATA[9:0]$1704
     4/4: $0$memwr$\storage_1$top.v:4739$781_ADDR[3:0]$1703
Creating decoders for process `\top.$proc$top.v:4726$1700'.
     1/1: $0\memdat_1[9:0]
Creating decoders for process `\top.$proc$top.v:4720$1695'.
     1/4: $0\memdat[9:0]
     2/4: $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698
     3/4: $0$memwr$\storage$top.v:4722$780_DATA[9:0]$1697
     4/4: $0$memwr$\storage$top.v:4722$780_ADDR[3:0]$1696
Creating decoders for process `\top.$proc$top.v:4703$1681'.
     1/13: $0\memadr[9:0]
     2/13: $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684
     3/13: $0$memwr$\mem$top.v:4705$776_DATA[31:0]$1683
     4/13: $0$memwr$\mem$top.v:4705$776_ADDR[9:0]$1682
     5/13: $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687
     6/13: $0$memwr$\mem$top.v:4707$777_DATA[31:0]$1686
     7/13: $0$memwr$\mem$top.v:4707$777_ADDR[9:0]$1685
     8/13: $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690
     9/13: $0$memwr$\mem$top.v:4709$778_DATA[31:0]$1689
    10/13: $0$memwr$\mem$top.v:4709$778_ADDR[9:0]$1688
    11/13: $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693
    12/13: $0$memwr$\mem$top.v:4711$779_DATA[31:0]$1692
    13/13: $0$memwr$\mem$top.v:4711$779_ADDR[9:0]$1691
Creating decoders for process `\top.$proc$top.v:4267$1575'.
     1/115: $0\usb_tx_crc[15:0] [15]
     2/115: $0\usb_tx_crc[15:0] [13]
     3/115: $0\usb_tx_crc[15:0] [12]
     4/115: $0\usb_tx_crc[15:0] [11]
     5/115: $0\usb_tx_crc[15:0] [10]
     6/115: $0\usb_tx_crc[15:0] [9]
     7/115: $0\usb_tx_crc[15:0] [8]
     8/115: $0\usb_tx_crc[15:0] [7]
     9/115: $0\usb_tx_crc[15:0] [6]
    10/115: $0\usb_tx_crc[15:0] [5]
    11/115: $0\usb_tx_crc[15:0] [4]
    12/115: $0\usb_tx_crc[15:0] [3]
    13/115: $0\usb_tx_crc[15:0] [2]
    14/115: $0\usb_tx_crc[15:0] [1]
    15/115: $0\usb_tx_crc[15:0] [0]
    16/115: $0\usb_tx_crc[15:0] [14]
    17/115: $0\multiregimpl11_regs0[9:0]
    18/115: $0\multiregimpl10_regs1[9:0]
    19/115: $0\multiregimpl10_regs0[9:0]
    20/115: $0\multiregimpl7_regs1[9:0]
    21/115: $0\multiregimpl7_regs0[9:0]
    22/115: $0\multiregimpl5_regs1[9:0]
    23/115: $0\multiregimpl5_regs0[9:0]
    24/115: $0\multiregimpl4_regs1[9:0]
    25/115: $0\multiregimpl4_regs0[9:0]
    26/115: $0\multiregimpl2_regs2[0:0]
    27/115: $0\multiregimpl2_regs1[0:0]
    28/115: $0\multiregimpl2_regs0[0:0]
    29/115: $0\multiregimpl1_regs2[0:0]
    30/115: $0\multiregimpl1_regs1[0:0]
    31/115: $0\multiregimpl1_regs0[0:0]
    32/115: $0\usb_endpointin2_graycounter5_q[9:0]
    33/115: $0\usb_endpointin2_graycounter5_q_binary[9:0]
    34/115: $0\usb_endpointout1_outbuf_graycounter2_q[9:0]
    35/115: $0\usb_endpointout1_outbuf_graycounter2_q_binary[9:0]
    36/115: $0\usb_endpointin1_graycounter3_q[9:0]
    37/115: $0\usb_endpointin1_graycounter3_q_binary[9:0]
    38/115: $0\usb_endpointin0_graycounter1_q[9:0]
    39/115: $0\usb_endpointin0_graycounter1_q_binary[9:0]
    40/115: $0\usb_endpointout0_outbuf_graycounter0_q[9:0]
    41/115: $0\usb_endpointout0_outbuf_graycounter0_q_binary[9:0]
    42/115: $0\state[2:0]
    43/115: $0\usb_signal_is_el1[0:0]
    44/115: $0\usb_signal_is_el0[0:0]
    45/115: $0\usbfstx_txnrziencoder_state[2:0]
    46/115: $0\usb_tx_nrzi_o_usbn[0:0]
    47/115: $0\usb_tx_nrzi_o_usbp[0:0]
    48/115: $0\usb_tx_nrzi_o_oe[0:0]
    49/115: $0\usbfstx_txbitstuffer_state[2:0]
    50/115: $0\usbfstx_fsm_state[2:0]
    51/115: $0\usb_tx_o_oe[0:0]
    52/115: $0\usb_tx_o_usbn[0:0]
    53/115: $0\usb_tx_o_usbp[0:0]
    54/115: $0\usb_tx_o_pkt_end[0:0]
    55/115: $0\usb_tx_o_data_get[0:0]
    56/115: $0\usb_tx_mux_stuff_data[0:0]
    57/115: $0\usb_tx_mux_stuff_se0[0:0]
    58/115: $0\usb_tx_mux_stuff_oe[0:0]
    59/115: $0\usb_tx_mux_stuff_bit_strobe[0:0]
    60/115: $0\usbfsrx_fsm_state[2:0]
    61/115: $0\usb_rx_o_put[0:0]
    62/115: $0\usbfsrx_rxpacketdetect_state[2:0]
    63/115: $0\usb_rx_o_pkt_end[0:0]
    64/115: $0\usb_rx_o_pkt_active[0:0]
    65/115: $0\usb_rx_o_pkt_start[0:0]
    66/115: $0\usb_rx_pkt_end1[0:0]
    67/115: $0\usb_rx_pkt_active1[0:0]
    68/115: $0\usb_rx_bitstuff_error[0:0]
    69/115: $0\usb_rx_se0[0:0]
    70/115: $0\usb_rx_data[0:0]
    71/115: $0\usb_rx_valid[0:0]
    72/115: $0\usbfsrx_rxbitstuffremover_state[2:0]
    73/115: $0\usb_rx_bitstuff_o_bitstuff_error[0:0]
    74/115: $0\usb_rx_bitstuff_o_data[0:0]
    75/115: $0\usb_rx_bitstuff_o_valid[0:0]
    76/115: $0\usb_rx_bitstuff_o_se0[0:0]
    77/115: $0\usbfsrx_rxnrzidecoder_state[0:0]
    78/115: $0\usb_rx_nrzi_o_data1[0:0]
    79/115: $0\usb_rx_nrzi_o_valid1[0:0]
    80/115: $0\usb_rx_nrzi_o_se0[0:0]
    81/115: $0\usbfsrx_rxclockdatarecovery_state[2:0]
    82/115: $0\usb_rx_line_state_se11[0:0]
    83/115: $0\usb_rx_line_state_se01[0:0]
    84/115: $0\usb_rx_line_state_dk1[0:0]
    85/115: $0\usb_rx_line_state_dj1[0:0]
    86/115: $0\usb_rx_line_state_valid[0:0]
    87/115: $0\usb_endpointin2_dout[7:0]
    88/115: $0\usb_endpointin2_readable[0:0]
    89/115: $0\usb_endpointin1_dout[7:0]
    90/115: $0\usb_endpointin1_readable[0:0]
    91/115: $0\usb_endpointin0_dout[7:0]
    92/115: $0\usb_endpointin0_readable[0:0]
    93/115: $0\usb_response_pid[3:0]
    94/115: $0\usb_ep_addr[4:0]
    95/115: $0\usb_transfer_tok[1:0]
    96/115: $0\usb_tx_bitstuffer_o_oe[0:0]
    97/115: $0\usb_tx_bitstuffer_o_se0[0:0]
    98/115: $0\usb_tx_bitstuffer_o_data[0:0]
    99/115: $0\usb_tx_pid_is_data[0:0]
   100/115: $0\usb_tx_crc16_shifter_not_empty[0:0]
   101/115: $0\usb_tx_crc16_shifter_shifter[16:0]
   102/115: $0\multiregimpl11_regs1[9:0]
   103/115: $0\usb_tx_data_shifter_not_empty[0:0]
   104/115: $0\usb_tx_data_shifter_shifter[8:0]
   105/115: $0\usb_tx_pid_shifter_not_empty[0:0]
   106/115: $0\usb_tx_pid_shifter_shifter[8:0]
   107/115: $0\usb_tx_sync_shifter_not_empty[0:0]
   108/115: $0\usb_tx_sync_shifter_shifter[8:0]
   109/115: $0\usb_rx_o_ep[3:0]
   110/115: $0\usb_rx_o_addr[6:0]
   111/115: $0\usb_rx_o_pid[3:0]
   112/115: $0\usb_rx_data_n1[7:0]
   113/115: $0\usb_rx_data_n0[7:0]
   114/115: $0\usb_rx_shift_reg[8:0]
   115/115: $0\usb_rx_line_state_phase[1:0]
Creating decoders for process `\top.$proc$top.v:3156$1470'.
     1/177: $0\usbsoc_spiflash_sr[31:0] [31:24]
     2/177: $0\usbsoc_usbsoc_ctrl_storage_full[31:0] [31:24]
     3/177: $0\usbsoc_usbsoc_uart_phy_storage_full[31:0] [15:8]
     4/177: $0\usbsoc_usbsoc_uart_phy_storage_full[31:0] [23:16]
     5/177: $0\usbsoc_usbsoc_timer0_load_storage_full[31:0] [31:24]
     6/177: $0\usbsoc_usbsoc_timer0_reload_storage_full[31:0] [15:8]
     7/177: $0\usbsoc_usbsoc_timer0_reload_storage_full[31:0] [23:16]
     8/177: $0\usbsoc_usbsoc_uart_phy_storage_full[31:0] [31:24]
     9/177: $0\usbsoc_usbsoc_timer0_load_storage_full[31:0] [15:8]
    10/177: $0\usbsoc_usbsoc_timer0_load_storage_full[31:0] [23:16]
    11/177: $0\usbsoc_usbsoc_uart_phy_storage_full[31:0] [7:0]
    12/177: $0\usbsoc_usbsoc_ctrl_storage_full[31:0] [15:8]
    13/177: $0\usbsoc_usbsoc_ctrl_storage_full[31:0] [23:16]
    14/177: $0\usbsoc_spiflash_sr[31:0] [23:8]
    15/177: $0\usbsoc_usbsoc_timer0_reload_storage_full[31:0] [31:24]
    16/177: $0\usbsoc_spiflash_sr[31:0] [7:0]
    17/177: $0\multiregimpl13_regs0[0:0]
    18/177: $0\multiregimpl12_regs1[9:0]
    19/177: $0\multiregimpl12_regs0[9:0]
    20/177: $0\multiregimpl9_regs1[9:0]
    21/177: $0\multiregimpl9_regs0[9:0]
    22/177: $0\multiregimpl8_regs1[9:0]
    23/177: $0\multiregimpl8_regs0[9:0]
    24/177: $0\multiregimpl6_regs1[9:0]
    25/177: $0\multiregimpl6_regs0[9:0]
    26/177: $0\multiregimpl3_regs1[9:0]
    27/177: $0\multiregimpl3_regs0[9:0]
    28/177: $0\multiregimpl0_regs1[0:0]
    29/177: $0\multiregimpl0_regs0[0:0]
    30/177: $0\interface6_bank_bus_dat_r[7:0]
    31/177: $0\usbsoc_usbsoc_uart_phy_re[0:0]
    32/177: $0\interface5_bank_bus_dat_r[7:0]
    33/177: $0\interface4_bank_bus_dat_r[7:0]
    34/177: $0\usbsoc_usbsoc_timer0_en_re[0:0]
    35/177: $0\usbsoc_usbsoc_timer0_reload_re[0:0]
    36/177: $0\usbsoc_usbsoc_timer0_load_re[0:0]
    37/177: $0\interface3_bank_bus_dat_r[7:0]
    38/177: $0\usbsoc_spiflash_bitbang_en_re[0:0]
    39/177: $0\usbsoc_spiflash_bitbang_re[0:0]
    40/177: $0\interface2_bank_bus_dat_r[7:0]
    41/177: $0\interface1_bank_bus_dat_r[7:0]
    42/177: $0\sel_r[0:0]
    43/177: $0\usbsoc_usbsoc_ctrl_re[0:0]
    44/177: $0\interface0_bank_bus_dat_r[7:0]
    45/177: $0\slave_sel_r[2:0]
    46/177: $0\usb_endpointin2_graycounter4_q[9:0]
    47/177: $0\usb_endpointin2_graycounter4_q_binary[9:0]
    48/177: $0\usb_endpointin2_dtb_re[0:0]
    49/177: $0\usb_endpointin2_respond_re[0:0]
    50/177: $0\usb_endpointin2_eventmanager2_re[0:0]
    51/177: $0\usb_endpointout1_outbuf_graycounter3_q[9:0]
    52/177: $0\usb_endpointout1_outbuf_graycounter3_q_binary[9:0]
    53/177: $0\usb_endpointout1_dtb_re[0:0]
    54/177: $0\usb_endpointout1_respond_re[0:0]
    55/177: $0\usb_endpointout1_eventmanager1_re[0:0]
    56/177: $0\usb_endpointin1_graycounter2_q[9:0]
    57/177: $0\usb_endpointin1_graycounter2_q_binary[9:0]
    58/177: $0\usb_endpointin1_dtb_re[0:0]
    59/177: $0\usb_endpointin1_respond_re[0:0]
    60/177: $0\usb_endpointin1_eventmanager1_re[0:0]
    61/177: $0\usb_endpointin0_graycounter0_q[9:0]
    62/177: $0\usb_endpointin0_graycounter0_q_binary[9:0]
    63/177: $0\usb_endpointin0_dtb_re[0:0]
    64/177: $0\usb_endpointin0_respond_re[0:0]
    65/177: $0\usb_endpointin0_eventmanager0_re[0:0]
    66/177: $0\usb_endpointout0_outbuf_graycounter1_q[9:0]
    67/177: $0\usb_endpointout0_outbuf_graycounter1_q_binary[9:0]
    68/177: $0\usb_endpointout0_dtb_re[0:0]
    69/177: $0\usb_endpointout0_respond_re[0:0]
    70/177: $0\usb_endpointout0_eventmanager0_re[0:0]
    71/177: $0\usb_pullup_re[0:0]
    72/177: $0\array_muxed[1:0]
    73/177: $0\usbsoc_usbsoc_timer0_eventmanager_re[0:0]
    74/177: $0\usbsoc_usbsoc_timer0_zero_old_trigger[0:0]
    75/177: $0\usbsoc_usbsoc_uart_eventmanager_re[0:0]
    76/177: $0\usbsoc_usbsoc_uart_rx_old_trigger[0:0]
    77/177: $0\usbsoc_usbsoc_uart_tx_old_trigger[0:0]
    78/177: $0\usbsoc_usbsoc_uart_phy_rx_r[0:0]
    79/177: $0\usbsoc_usbsoc_uart_phy_source_valid[0:0]
    80/177: $0\usbsoc_usbsoc_uart_phy_sink_ready[0:0]
    81/177: $0\usbsoc_usbsoc_bus_wishbone_dat_r[31:0]
    82/177: $0\usbsoc_usbsoc_interface_adr[13:0]
    83/177: $0\usbsoc_usbsoc_interface_dat_w[7:0]
    84/177: $0\usbsoc_usbsoc_interface_we[0:0]
    85/177: $0\usbsoc_usbsoc_sram_bus_ack[0:0]
    86/177: $0\count[16:0]
    87/177: $0\grant[0:0]
    88/177: $0\usb_endpointin2_toggle[0:0]
    89/177: $0\usb_endpointin2_dtb_we[0:0]
    90/177: $0\usb_endpointin2_dtb_storage_full[0:0]
    91/177: $0\usb_endpointin2_respond_storage_full[1:0]
    92/177: $0\usb_endpointin2_last_tok_status[1:0]
    93/177: $0\usb_endpointin2_eventmanager2_storage_full[1:0]
    94/177: $0\usb_endpointin2_packet_pending[0:0]
    95/177: $0\usb_endpointin2_error_pending[0:0]
    96/177: $0\usb_endpointout1_outbuf_dout[7:0]
    97/177: $0\usb_endpointout1_outbuf_readable[0:0]
    98/177: $0\usb_endpointout1_toggle[0:0]
    99/177: $0\usb_endpointout1_dtb_we[0:0]
   100/177: $0\usb_endpointout1_dtb_storage_full[0:0]
   101/177: $0\usb_endpointout1_respond_storage_full[1:0]
   102/177: $0\usb_endpointout1_last_tok_status[1:0]
   103/177: $0\usb_endpointout1_eventmanager1_storage_full[1:0]
   104/177: $0\usb_endpointout1_packet_pending[0:0]
   105/177: $0\usb_endpointout1_error_pending[0:0]
   106/177: $0\usb_endpointin1_toggle[0:0]
   107/177: $0\usb_endpointin1_dtb_we[0:0]
   108/177: $0\usb_endpointin1_dtb_storage_full[0:0]
   109/177: $0\usb_endpointin1_respond_storage_full[1:0]
   110/177: $0\usb_endpointin1_last_tok_status[1:0]
   111/177: $0\usb_endpointin1_eventmanager1_storage_full[1:0]
   112/177: $0\usb_endpointin1_packet_pending[0:0]
   113/177: $0\usb_endpointin1_error_pending[0:0]
   114/177: $0\usb_oep_status[1:0]
   115/177: $0\usb_endpointin0_toggle[0:0]
   116/177: $0\usb_endpointin0_dtb_we[0:0]
   117/177: $0\usb_endpointin0_dtb_storage_full[0:0]
   118/177: $0\usb_endpointin0_respond_storage_full[1:0]
   119/177: $0\usb_endpointin0_last_tok_status[1:0]
   120/177: $0\usb_endpointin0_eventmanager0_storage_full[1:0]
   121/177: $0\usb_endpointin0_packet_pending[0:0]
   122/177: $0\usb_endpointin0_error_pending[0:0]
   123/177: $0\usb_endpointout0_outbuf_dout[7:0]
   124/177: $0\usb_endpointout0_outbuf_readable[0:0]
   125/177: $0\usb_endpointout0_toggle[0:0]
   126/177: $0\usb_endpointout0_dtb_we[0:0]
   127/177: $0\usb_endpointout0_dtb_storage_full[0:0]
   128/177: $0\usb_endpointout0_respond_storage_full[1:0]
   129/177: $0\usb_endpointout0_last_tok_status[1:0]
   130/177: $0\usb_endpointout0_eventmanager0_storage_full[1:0]
   131/177: $0\usb_endpointout0_packet_pending[0:0]
   132/177: $0\usb_endpointout0_error_pending[0:0]
   133/177: $0\usb_pullup_storage_full[0:0]
   134/177: $0\usbsoc_spiflash_counter[7:0]
   135/177: $0\usbsoc_spiflash_miso1[0:0]
   136/177: $0\usbsoc_spiflash_i[0:0]
   137/177: $0\usbsoc_usbsoc_uart_phy_uart_clk_rxen[0:0]
   138/177: $0\usbsoc_spiflash_clk1[0:0]
   139/177: $0\usbsoc_spiflash_cs_n1[0:0]
   140/177: $0\usbsoc_spiflash_bitbang_en_storage_full[0:0]
   141/177: $0\usbsoc_spiflash_bitbang_storage_full[3:0]
   142/177: $0\usbsoc_spiflash_bus_ack[0:0]
   143/177: $0\usbsoc_usbsoc_timer0_value[31:0]
   144/177: $0\usbsoc_usbsoc_timer0_eventmanager_storage_full[0:0]
   145/177: $0\usbsoc_usbsoc_timer0_zero_pending[0:0]
   146/177: $0\usbsoc_usbsoc_timer0_value_status[31:0]
   147/177: $0\usbsoc_usbsoc_timer0_en_storage_full[0:0]
   148/177: $0\usbsoc_usbsoc_timer0_load_storage_full[31:0] [7:0]
   149/177: $0\usbsoc_usbsoc_ctrl_storage_full[31:0] [7:0]
   150/177: $0\usbsoc_usbsoc_uart_rx_fifo_consume[3:0]
   151/177: $0\usbsoc_usbsoc_uart_rx_fifo_produce[3:0]
   152/177: $0\usbsoc_usbsoc_uart_rx_fifo_level0[4:0]
   153/177: $0\usbsoc_usbsoc_uart_rx_fifo_readable[0:0]
   154/177: $0\usbsoc_usbsoc_uart_tx_fifo_consume[3:0]
   155/177: $0\usbsoc_usbsoc_uart_tx_fifo_produce[3:0]
   156/177: $0\usbsoc_usbsoc_uart_tx_fifo_level0[4:0]
   157/177: $0\usbsoc_usbsoc_uart_tx_fifo_readable[0:0]
   158/177: $0\usbsoc_usbsoc_uart_eventmanager_storage_full[1:0]
   159/177: $0\usbsoc_usbsoc_uart_rx_pending[0:0]
   160/177: $0\usbsoc_usbsoc_uart_tx_pending[0:0]
   161/177: $0\usbsoc_usbsoc_uart_phy_rx_busy[0:0]
   162/177: $0\usbsoc_usbsoc_uart_phy_rx_bitcount[3:0]
   163/177: $0\usbsoc_usbsoc_uart_phy_rx_reg[7:0]
   164/177: $0\usbsoc_usbsoc_uart_phy_uart_clk_txen[0:0]
   165/177: $0\usbsoc_usbsoc_uart_phy_phase_accumulator_rx[31:0]
   166/177: $0\usbsoc_usbsoc_uart_phy_source_payload_data[7:0]
   167/177: $0\usbsoc_usbsoc_uart_phy_tx_busy[0:0]
   168/177: $0\usbsoc_usbsoc_uart_phy_tx_bitcount[3:0]
   169/177: $0\usbsoc_usbsoc_uart_phy_tx_reg[7:0]
   170/177: $0\multiregimpl13_regs1[0:0]
   171/177: $0\usbsoc_usbsoc_uart_phy_phase_accumulator_tx[31:0]
   172/177: $0\usbsoc_usbsoc_timer0_reload_storage_full[31:0] [7:0]
   173/177: $0\usbsoc_usbsoc_counter[1:0]
   174/177: $0\usbsoc_usbsoc_bus_wishbone_ack[0:0]
   175/177: $0\usbsoc_usbsoc_ctrl_bus_errors[31:0]
   176/177: $1\array_muxed[1:0]
   177/177: $0\serial_tx[0:0]
Creating decoders for process `\top.$proc$top.v:3147$1467'.
     1/1: $0\usbsoc_reset_delay[11:0]
Creating decoders for process `\top.$proc$top.v:3121$1466'.
     1/1: $0\rhs_array_muxed12[1:0]
Creating decoders for process `\top.$proc$top.v:3110$1465'.
     1/1: $0\rhs_array_muxed11[2:0]
Creating decoders for process `\top.$proc$top.v:3099$1464'.
     1/1: $0\rhs_array_muxed10[0:0]
Creating decoders for process `\top.$proc$top.v:3088$1463'.
     1/1: $0\rhs_array_muxed9[0:0]
Creating decoders for process `\top.$proc$top.v:3077$1462'.
     1/1: $0\rhs_array_muxed8[0:0]
Creating decoders for process `\top.$proc$top.v:3066$1461'.
     1/1: $0\rhs_array_muxed7[3:0]
Creating decoders for process `\top.$proc$top.v:3055$1460'.
     1/1: $0\rhs_array_muxed6[31:0]
Creating decoders for process `\top.$proc$top.v:3044$1459'.
     1/1: $0\rhs_array_muxed5[29:0]
Creating decoders for process `\top.$proc$top.v:3021$1458'.
     1/1: $0\rhs_array_muxed4[7:0]
Creating decoders for process `\top.$proc$top.v:2998$1457'.
     1/1: $0\rhs_array_muxed3[0:0]
Creating decoders for process `\top.$proc$top.v:2975$1456'.
     1/1: $0\rhs_array_muxed2[0:0]
Creating decoders for process `\top.$proc$top.v:2952$1455'.
     1/1: $0\rhs_array_muxed1[0:0]
Creating decoders for process `\top.$proc$top.v:2929$1454'.
     1/1: $0\rhs_array_muxed0[1:0]
Creating decoders for process `\top.$proc$top.v:2601$1118'.
     1/1: $0\sram_bus_dat_r[7:0]
Creating decoders for process `\top.$proc$top.v:2559$1080'.
     1/3: $0\shared_dat_r[31:0]
     2/3: $0\shared_ack[0:0]
     3/3: $0\error[0:0]
Creating decoders for process `\top.$proc$top.v:2527$1068'.
     1/3: $0\slave_sel[2:0] [2]
     2/3: $0\slave_sel[2:0] [1]
     3/3: $0\slave_sel[2:0] [0]
Creating decoders for process `\top.$proc$top.v:2502$1053'.
     1/1: $0\usb_endpointin2_graycounter5_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2493$1050'.
     1/1: $0\usb_endpointin2_graycounter4_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2469$1036'.
     1/2: $0\usb_endpointin2_eventmanager2_pending_w[1:0] [1]
     2/2: $0\usb_endpointin2_eventmanager2_pending_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2463$1034'.
     1/1: $0\usb_endpointin2_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2458$1033'.
     1/2: $0\usb_endpointin2_eventmanager2_status_w[1:0] [1]
     2/2: $0\usb_endpointin2_eventmanager2_status_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2452$1031'.
     1/1: $0\usb_endpointin2_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2436$1024'.
     1/1: $0\usb_endpointout1_outbuf_graycounter3_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2427$1021'.
     1/1: $0\usb_endpointout1_outbuf_graycounter2_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2403$1007'.
     1/2: $0\usb_endpointout1_eventmanager1_pending_w[1:0] [1]
     2/2: $0\usb_endpointout1_eventmanager1_pending_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2397$1005'.
     1/1: $0\usb_endpointout1_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2392$1004'.
     1/2: $0\usb_endpointout1_eventmanager1_status_w[1:0] [1]
     2/2: $0\usb_endpointout1_eventmanager1_status_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2386$1002'.
     1/1: $0\usb_endpointout1_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2370$995'.
     1/1: $0\usb_endpointin1_graycounter3_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2361$992'.
     1/1: $0\usb_endpointin1_graycounter2_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2337$978'.
     1/2: $0\usb_endpointin1_eventmanager1_pending_w[1:0] [1]
     2/2: $0\usb_endpointin1_eventmanager1_pending_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2331$976'.
     1/1: $0\usb_endpointin1_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2326$975'.
     1/2: $0\usb_endpointin1_eventmanager1_status_w[1:0] [1]
     2/2: $0\usb_endpointin1_eventmanager1_status_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2320$973'.
     1/1: $0\usb_endpointin1_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2304$966'.
     1/1: $0\usb_endpointin0_graycounter1_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2295$963'.
     1/1: $0\usb_endpointin0_graycounter0_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2271$949'.
     1/2: $0\usb_endpointin0_eventmanager0_pending_w[1:0] [1]
     2/2: $0\usb_endpointin0_eventmanager0_pending_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2265$947'.
     1/1: $0\usb_endpointin0_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2260$946'.
     1/2: $0\usb_endpointin0_eventmanager0_status_w[1:0] [1]
     2/2: $0\usb_endpointin0_eventmanager0_status_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2254$944'.
     1/1: $0\usb_endpointin0_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2238$937'.
     1/1: $0\usb_endpointout0_outbuf_graycounter1_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2229$934'.
     1/1: $0\usb_endpointout0_outbuf_graycounter0_q_next_binary[9:0]
Creating decoders for process `\top.$proc$top.v:2205$920'.
     1/2: $0\usb_endpointout0_eventmanager0_pending_w[1:0] [1]
     2/2: $0\usb_endpointout0_eventmanager0_pending_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2199$918'.
     1/1: $0\usb_endpointout0_packet_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2194$917'.
     1/2: $0\usb_endpointout0_eventmanager0_status_w[1:0] [1]
     2/2: $0\usb_endpointout0_eventmanager0_status_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:2188$915'.
     1/1: $0\usb_endpointout0_error_clear[0:0]
Creating decoders for process `\top.$proc$top.v:2073$902'.
     1/13: $0\next_state[2:0]
     2/13: $0\usb_data_send_get[0:0]
     3/13: $0\usb_data_recv_put[0:0]
     4/13: $0\usb_transfer_abort[0:0]
     5/13: $0\usb_transfer_commit0[0:0]
     6/13: $0\usb_response_pid_next_value_ce2[0:0]
     7/13: $0\usb_transfer_setup[0:0]
     8/13: $0\usb_response_pid_next_value2[3:0]
     9/13: $0\usb_transfer_start[0:0]
    10/13: $0\usb_transfer_tok_next_value_ce1[0:0]
    11/13: $0\usb_transfer_tok_next_value1[1:0]
    12/13: $0\usb_ep_addr_next_value_ce0[0:0]
    13/13: $0\usb_ep_addr_next_value0[4:0]
Creating decoders for process `\top.$proc$top.v:2000$893'.
     1/4: $0\usbfstx_txnrziencoder_next_state[2:0]
     2/4: $0\usb_tx_nrzi_oe[0:0]
     3/4: $0\usb_tx_nrzi_usbn[0:0]
     4/4: $0\usb_tx_nrzi_usbp[0:0]
Creating decoders for process `\top.$proc$top.v:1933$892'.
     1/2: $0\usbfstx_txbitstuffer_next_state[2:0]
     2/2: $0\usb_tx_bitstuffer_stuff_bit[0:0]
Creating decoders for process `\top.$proc$top.v:1911$874'.
     1/16: $0\usb_tx_o_crc[15:0] [15]
     2/16: $0\usb_tx_o_crc[15:0] [14]
     3/16: $0\usb_tx_o_crc[15:0] [13]
     4/16: $0\usb_tx_o_crc[15:0] [12]
     5/16: $0\usb_tx_o_crc[15:0] [11]
     6/16: $0\usb_tx_o_crc[15:0] [10]
     7/16: $0\usb_tx_o_crc[15:0] [9]
     8/16: $0\usb_tx_o_crc[15:0] [8]
     9/16: $0\usb_tx_o_crc[15:0] [7]
    10/16: $0\usb_tx_o_crc[15:0] [6]
    11/16: $0\usb_tx_o_crc[15:0] [5]
    12/16: $0\usb_tx_o_crc[15:0] [4]
    13/16: $0\usb_tx_o_crc[15:0] [3]
    14/16: $0\usb_tx_o_crc[15:0] [2]
    15/16: $0\usb_tx_o_crc[15:0] [1]
    16/16: $0\usb_tx_o_crc[15:0] [0]
Creating decoders for process `\top.$proc$top.v:1826$869'.
     1/10: $0\usbfstx_fsm_next_state[2:0]
     2/10: $0\usb_tx_shift_eop[0:0]
     3/10: $0\usb_tx_shift_pid[0:0]
     4/10: $0\usb_tx_shift_sync[0:0]
     5/10: $0\usb_tx_pkt_active[0:0]
     6/10: $0\usb_tx_pkt_end[0:0]
     7/10: $0\usb_tx_shift_crc16[0:0]
     8/10: $0\usb_tx_load_crc16[0:0]
     9/10: $0\usb_tx_shift_data[0:0]
    10/10: $0\usb_tx_load_data[0:0]
Creating decoders for process `\top.$proc$top.v:1755$865'.
     1/10: $0\usbfsrx_fsm_next_state[2:0]
     2/10: $0\usb_rx_i_reset[0:0]
     3/10: $0\usb_rx_start_tok[0:0]
     4/10: $0\usb_rx_end_data[0:0]
     5/10: $0\usb_rx_put_data[0:0]
     6/10: $0\usb_rx_start_data[0:0]
     7/10: $0\usb_rx_end_token[0:0]
     8/10: $0\usb_rx_start_token[0:0]
     9/10: $0\usb_rx_end_handshake[0:0]
    10/10: $0\usb_rx_end_pid[0:0]
Creating decoders for process `\top.$proc$top.v:1680$859'.
     1/4: $0\usbfsrx_rxpacketdetect_next_state[2:0]
     2/4: $0\usb_rx_pkt_end0[0:0]
     3/4: $0\usb_rx_pkt_active0[0:0]
     4/4: $0\usb_rx_pkt_start[0:0]
Creating decoders for process `\top.$proc$top.v:1613$858'.
     1/2: $0\usbfsrx_rxbitstuffremover_next_state[2:0]
     2/2: $0\usb_rx_bitstuff_drop_bit[0:0]
Creating decoders for process `\top.$proc$top.v:1579$857'.
     1/3: $0\usbfsrx_rxnrzidecoder_next_state[0:0]
     2/3: $0\usb_rx_nrzi_o_data0[0:0]
     3/3: $0\usb_rx_nrzi_o_valid0[0:0]
Creating decoders for process `\top.$proc$top.v:1527$852'.
     1/6: $0\usbfsrx_rxclockdatarecovery_next_state[2:0]
     2/6: $0\usb_rx_line_state_dj0[0:0]
     3/6: $0\usb_rx_line_state_dt[0:0]
     4/6: $0\usb_rx_line_state_se10[0:0]
     5/6: $0\usb_rx_line_state_se00[0:0]
     6/6: $0\usb_rx_line_state_dk0[0:0]
Creating decoders for process `\top.$proc$top.v:1515$851'.
     1/2: $0\usb_iobuf_usb_n_rx[0:0]
     2/2: $0\usb_iobuf_usb_p_rx[0:0]
Creating decoders for process `\top.$proc$top.v:1498$850'.
     1/2: $0\usb_tx_i_pkt_start[0:0]
     2/2: $0\usb_tx_i_pid[3:0]
Creating decoders for process `\top.$proc$top.v:1456$846'.
     1/6: $0\usb_oep_re[0:0]
     2/6: $0\usb_endpointin0_re[0:0]
     3/6: $0\usb_endpointout0_ibuf_re[0:0]
     4/6: $0\usb_endpointin2_re[0:0]
     5/6: $0\usb_endpointout1_ibuf_re[0:0]
     6/6: $0\usb_endpointin1_re[0:0]
Creating decoders for process `\top.$proc$top.v:1425$845'.
     1/6: $0\usb_endpointin2_din[7:0]
     2/6: $0\usb_oep_din[7:0]
     3/6: $0\usb_endpointout0_outbuf_asyncfifo0_din[7:0]
     4/6: $0\usb_endpointin1_din[7:0]
     5/6: $0\usb_endpointout1_outbuf_asyncfifo1_din[7:0]
     6/6: $0\usb_endpointin0_din[7:0]
Creating decoders for process `\top.$proc$top.v:1396$844'.
     1/6: $0\usb_oep_we[0:0]
     2/6: $0\usb_endpointin1_we[0:0]
     3/6: $0\usb_endpointout0_outbuf_asyncfifo0_we[0:0]
     4/6: $0\usb_endpointout1_outbuf_asyncfifo1_we[0:0]
     5/6: $0\usb_endpointin0_we[0:0]
     6/6: $0\usb_endpointin2_we[0:0]
Creating decoders for process `\top.$proc$top.v:1353$842'.
     1/8: $0\usb_data_toggle_bit[0:0]
     2/8: $0\usb_endpointout0_packet_trigger[0:0]
     3/8: $0\usb_endpointout1_packet_trigger[0:0]
     4/8: $0\usb_endpointin0_packet_trigger[0:0]
     5/8: $0\usb_endpointin2_packet_trigger[0:0]
     6/8: $0\usb_oep_trigger[0:0]
     7/8: $0\lhs_array_muxed0[0:0]
     8/8: $0\usb_endpointin1_packet_trigger[0:0]
Creating decoders for process `\top.$proc$top.v:1332$841'.
     1/4: $0\spiflash_mosi[0:0]
     2/4: $0\usbsoc_spiflash_miso_status[0:0]
     3/4: $0\spiflash_clk[0:0]
     4/4: $0\spiflash_cs_n[0:0]
Creating decoders for process `\top.$proc$top.v:1310$837'.
     1/1: $0\usbsoc_usbsoc_timer0_zero_clear[0:0]
Creating decoders for process `\top.$proc$top.v:1292$829'.
     1/1: $0\usbsoc_usbsoc_uart_rx_fifo_wrport_adr[3:0]
Creating decoders for process `\top.$proc$top.v:1262$818'.
     1/1: $0\usbsoc_usbsoc_uart_tx_fifo_wrport_adr[3:0]
Creating decoders for process `\top.$proc$top.v:1238$810'.
     1/2: $0\usbsoc_usbsoc_uart_eventmanager_pending_w[1:0] [1]
     2/2: $0\usbsoc_usbsoc_uart_eventmanager_pending_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:1232$808'.
     1/1: $0\usbsoc_usbsoc_uart_rx_clear[0:0]
Creating decoders for process `\top.$proc$top.v:1227$807'.
     1/2: $0\usbsoc_usbsoc_uart_eventmanager_status_w[1:0] [1]
     2/2: $0\usbsoc_usbsoc_uart_eventmanager_status_w[1:0] [0]
Creating decoders for process `\top.$proc$top.v:1221$805'.
     1/1: $0\usbsoc_usbsoc_uart_tx_clear[0:0]
Creating decoders for process `\top.$proc$top.v:1193$788'.
     1/4: $0\usbsoc_usbsoc_sram_we[3:0] [3]
     2/4: $0\usbsoc_usbsoc_sram_we[3:0] [2]
     3/4: $0\usbsoc_usbsoc_sram_we[3:0] [1]
     4/4: $0\usbsoc_usbsoc_sram_we[3:0] [0]
Creating decoders for process `\top.$proc$top.v:1184$787'.
     1/3: $0\usbsoc_usbsoc_lm32_interrupt[31:0] [2]
     2/3: $0\usbsoc_usbsoc_lm32_interrupt[31:0] [1]
     3/3: { $0\usbsoc_usbsoc_lm32_interrupt[31:0] [31:3] $0\usbsoc_usbsoc_lm32_interrupt[31:0] [0] }
Creating decoders for process `\lm32_logic_op.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_logic_op.v:90$743'.
     1/32: $0\logic_result_x[31:0] [31]
     2/32: $0\logic_result_x[31:0] [30]
     3/32: $0\logic_result_x[31:0] [29]
     4/32: $0\logic_result_x[31:0] [28]
     5/32: $0\logic_result_x[31:0] [27]
     6/32: $0\logic_result_x[31:0] [26]
     7/32: $0\logic_result_x[31:0] [25]
     8/32: $0\logic_result_x[31:0] [24]
     9/32: $0\logic_result_x[31:0] [23]
    10/32: $0\logic_result_x[31:0] [22]
    11/32: $0\logic_result_x[31:0] [21]
    12/32: $0\logic_result_x[31:0] [20]
    13/32: $0\logic_result_x[31:0] [19]
    14/32: $0\logic_result_x[31:0] [18]
    15/32: $0\logic_result_x[31:0] [17]
    16/32: $0\logic_result_x[31:0] [16]
    17/32: $0\logic_result_x[31:0] [15]
    18/32: $0\logic_result_x[31:0] [14]
    19/32: $0\logic_result_x[31:0] [13]
    20/32: $0\logic_result_x[31:0] [12]
    21/32: $0\logic_result_x[31:0] [11]
    22/32: $0\logic_result_x[31:0] [10]
    23/32: $0\logic_result_x[31:0] [9]
    24/32: $0\logic_result_x[31:0] [8]
    25/32: $0\logic_result_x[31:0] [7]
    26/32: $0\logic_result_x[31:0] [6]
    27/32: $0\logic_result_x[31:0] [5]
    28/32: $0\logic_result_x[31:0] [4]
    29/32: $0\logic_result_x[31:0] [3]
    30/32: $0\logic_result_x[31:0] [2]
    31/32: $0\logic_result_x[31:0] [1]
    32/32: $0\logic_result_x[31:0] [0]
Creating decoders for process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:486$2882'.
     1/1: $0\refill_offset[1:0]
Creating decoders for process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:400$2866'.
     1/4: $0\flush_set[6:0]
     2/4: $0\refill_address[29:0]
     3/4: $0\restart_request[0:0]
     4/4: $0\state[3:0]
Creating decoders for process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:391$2864'.
     1/1: $0\refilling[0:0]
Creating decoders for process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:934$2838'.
     1/2: $0\instruction_d[31:0]
     2/2: $0\bus_error_d[0:0]
Creating decoders for process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
     1/10: $0\i_adr_o[31:0] [31:4]
     2/10: $0\i_adr_o[31:0] [1:0]
     3/10: $0\i_adr_o[31:0] [3:2]
     4/10: $0\icache_refill_data[31:0]
     5/10: $0\icache_refill_ready[0:0]
     6/10: $0\i_lock_o[0:0]
     7/10: $0\i_cti_o[2:0]
     8/10: $0\i_stb_o[0:0]
     9/10: $0\i_cyc_o[0:0]
    10/10: $0\bus_error_f[0:0]
Creating decoders for process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:686$2822'.
     1/1: $0\restart_address[29:0]
Creating decoders for process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
     1/5: $0\pc_w[29:0]
     2/5: $0\pc_m[29:0]
     3/5: $0\pc_x[29:0]
     4/5: $0\pc_d[29:0]
     5/5: $0\pc_f[29:0]
Creating decoders for process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:539$2806'.
     1/5: $4\pc_a[29:0]
     2/5: $3\pc_a[29:0]
     3/5: $2\pc_a[29:0]
     4/5: $1\pc_a[29:0]
     5/5: $0\pc_a[29:0]
Creating decoders for process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:859$2330'.
     1/3: $0\data_w[31:0]
     2/3: $0\sign_extend_w[0:0]
     3/3: $0\size_w[1:0]
Creating decoders for process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
     1/5: $0\wb_select_m[0:0]
     2/5: $0\byte_enable_m[3:0]
     3/5: $0\store_data_m[31:0]
     4/5: $0\sign_extend_m[0:0]
     5/5: $0\size_m[1:0]
Creating decoders for process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
     1/11: $0\wb_load_complete[0:0]
     2/11: $0\wb_data_m[31:0]
     3/11: $0\d_lock_o[0:0]
     4/11: $0\d_cti_o[2:0]
     5/11: $0\d_we_o[0:0]
     6/11: $0\d_stb_o[0:0]
     7/11: $0\d_sel_o[3:0]
     8/11: $0\d_cyc_o[0:0]
     9/11: $0\d_adr_o[31:0]
    10/11: $0\d_dat_o[31:0]
    11/11: $0\stall_wb_load[0:0]
Creating decoders for process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:632$2296'.
     1/2: $1\load_data_w[31:0]
     2/2: $0\load_data_w[31:0]
Creating decoders for process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:518$2295'.
     1/2: $1\byte_enable_x[3:0]
     2/2: $0\byte_enable_x[3:0]
Creating decoders for process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:507$2294'.
     1/2: $1\store_data_x[31:0]
     2/2: $0\store_data_x[31:0]
Creating decoders for process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
     1/8: $0\cycles[5:0]
     2/8: $0\state[2:0]
     3/8: $0\b[31:0]
     4/8: $0\a[31:0]
     5/8: $0\p[31:0]
     6/8: $0\result_x[31:0]
     7/8: $0\divide_by_zero_x[0:0]
     8/8: $0\sign_extend_x[0:0]
Creating decoders for process `\lm32_adder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_adder.v:123$140'.
     1/2: $1\adder_overflow_x[0:0]
     2/2: $0\adder_overflow_x[0:0]
Creating decoders for process `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:232$132'.
     1/3: $0\im[31:0]
     2/3: $0\eie[0:0]
     3/3: $0\ie[0:0]
Creating decoders for process `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:181$131'.
     1/2: $1\csr_read_data[31:0]
     2/2: $0\csr_read_data[31:0]
Creating decoders for process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
     1/34: $6\x_result_sel_logic[0:0]
     2/34: $6\x_result_sel_add[0:0]
     3/34: $5\x_result_sel_sext[0:0]
     4/34: $5\x_result_sel_add[0:0]
     5/34: $5\x_result_sel_logic[0:0]
     6/34: $4\x_result_sel_mc_arith[0:0]
     7/34: $4\x_result_sel_add[0:0]
     8/34: $4\x_result_sel_logic[0:0]
     9/34: $4\x_result_sel_sext[0:0]
    10/34: $3\x_result_sel_mc_arith[0:0]
    11/34: $3\x_result_sel_add[0:0]
    12/34: $3\x_result_sel_logic[0:0]
    13/34: $3\x_result_sel_sext[0:0]
    14/34: $2\x_result_sel_mc_arith[0:0]
    15/34: $2\x_result_sel_add[0:0]
    16/34: $2\x_result_sel_logic[0:0]
    17/34: $2\x_result_sel_sext[0:0]
    18/34: $1\x_result_sel_csr[0:0]
    19/34: $1\x_result_sel_add[0:0]
    20/34: $1\x_result_sel_logic[0:0]
    21/34: $1\x_result_sel_sext[0:0]
    22/34: $1\x_result_sel_mc_arith[0:0]
    23/34: $2\d_result_sel_1[1:0]
    24/34: $1\d_result_sel_1[1:0]
    25/34: $1\d_result_sel_0[0:0]
    26/34: $0\w_result_sel_load[0:0]
    27/34: $0\m_result_sel_compare[0:0]
    28/34: $0\x_result_sel_add[0:0]
    29/34: $0\x_result_sel_logic[0:0]
    30/34: $0\x_result_sel_sext[0:0]
    31/34: $0\x_result_sel_mc_arith[0:0]
    32/34: $0\x_result_sel_csr[0:0]
    33/34: $0\d_result_sel_1[1:0]
    34/34: $0\d_result_sel_0[0:0]

21.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\valid_a' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2604$2716'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\csr_read_data_x' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2290$2697'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\eid_x' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1892$2563'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\w_result' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1661$2492'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\m_result' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1651$2490'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\x_result' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1631$2485'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\condition_met_x' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1615$2477'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\d_result_0' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1581$2472'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\d_result_1' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1581$2472'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\bypass_data_1' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1551$2463'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\bypass_data_0' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1538$2459'.
No latch inferred for signal `$paramod\lm32_cpu\eba_reset=537198592.\interlock' from process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1519$2439'.
No latch inferred for signal `\top.\usb_endpointin2_writable' from process `\top.$proc$top.v:779$2114'.
No latch inferred for signal `\top.\usb_endpointin2_ibuf_head_w' from process `\top.$proc$top.v:776$2112'.
No latch inferred for signal `\top.\usb_endpointin2_reset' from process `\top.$proc$top.v:740$2098'.
No latch inferred for signal `\top.\usb_endpointin2_error_trigger' from process `\top.$proc$top.v:715$2086'.
No latch inferred for signal `\top.\usb_endpointout1_ibuf_readable' from process `\top.$proc$top.v:710$2083'.
No latch inferred for signal `\top.\usb_endpointout1_ibuf_dout' from process `\top.$proc$top.v:709$2082'.
No latch inferred for signal `\top.\usb_endpointout1_reset' from process `\top.$proc$top.v:671$2067'.
No latch inferred for signal `\top.\usb_endpointout1_error_trigger' from process `\top.$proc$top.v:646$2055'.
No latch inferred for signal `\top.\usb_endpointin1_writable' from process `\top.$proc$top.v:641$2052'.
No latch inferred for signal `\top.\usb_endpointin1_ibuf_head_w' from process `\top.$proc$top.v:638$2050'.
No latch inferred for signal `\top.\usb_endpointin1_reset' from process `\top.$proc$top.v:602$2036'.
No latch inferred for signal `\top.\usb_endpointin1_error_trigger' from process `\top.$proc$top.v:577$2024'.
No latch inferred for signal `\top.\usb_oep_storage' from process `\top.$proc$top.v:573$2022'.
No latch inferred for signal `\top.\usb_oep_response' from process `\top.$proc$top.v:570$2019'.
No latch inferred for signal `\top.\usb_oep_writable' from process `\top.$proc$top.v:568$2017'.
No latch inferred for signal `\top.\usb_oep_readable' from process `\top.$proc$top.v:565$2014'.
No latch inferred for signal `\top.\usb_oep_dout' from process `\top.$proc$top.v:564$2013'.
No latch inferred for signal `\top.\usb_endpointin0_writable' from process `\top.$proc$top.v:562$2011'.
No latch inferred for signal `\top.\usb_endpointin0_ibuf_head_w' from process `\top.$proc$top.v:559$2009'.
No latch inferred for signal `\top.\usb_endpointin0_error_trigger' from process `\top.$proc$top.v:498$1984'.
No latch inferred for signal `\top.\usb_endpointout0_ibuf_readable' from process `\top.$proc$top.v:493$1981'.
No latch inferred for signal `\top.\usb_endpointout0_ibuf_dout' from process `\top.$proc$top.v:492$1980'.
No latch inferred for signal `\top.\usb_endpointout0_error_trigger' from process `\top.$proc$top.v:429$1954'.
No latch inferred for signal `\top.\usb_reset' from process `\top.$proc$top.v:401$1940'.
No latch inferred for signal `\top.\usbsoc_spiflash_bus_err' from process `\top.$proc$top.v:268$1834'.
No latch inferred for signal `\top.\usbsoc_reset' from process `\top.$proc$top.v:251$1831'.
No latch inferred for signal `\top.\usb_48_rst' from process `\top.$proc$top.v:250$1830'.
No latch inferred for signal `\top.\usbsoc_usbsoc_timer0_update_value_w' from process `\top.$proc$top.v:226$1822'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_reset' from process `\top.$proc$top.v:214$1815'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_rx_fifo_replace' from process `\top.$proc$top.v:196$1811'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_replace' from process `\top.$proc$top.v:159$1805'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_sink_last' from process `\top.$proc$top.v:143$1802'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_sink_first' from process `\top.$proc$top.v:142$1801'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_phy_source_last' from process `\top.$proc$top.v:103$1783'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_phy_source_first' from process `\top.$proc$top.v:102$1782'.
No latch inferred for signal `\top.\usbsoc_usbsoc_bus_wishbone_err' from process `\top.$proc$top.v:85$1771'.
No latch inferred for signal `\top.\usbsoc_usbsoc_sram_bus_err' from process `\top.$proc$top.v:66$1764'.
No latch inferred for signal `\top.\usbsoc_usbsoc_ctrl_reset_reset_w' from process `\top.$proc$top.v:22$1758'.
No latch inferred for signal `\top.\rhs_array_muxed12' from process `\top.$proc$top.v:3121$1466'.
No latch inferred for signal `\top.\rhs_array_muxed11' from process `\top.$proc$top.v:3110$1465'.
No latch inferred for signal `\top.\rhs_array_muxed10' from process `\top.$proc$top.v:3099$1464'.
No latch inferred for signal `\top.\rhs_array_muxed9' from process `\top.$proc$top.v:3088$1463'.
No latch inferred for signal `\top.\rhs_array_muxed8' from process `\top.$proc$top.v:3077$1462'.
No latch inferred for signal `\top.\rhs_array_muxed7' from process `\top.$proc$top.v:3066$1461'.
No latch inferred for signal `\top.\rhs_array_muxed6' from process `\top.$proc$top.v:3055$1460'.
No latch inferred for signal `\top.\rhs_array_muxed5' from process `\top.$proc$top.v:3044$1459'.
No latch inferred for signal `\top.\rhs_array_muxed4' from process `\top.$proc$top.v:3021$1458'.
No latch inferred for signal `\top.\rhs_array_muxed3' from process `\top.$proc$top.v:2998$1457'.
No latch inferred for signal `\top.\rhs_array_muxed2' from process `\top.$proc$top.v:2975$1456'.
No latch inferred for signal `\top.\rhs_array_muxed1' from process `\top.$proc$top.v:2952$1455'.
No latch inferred for signal `\top.\rhs_array_muxed0' from process `\top.$proc$top.v:2929$1454'.
No latch inferred for signal `\top.\sram_bus_dat_r' from process `\top.$proc$top.v:2601$1118'.
No latch inferred for signal `\top.\shared_dat_r' from process `\top.$proc$top.v:2559$1080'.
No latch inferred for signal `\top.\shared_ack' from process `\top.$proc$top.v:2559$1080'.
No latch inferred for signal `\top.\error' from process `\top.$proc$top.v:2559$1080'.
No latch inferred for signal `\top.\slave_sel' from process `\top.$proc$top.v:2527$1068'.
No latch inferred for signal `\top.\usb_endpointin2_graycounter5_q_next_binary' from process `\top.$proc$top.v:2502$1053'.
No latch inferred for signal `\top.\usb_endpointin2_graycounter4_q_next_binary' from process `\top.$proc$top.v:2493$1050'.
No latch inferred for signal `\top.\usb_endpointin2_eventmanager2_pending_w' from process `\top.$proc$top.v:2469$1036'.
No latch inferred for signal `\top.\usb_endpointin2_packet_clear' from process `\top.$proc$top.v:2463$1034'.
No latch inferred for signal `\top.\usb_endpointin2_eventmanager2_status_w' from process `\top.$proc$top.v:2458$1033'.
No latch inferred for signal `\top.\usb_endpointin2_error_clear' from process `\top.$proc$top.v:2452$1031'.
No latch inferred for signal `\top.\usb_endpointout1_outbuf_graycounter3_q_next_binary' from process `\top.$proc$top.v:2436$1024'.
No latch inferred for signal `\top.\usb_endpointout1_outbuf_graycounter2_q_next_binary' from process `\top.$proc$top.v:2427$1021'.
No latch inferred for signal `\top.\usb_endpointout1_eventmanager1_pending_w' from process `\top.$proc$top.v:2403$1007'.
No latch inferred for signal `\top.\usb_endpointout1_packet_clear' from process `\top.$proc$top.v:2397$1005'.
No latch inferred for signal `\top.\usb_endpointout1_eventmanager1_status_w' from process `\top.$proc$top.v:2392$1004'.
No latch inferred for signal `\top.\usb_endpointout1_error_clear' from process `\top.$proc$top.v:2386$1002'.
No latch inferred for signal `\top.\usb_endpointin1_graycounter3_q_next_binary' from process `\top.$proc$top.v:2370$995'.
No latch inferred for signal `\top.\usb_endpointin1_graycounter2_q_next_binary' from process `\top.$proc$top.v:2361$992'.
No latch inferred for signal `\top.\usb_endpointin1_eventmanager1_pending_w' from process `\top.$proc$top.v:2337$978'.
No latch inferred for signal `\top.\usb_endpointin1_packet_clear' from process `\top.$proc$top.v:2331$976'.
No latch inferred for signal `\top.\usb_endpointin1_eventmanager1_status_w' from process `\top.$proc$top.v:2326$975'.
No latch inferred for signal `\top.\usb_endpointin1_error_clear' from process `\top.$proc$top.v:2320$973'.
No latch inferred for signal `\top.\usb_endpointin0_graycounter1_q_next_binary' from process `\top.$proc$top.v:2304$966'.
No latch inferred for signal `\top.\usb_endpointin0_graycounter0_q_next_binary' from process `\top.$proc$top.v:2295$963'.
No latch inferred for signal `\top.\usb_endpointin0_eventmanager0_pending_w' from process `\top.$proc$top.v:2271$949'.
No latch inferred for signal `\top.\usb_endpointin0_packet_clear' from process `\top.$proc$top.v:2265$947'.
No latch inferred for signal `\top.\usb_endpointin0_eventmanager0_status_w' from process `\top.$proc$top.v:2260$946'.
No latch inferred for signal `\top.\usb_endpointin0_error_clear' from process `\top.$proc$top.v:2254$944'.
No latch inferred for signal `\top.\usb_endpointout0_outbuf_graycounter1_q_next_binary' from process `\top.$proc$top.v:2238$937'.
No latch inferred for signal `\top.\usb_endpointout0_outbuf_graycounter0_q_next_binary' from process `\top.$proc$top.v:2229$934'.
No latch inferred for signal `\top.\usb_endpointout0_eventmanager0_pending_w' from process `\top.$proc$top.v:2205$920'.
No latch inferred for signal `\top.\usb_endpointout0_packet_clear' from process `\top.$proc$top.v:2199$918'.
No latch inferred for signal `\top.\usb_endpointout0_eventmanager0_status_w' from process `\top.$proc$top.v:2194$917'.
No latch inferred for signal `\top.\usb_endpointout0_error_clear' from process `\top.$proc$top.v:2188$915'.
No latch inferred for signal `\top.\usb_transfer_start' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_transfer_setup' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_transfer_commit0' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_transfer_abort' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_data_recv_put' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_data_send_get' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\next_state' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_ep_addr_next_value0' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_ep_addr_next_value_ce0' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_transfer_tok_next_value1' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_transfer_tok_next_value_ce1' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_response_pid_next_value2' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_response_pid_next_value_ce2' from process `\top.$proc$top.v:2073$902'.
No latch inferred for signal `\top.\usb_tx_nrzi_usbp' from process `\top.$proc$top.v:2000$893'.
No latch inferred for signal `\top.\usb_tx_nrzi_usbn' from process `\top.$proc$top.v:2000$893'.
No latch inferred for signal `\top.\usb_tx_nrzi_oe' from process `\top.$proc$top.v:2000$893'.
No latch inferred for signal `\top.\usbfstx_txnrziencoder_next_state' from process `\top.$proc$top.v:2000$893'.
No latch inferred for signal `\top.\usb_tx_bitstuffer_stuff_bit' from process `\top.$proc$top.v:1933$892'.
No latch inferred for signal `\top.\usbfstx_txbitstuffer_next_state' from process `\top.$proc$top.v:1933$892'.
No latch inferred for signal `\top.\usb_tx_o_crc' from process `\top.$proc$top.v:1911$874'.
No latch inferred for signal `\top.\usb_tx_pkt_active' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_shift_sync' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_shift_pid' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_shift_eop' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_load_data' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_shift_data' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_load_crc16' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_shift_crc16' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_tx_pkt_end' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usbfstx_fsm_next_state' from process `\top.$proc$top.v:1826$869'.
No latch inferred for signal `\top.\usb_rx_i_reset' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_start_tok' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_end_pid' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_end_handshake' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_start_token' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_end_token' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_start_data' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_put_data' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_end_data' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usbfsrx_fsm_next_state' from process `\top.$proc$top.v:1755$865'.
No latch inferred for signal `\top.\usb_rx_pkt_start' from process `\top.$proc$top.v:1680$859'.
No latch inferred for signal `\top.\usb_rx_pkt_active0' from process `\top.$proc$top.v:1680$859'.
No latch inferred for signal `\top.\usb_rx_pkt_end0' from process `\top.$proc$top.v:1680$859'.
No latch inferred for signal `\top.\usbfsrx_rxpacketdetect_next_state' from process `\top.$proc$top.v:1680$859'.
No latch inferred for signal `\top.\usb_rx_bitstuff_drop_bit' from process `\top.$proc$top.v:1613$858'.
No latch inferred for signal `\top.\usbfsrx_rxbitstuffremover_next_state' from process `\top.$proc$top.v:1613$858'.
No latch inferred for signal `\top.\usb_rx_nrzi_o_valid0' from process `\top.$proc$top.v:1579$857'.
No latch inferred for signal `\top.\usb_rx_nrzi_o_data0' from process `\top.$proc$top.v:1579$857'.
No latch inferred for signal `\top.\usbfsrx_rxnrzidecoder_next_state' from process `\top.$proc$top.v:1579$857'.
No latch inferred for signal `\top.\usb_rx_line_state_dt' from process `\top.$proc$top.v:1527$852'.
No latch inferred for signal `\top.\usb_rx_line_state_dj0' from process `\top.$proc$top.v:1527$852'.
No latch inferred for signal `\top.\usb_rx_line_state_dk0' from process `\top.$proc$top.v:1527$852'.
No latch inferred for signal `\top.\usb_rx_line_state_se00' from process `\top.$proc$top.v:1527$852'.
No latch inferred for signal `\top.\usb_rx_line_state_se10' from process `\top.$proc$top.v:1527$852'.
No latch inferred for signal `\top.\usbfsrx_rxclockdatarecovery_next_state' from process `\top.$proc$top.v:1527$852'.
No latch inferred for signal `\top.\usb_iobuf_usb_p_rx' from process `\top.$proc$top.v:1515$851'.
No latch inferred for signal `\top.\usb_iobuf_usb_n_rx' from process `\top.$proc$top.v:1515$851'.
No latch inferred for signal `\top.\usb_tx_i_pkt_start' from process `\top.$proc$top.v:1498$850'.
No latch inferred for signal `\top.\usb_tx_i_pid' from process `\top.$proc$top.v:1498$850'.
No latch inferred for signal `\top.\usb_endpointout0_ibuf_re' from process `\top.$proc$top.v:1456$846'.
No latch inferred for signal `\top.\usb_endpointin0_re' from process `\top.$proc$top.v:1456$846'.
No latch inferred for signal `\top.\usb_oep_re' from process `\top.$proc$top.v:1456$846'.
No latch inferred for signal `\top.\usb_endpointin1_re' from process `\top.$proc$top.v:1456$846'.
No latch inferred for signal `\top.\usb_endpointout1_ibuf_re' from process `\top.$proc$top.v:1456$846'.
No latch inferred for signal `\top.\usb_endpointin2_re' from process `\top.$proc$top.v:1456$846'.
No latch inferred for signal `\top.\usb_endpointout0_outbuf_asyncfifo0_din' from process `\top.$proc$top.v:1425$845'.
No latch inferred for signal `\top.\usb_endpointin0_din' from process `\top.$proc$top.v:1425$845'.
No latch inferred for signal `\top.\usb_oep_din' from process `\top.$proc$top.v:1425$845'.
No latch inferred for signal `\top.\usb_endpointin1_din' from process `\top.$proc$top.v:1425$845'.
No latch inferred for signal `\top.\usb_endpointout1_outbuf_asyncfifo1_din' from process `\top.$proc$top.v:1425$845'.
No latch inferred for signal `\top.\usb_endpointin2_din' from process `\top.$proc$top.v:1425$845'.
No latch inferred for signal `\top.\usb_endpointout0_outbuf_asyncfifo0_we' from process `\top.$proc$top.v:1396$844'.
No latch inferred for signal `\top.\usb_endpointin0_we' from process `\top.$proc$top.v:1396$844'.
No latch inferred for signal `\top.\usb_oep_we' from process `\top.$proc$top.v:1396$844'.
No latch inferred for signal `\top.\usb_endpointin1_we' from process `\top.$proc$top.v:1396$844'.
No latch inferred for signal `\top.\usb_endpointout1_outbuf_asyncfifo1_we' from process `\top.$proc$top.v:1396$844'.
No latch inferred for signal `\top.\usb_endpointin2_we' from process `\top.$proc$top.v:1396$844'.
No latch inferred for signal `\top.\usb_data_toggle_bit' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\usb_endpointout0_packet_trigger' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\usb_endpointin0_packet_trigger' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\usb_oep_trigger' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\usb_endpointin1_packet_trigger' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\usb_endpointout1_packet_trigger' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\usb_endpointin2_packet_trigger' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\lhs_array_muxed0' from process `\top.$proc$top.v:1353$842'.
No latch inferred for signal `\top.\spiflash_cs_n' from process `\top.$proc$top.v:1332$841'.
No latch inferred for signal `\top.\spiflash_clk' from process `\top.$proc$top.v:1332$841'.
No latch inferred for signal `\top.\spiflash_mosi' from process `\top.$proc$top.v:1332$841'.
No latch inferred for signal `\top.\usbsoc_spiflash_miso_status' from process `\top.$proc$top.v:1332$841'.
No latch inferred for signal `\top.\usbsoc_usbsoc_timer0_zero_clear' from process `\top.$proc$top.v:1310$837'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_rx_fifo_wrport_adr' from process `\top.$proc$top.v:1292$829'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_wrport_adr' from process `\top.$proc$top.v:1262$818'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_eventmanager_pending_w' from process `\top.$proc$top.v:1238$810'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_rx_clear' from process `\top.$proc$top.v:1232$808'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_eventmanager_status_w' from process `\top.$proc$top.v:1227$807'.
No latch inferred for signal `\top.\usbsoc_usbsoc_uart_tx_clear' from process `\top.$proc$top.v:1221$805'.
No latch inferred for signal `\top.\usbsoc_usbsoc_sram_we' from process `\top.$proc$top.v:1193$788'.
No latch inferred for signal `\top.\usbsoc_usbsoc_lm32_interrupt' from process `\top.$proc$top.v:1184$787'.
No latch inferred for signal `\lm32_logic_op.\logic_result_x' from process `\lm32_logic_op.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_logic_op.v:90$743'.
No latch inferred for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\pc_a' from process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:539$2806'.
No latch inferred for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\load_data_w' from process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:632$2296'.
No latch inferred for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\byte_enable_x' from process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:518$2295'.
No latch inferred for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\store_data_x' from process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:507$2294'.
No latch inferred for signal `\lm32_adder.\adder_overflow_x' from process `\lm32_adder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_adder.v:123$140'.
No latch inferred for signal `\lm32_interrupt.\csr_read_data' from process `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:181$131'.
No latch inferred for signal `\lm32_decoder.\d_result_sel_0' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\d_result_sel_1' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\x_result_sel_csr' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\x_result_sel_mc_arith' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\x_result_sel_sext' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\x_result_sel_logic' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\x_result_sel_add' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\m_result_sel_compare' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
No latch inferred for signal `\lm32_decoder.\w_result_sel_load' from process `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.

21.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod\lm32_ram\data_width=32\address_width=9.\ra' using process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2908'.
  created $dff cell `$procdff$7361' with positive edge clock.
Creating register for signal `$paramod\lm32_ram\data_width=32\address_width=9.$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_ADDR' using process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2901'.
  created $dff cell `$procdff$7362' with positive edge clock.
Creating register for signal `$paramod\lm32_ram\data_width=32\address_width=9.$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_DATA' using process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2901'.
  created $dff cell `$procdff$7363' with positive edge clock.
Creating register for signal `$paramod\lm32_ram\data_width=32\address_width=9.$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN' using process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2901'.
  created $dff cell `$procdff$7364' with positive edge clock.
Creating register for signal `$paramod\lm32_ram\data_width=22\address_width=7.\ra' using process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2897'.
  created $dff cell `$procdff$7365' with positive edge clock.
Creating register for signal `$paramod\lm32_ram\data_width=22\address_width=7.$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_ADDR' using process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2890'.
  created $dff cell `$procdff$7366' with positive edge clock.
Creating register for signal `$paramod\lm32_ram\data_width=22\address_width=7.$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_DATA' using process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2890'.
  created $dff cell `$procdff$7367' with positive edge clock.
Creating register for signal `$paramod\lm32_ram\data_width=22\address_width=7.$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN' using process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2890'.
  created $dff cell `$procdff$7368' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_ADDR' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3033$2774'.
  created $dff cell `$procdff$7369' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_DATA' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3033$2774'.
  created $dff cell `$procdff$7370' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3033$2774'.
  created $dff cell `$procdff$7371' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\adder_op_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7372' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\adder_op_x_n' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7373' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\operand_0_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7374' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\operand_1_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7375' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\load_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7376' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\load_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7377' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\store_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7378' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\store_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7379' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\size_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7380' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7381' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_predict_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7382' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_predict_taken_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7383' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7384' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_predict_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7385' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_predict_taken_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7386' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_target_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7387' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\branch_target_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7388' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\x_result_sel_csr_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7389' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\x_result_sel_mc_arith_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7390' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\x_result_sel_sext_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7391' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\x_result_sel_logic_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7392' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\x_result_sel_add_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7393' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\m_result_sel_compare_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7394' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\m_result_sel_compare_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7395' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\w_result_sel_load_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7396' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\w_result_sel_load_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7397' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\w_result_sel_load_w' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7398' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\x_bypass_enable_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7399' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\m_bypass_enable_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7400' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\m_bypass_enable_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7401' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\sign_extend_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7402' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\write_enable_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7403' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\write_enable_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7404' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\write_enable_w' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7405' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\write_idx_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7406' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\write_idx_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7407' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\write_idx_w' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7408' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\csr_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7409' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\condition_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7410' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\scall_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7411' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\eret_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7412' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\eret_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7413' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\csr_write_enable_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7414' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\bus_error_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7415' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\data_bus_error_exception_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7416' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\memop_pc_w' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7417' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\store_operand_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7418' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\operand_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7419' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\operand_w' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7420' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\logic_op_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7421' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\condition_met_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7422' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\exception_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7423' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\exception_w' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
  created $dff cell `$procdff$7424' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\valid_f' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
  created $dff cell `$procdff$7425' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\valid_d' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
  created $dff cell `$procdff$7426' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\valid_x' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
  created $dff cell `$procdff$7427' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\valid_m' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
  created $dff cell `$procdff$7428' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\valid_w' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
  created $dff cell `$procdff$7429' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\data_bus_error_seen' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2555$2708'.
  created $dff cell `$procdff$7430' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\cc' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2544$2705'.
  created $dff cell `$procdff$7431' with positive edge clock.
Creating register for signal `$paramod\lm32_cpu\eba_reset=537198592.\eba' using process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2509$2698'.
  created $dff cell `$procdff$7432' with positive edge clock.
Creating register for signal `\top.\memadr_11' using process `\top.$proc$top.v:4876$1743'.
  created $dff cell `$procdff$7433' with positive edge clock.
Creating register for signal `\top.\memadr_10' using process `\top.$proc$top.v:4870$1739'.
  created $dff cell `$procdff$7434' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_6$top.v:4872$786_ADDR' using process `\top.$proc$top.v:4870$1739'.
  created $dff cell `$procdff$7435' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_6$top.v:4872$786_DATA' using process `\top.$proc$top.v:4870$1739'.
  created $dff cell `$procdff$7436' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_6$top.v:4872$786_EN' using process `\top.$proc$top.v:4870$1739'.
  created $dff cell `$procdff$7437' with positive edge clock.
Creating register for signal `\top.\memadr_9' using process `\top.$proc$top.v:4860$1736'.
  created $dff cell `$procdff$7438' with positive edge clock.
Creating register for signal `\top.\memadr_8' using process `\top.$proc$top.v:4854$1732'.
  created $dff cell `$procdff$7439' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_5$top.v:4856$785_ADDR' using process `\top.$proc$top.v:4854$1732'.
  created $dff cell `$procdff$7440' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_5$top.v:4856$785_DATA' using process `\top.$proc$top.v:4854$1732'.
  created $dff cell `$procdff$7441' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_5$top.v:4856$785_EN' using process `\top.$proc$top.v:4854$1732'.
  created $dff cell `$procdff$7442' with positive edge clock.
Creating register for signal `\top.\memadr_7' using process `\top.$proc$top.v:4844$1729'.
  created $dff cell `$procdff$7443' with positive edge clock.
Creating register for signal `\top.\memadr_6' using process `\top.$proc$top.v:4838$1725'.
  created $dff cell `$procdff$7444' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_4$top.v:4840$784_ADDR' using process `\top.$proc$top.v:4838$1725'.
  created $dff cell `$procdff$7445' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_4$top.v:4840$784_DATA' using process `\top.$proc$top.v:4838$1725'.
  created $dff cell `$procdff$7446' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_4$top.v:4840$784_EN' using process `\top.$proc$top.v:4838$1725'.
  created $dff cell `$procdff$7447' with positive edge clock.
Creating register for signal `\top.\memadr_5' using process `\top.$proc$top.v:4828$1722'.
  created $dff cell `$procdff$7448' with positive edge clock.
Creating register for signal `\top.\memadr_4' using process `\top.$proc$top.v:4822$1718'.
  created $dff cell `$procdff$7449' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_3$top.v:4824$783_ADDR' using process `\top.$proc$top.v:4822$1718'.
  created $dff cell `$procdff$7450' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_3$top.v:4824$783_DATA' using process `\top.$proc$top.v:4822$1718'.
  created $dff cell `$procdff$7451' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_3$top.v:4824$783_EN' using process `\top.$proc$top.v:4822$1718'.
  created $dff cell `$procdff$7452' with positive edge clock.
Creating register for signal `\top.\memadr_3' using process `\top.$proc$top.v:4812$1715'.
  created $dff cell `$procdff$7453' with positive edge clock.
Creating register for signal `\top.\memadr_2' using process `\top.$proc$top.v:4806$1711'.
  created $dff cell `$procdff$7454' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_2$top.v:4808$782_ADDR' using process `\top.$proc$top.v:4806$1711'.
  created $dff cell `$procdff$7455' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_2$top.v:4808$782_DATA' using process `\top.$proc$top.v:4806$1711'.
  created $dff cell `$procdff$7456' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_2$top.v:4808$782_EN' using process `\top.$proc$top.v:4806$1711'.
  created $dff cell `$procdff$7457' with positive edge clock.
Creating register for signal `\top.\memadr_1' using process `\top.$proc$top.v:4753$1709'.
  created $dff cell `$procdff$7458' with positive edge clock.
Creating register for signal `\top.\memdat_3' using process `\top.$proc$top.v:4743$1707'.
  created $dff cell `$procdff$7459' with positive edge clock.
Creating register for signal `\top.\memdat_2' using process `\top.$proc$top.v:4737$1702'.
  created $dff cell `$procdff$7460' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_1$top.v:4739$781_ADDR' using process `\top.$proc$top.v:4737$1702'.
  created $dff cell `$procdff$7461' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_1$top.v:4739$781_DATA' using process `\top.$proc$top.v:4737$1702'.
  created $dff cell `$procdff$7462' with positive edge clock.
Creating register for signal `\top.$memwr$\storage_1$top.v:4739$781_EN' using process `\top.$proc$top.v:4737$1702'.
  created $dff cell `$procdff$7463' with positive edge clock.
Creating register for signal `\top.\memdat_1' using process `\top.$proc$top.v:4726$1700'.
  created $dff cell `$procdff$7464' with positive edge clock.
Creating register for signal `\top.\memdat' using process `\top.$proc$top.v:4720$1695'.
  created $dff cell `$procdff$7465' with positive edge clock.
Creating register for signal `\top.$memwr$\storage$top.v:4722$780_ADDR' using process `\top.$proc$top.v:4720$1695'.
  created $dff cell `$procdff$7466' with positive edge clock.
Creating register for signal `\top.$memwr$\storage$top.v:4722$780_DATA' using process `\top.$proc$top.v:4720$1695'.
  created $dff cell `$procdff$7467' with positive edge clock.
Creating register for signal `\top.$memwr$\storage$top.v:4722$780_EN' using process `\top.$proc$top.v:4720$1695'.
  created $dff cell `$procdff$7468' with positive edge clock.
Creating register for signal `\top.\memadr' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7469' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4705$776_ADDR' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7470' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4705$776_DATA' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7471' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4705$776_EN' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7472' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4707$777_ADDR' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7473' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4707$777_DATA' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7474' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4707$777_EN' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7475' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4709$778_ADDR' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7476' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4709$778_DATA' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7477' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4709$778_EN' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7478' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4711$779_ADDR' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7479' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4711$779_DATA' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7480' with positive edge clock.
Creating register for signal `\top.$memwr$\mem$top.v:4711$779_EN' using process `\top.$proc$top.v:4703$1681'.
  created $dff cell `$procdff$7481' with positive edge clock.
Creating register for signal `\top.\state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7482' with positive edge clock.
Creating register for signal `\top.\usb_rx_line_state_phase' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7483' with positive edge clock.
Creating register for signal `\top.\usb_rx_line_state_valid' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7484' with positive edge clock.
Creating register for signal `\top.\usb_rx_line_state_dj1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7485' with positive edge clock.
Creating register for signal `\top.\usb_rx_line_state_dk1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7486' with positive edge clock.
Creating register for signal `\top.\usb_rx_line_state_se01' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7487' with positive edge clock.
Creating register for signal `\top.\usb_rx_line_state_se11' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7488' with positive edge clock.
Creating register for signal `\top.\usb_rx_nrzi_o_valid1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7489' with positive edge clock.
Creating register for signal `\top.\usb_rx_nrzi_o_data1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7490' with positive edge clock.
Creating register for signal `\top.\usb_rx_nrzi_o_se0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7491' with positive edge clock.
Creating register for signal `\top.\usb_rx_bitstuff_o_valid' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7492' with positive edge clock.
Creating register for signal `\top.\usb_rx_bitstuff_o_data' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7493' with positive edge clock.
Creating register for signal `\top.\usb_rx_bitstuff_o_se0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7494' with positive edge clock.
Creating register for signal `\top.\usb_rx_bitstuff_o_bitstuff_error' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7495' with positive edge clock.
Creating register for signal `\top.\usb_rx_valid' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7496' with positive edge clock.
Creating register for signal `\top.\usb_rx_data' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7497' with positive edge clock.
Creating register for signal `\top.\usb_rx_se0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7498' with positive edge clock.
Creating register for signal `\top.\usb_rx_bitstuff_error' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7499' with positive edge clock.
Creating register for signal `\top.\usb_rx_o_pkt_start' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7500' with positive edge clock.
Creating register for signal `\top.\usb_rx_o_pkt_active' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7501' with positive edge clock.
Creating register for signal `\top.\usb_rx_o_pkt_end' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7502' with positive edge clock.
Creating register for signal `\top.\usb_rx_pkt_active1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7503' with positive edge clock.
Creating register for signal `\top.\usb_rx_pkt_end1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7504' with positive edge clock.
Creating register for signal `\top.\usb_rx_shift_reg' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7505' with positive edge clock.
Creating register for signal `\top.\usb_rx_o_put' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7506' with positive edge clock.
Creating register for signal `\top.\usb_rx_data_n0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7507' with positive edge clock.
Creating register for signal `\top.\usb_rx_data_n1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7508' with positive edge clock.
Creating register for signal `\top.\usb_rx_o_pid' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7509' with positive edge clock.
Creating register for signal `\top.\usb_rx_o_addr' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7510' with positive edge clock.
Creating register for signal `\top.\usb_rx_o_ep' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7511' with positive edge clock.
Creating register for signal `\top.\usb_tx_sync_shifter_shifter' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7512' with positive edge clock.
Creating register for signal `\top.\usb_tx_sync_shifter_not_empty' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7513' with positive edge clock.
Creating register for signal `\top.\usb_tx_pid_shifter_shifter' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7514' with positive edge clock.
Creating register for signal `\top.\usb_tx_pid_shifter_not_empty' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7515' with positive edge clock.
Creating register for signal `\top.\usb_tx_data_shifter_shifter' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7516' with positive edge clock.
Creating register for signal `\top.\usb_tx_data_shifter_not_empty' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7517' with positive edge clock.
Creating register for signal `\top.\usb_tx_crc' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7518' with positive edge clock.
Creating register for signal `\top.\usb_tx_crc16_shifter_shifter' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7519' with positive edge clock.
Creating register for signal `\top.\usb_tx_crc16_shifter_not_empty' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7520' with positive edge clock.
Creating register for signal `\top.\usb_tx_pid_is_data' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7521' with positive edge clock.
Creating register for signal `\top.\usb_tx_mux_stuff_oe' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7522' with positive edge clock.
Creating register for signal `\top.\usb_tx_mux_stuff_data' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7523' with positive edge clock.
Creating register for signal `\top.\usb_tx_mux_stuff_se0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7524' with positive edge clock.
Creating register for signal `\top.\usb_tx_mux_stuff_bit_strobe' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7525' with positive edge clock.
Creating register for signal `\top.\usb_tx_bitstuffer_o_data' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7526' with positive edge clock.
Creating register for signal `\top.\usb_tx_bitstuffer_o_se0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7527' with positive edge clock.
Creating register for signal `\top.\usb_tx_bitstuffer_o_oe' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7528' with positive edge clock.
Creating register for signal `\top.\usb_tx_nrzi_o_usbp' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7529' with positive edge clock.
Creating register for signal `\top.\usb_tx_nrzi_o_usbn' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7530' with positive edge clock.
Creating register for signal `\top.\usb_tx_nrzi_o_oe' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7531' with positive edge clock.
Creating register for signal `\top.\usb_tx_o_data_get' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7532' with positive edge clock.
Creating register for signal `\top.\usb_tx_o_pkt_end' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7533' with positive edge clock.
Creating register for signal `\top.\usb_tx_o_usbp' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7534' with positive edge clock.
Creating register for signal `\top.\usb_tx_o_usbn' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7535' with positive edge clock.
Creating register for signal `\top.\usb_tx_o_oe' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7536' with positive edge clock.
Creating register for signal `\top.\usb_transfer_tok' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7537' with positive edge clock.
Creating register for signal `\top.\usb_ep_addr' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7538' with positive edge clock.
Creating register for signal `\top.\usb_response_pid' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7539' with positive edge clock.
Creating register for signal `\top.\usb_signal_is_el0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7540' with positive edge clock.
Creating register for signal `\top.\usb_signal_is_el1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7541' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_outbuf_graycounter0_q' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7542' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_outbuf_graycounter0_q_binary' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7543' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_readable' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7544' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_dout' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7545' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_graycounter1_q' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7546' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_graycounter1_q_binary' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7547' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_readable' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7548' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_dout' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7549' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_graycounter3_q' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7550' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_graycounter3_q_binary' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7551' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_outbuf_graycounter2_q' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7552' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_outbuf_graycounter2_q_binary' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7553' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_readable' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7554' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_dout' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7555' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_graycounter5_q' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7556' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_graycounter5_q_binary' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7557' with positive edge clock.
Creating register for signal `\top.\usbfsrx_rxclockdatarecovery_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7558' with positive edge clock.
Creating register for signal `\top.\usbfsrx_rxnrzidecoder_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7559' with positive edge clock.
Creating register for signal `\top.\usbfsrx_rxbitstuffremover_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7560' with positive edge clock.
Creating register for signal `\top.\usbfsrx_rxpacketdetect_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7561' with positive edge clock.
Creating register for signal `\top.\usbfsrx_fsm_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7562' with positive edge clock.
Creating register for signal `\top.\usbfstx_fsm_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7563' with positive edge clock.
Creating register for signal `\top.\usbfstx_txbitstuffer_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7564' with positive edge clock.
Creating register for signal `\top.\usbfstx_txnrziencoder_state' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7565' with positive edge clock.
Creating register for signal `\top.\multiregimpl1_regs0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7566' with positive edge clock.
Creating register for signal `\top.\multiregimpl1_regs1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7567' with positive edge clock.
Creating register for signal `\top.\multiregimpl1_regs2' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7568' with positive edge clock.
Creating register for signal `\top.\multiregimpl2_regs0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7569' with positive edge clock.
Creating register for signal `\top.\multiregimpl2_regs1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7570' with positive edge clock.
Creating register for signal `\top.\multiregimpl2_regs2' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7571' with positive edge clock.
Creating register for signal `\top.\multiregimpl4_regs0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7572' with positive edge clock.
Creating register for signal `\top.\multiregimpl4_regs1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7573' with positive edge clock.
Creating register for signal `\top.\multiregimpl5_regs0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7574' with positive edge clock.
Creating register for signal `\top.\multiregimpl5_regs1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7575' with positive edge clock.
Creating register for signal `\top.\multiregimpl7_regs0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7576' with positive edge clock.
Creating register for signal `\top.\multiregimpl7_regs1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7577' with positive edge clock.
Creating register for signal `\top.\multiregimpl10_regs0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7578' with positive edge clock.
Creating register for signal `\top.\multiregimpl10_regs1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7579' with positive edge clock.
Creating register for signal `\top.\multiregimpl11_regs0' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7580' with positive edge clock.
Creating register for signal `\top.\multiregimpl11_regs1' using process `\top.$proc$top.v:4267$1575'.
  created $dff cell `$procdff$7581' with positive edge clock.
Creating register for signal `\top.\serial_tx' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7582' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_ctrl_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7583' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_ctrl_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7584' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_ctrl_bus_errors' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7585' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_sram_bus_ack' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7586' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_interface_adr' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7587' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_interface_we' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7588' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_interface_dat_w' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7589' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_bus_wishbone_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7590' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_bus_wishbone_ack' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7591' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_counter' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7592' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7593' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7594' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_sink_ready' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7595' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_uart_clk_txen' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7596' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_phase_accumulator_tx' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7597' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_tx_reg' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7598' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_tx_bitcount' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7599' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_tx_busy' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7600' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_source_valid' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7601' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_source_payload_data' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7602' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_uart_clk_rxen' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7603' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_phase_accumulator_rx' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7604' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_rx_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7605' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_rx_reg' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7606' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_rx_bitcount' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7607' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_phy_rx_busy' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7608' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_tx_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7609' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_tx_old_trigger' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7610' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_rx_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7611' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_rx_old_trigger' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7612' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_eventmanager_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7613' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_eventmanager_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7614' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_readable' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7615' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_level0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7616' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_produce' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7617' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_tx_fifo_consume' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7618' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_rx_fifo_readable' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7619' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_rx_fifo_level0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7620' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_rx_fifo_produce' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7621' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_uart_rx_fifo_consume' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7622' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_load_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7623' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_load_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7624' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_reload_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7625' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_reload_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7626' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_en_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7627' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_en_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7628' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_value_status' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7629' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_zero_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7630' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_zero_old_trigger' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7631' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_eventmanager_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7632' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_eventmanager_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7633' with positive edge clock.
Creating register for signal `\top.\usbsoc_usbsoc_timer0_value' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7634' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_bus_ack' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7635' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_bitbang_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7636' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_bitbang_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7637' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_bitbang_en_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7638' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_bitbang_en_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7639' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_cs_n1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7640' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_clk1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7641' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_sr' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7642' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_i' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7643' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_miso1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7644' with positive edge clock.
Creating register for signal `\top.\usbsoc_spiflash_counter' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7645' with positive edge clock.
Creating register for signal `\top.\usb_pullup_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7646' with positive edge clock.
Creating register for signal `\top.\usb_pullup_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7647' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_error_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7648' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_packet_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7649' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_eventmanager0_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7650' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_eventmanager0_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7651' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_last_tok_status' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7652' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_respond_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7653' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_respond_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7654' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_dtb_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7655' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_dtb_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7656' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_dtb_we' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7657' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_toggle' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7658' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_outbuf_readable' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7659' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_outbuf_dout' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7660' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_outbuf_graycounter1_q' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7661' with positive edge clock.
Creating register for signal `\top.\usb_endpointout0_outbuf_graycounter1_q_binary' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7662' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_error_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7663' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_packet_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7664' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_eventmanager0_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7665' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_eventmanager0_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7666' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_last_tok_status' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7667' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_respond_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7668' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_respond_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7669' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_dtb_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7670' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_dtb_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7671' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_dtb_we' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7672' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_toggle' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7673' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_graycounter0_q' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7674' with positive edge clock.
Creating register for signal `\top.\usb_endpointin0_graycounter0_q_binary' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7675' with positive edge clock.
Creating register for signal `\top.\usb_oep_status' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7676' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_error_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7677' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_packet_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7678' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_eventmanager1_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7679' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_eventmanager1_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7680' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_last_tok_status' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7681' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_respond_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7682' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_respond_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7683' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_dtb_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7684' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_dtb_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7685' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_dtb_we' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7686' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_toggle' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7687' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_graycounter2_q' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7688' with positive edge clock.
Creating register for signal `\top.\usb_endpointin1_graycounter2_q_binary' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7689' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_error_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7690' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_packet_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7691' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_eventmanager1_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7692' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_eventmanager1_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7693' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_last_tok_status' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7694' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_respond_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7695' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_respond_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7696' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_dtb_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7697' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_dtb_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7698' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_dtb_we' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7699' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_toggle' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7700' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_outbuf_readable' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7701' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_outbuf_dout' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7702' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_outbuf_graycounter3_q' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7703' with positive edge clock.
Creating register for signal `\top.\usb_endpointout1_outbuf_graycounter3_q_binary' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7704' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_error_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7705' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_packet_pending' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7706' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_eventmanager2_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7707' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_eventmanager2_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7708' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_last_tok_status' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7709' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_respond_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7710' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_respond_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7711' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_dtb_storage_full' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7712' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_dtb_re' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7713' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_dtb_we' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7714' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_toggle' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7715' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_graycounter4_q' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7716' with positive edge clock.
Creating register for signal `\top.\usb_endpointin2_graycounter4_q_binary' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7717' with positive edge clock.
Creating register for signal `\top.\grant' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7718' with positive edge clock.
Creating register for signal `\top.\slave_sel_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7719' with positive edge clock.
Creating register for signal `\top.\count' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7720' with positive edge clock.
Creating register for signal `\top.\interface0_bank_bus_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7721' with positive edge clock.
Creating register for signal `\top.\sel_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7722' with positive edge clock.
Creating register for signal `\top.\interface1_bank_bus_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7723' with positive edge clock.
Creating register for signal `\top.\interface2_bank_bus_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7724' with positive edge clock.
Creating register for signal `\top.\interface3_bank_bus_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7725' with positive edge clock.
Creating register for signal `\top.\interface4_bank_bus_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7726' with positive edge clock.
Creating register for signal `\top.\interface5_bank_bus_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7727' with positive edge clock.
Creating register for signal `\top.\interface6_bank_bus_dat_r' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7728' with positive edge clock.
Creating register for signal `\top.\array_muxed' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7729' with positive edge clock.
Creating register for signal `\top.\multiregimpl0_regs0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7730' with positive edge clock.
Creating register for signal `\top.\multiregimpl0_regs1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7731' with positive edge clock.
Creating register for signal `\top.\multiregimpl3_regs0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7732' with positive edge clock.
Creating register for signal `\top.\multiregimpl3_regs1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7733' with positive edge clock.
Creating register for signal `\top.\multiregimpl6_regs0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7734' with positive edge clock.
Creating register for signal `\top.\multiregimpl6_regs1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7735' with positive edge clock.
Creating register for signal `\top.\multiregimpl8_regs0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7736' with positive edge clock.
Creating register for signal `\top.\multiregimpl8_regs1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7737' with positive edge clock.
Creating register for signal `\top.\multiregimpl9_regs0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7738' with positive edge clock.
Creating register for signal `\top.\multiregimpl9_regs1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7739' with positive edge clock.
Creating register for signal `\top.\multiregimpl12_regs0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7740' with positive edge clock.
Creating register for signal `\top.\multiregimpl12_regs1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7741' with positive edge clock.
Creating register for signal `\top.\multiregimpl13_regs0' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7742' with positive edge clock.
Creating register for signal `\top.\multiregimpl13_regs1' using process `\top.$proc$top.v:3156$1470'.
  created $dff cell `$procdff$7743' with positive edge clock.
Creating register for signal `\top.\usbsoc_reset_delay' using process `\top.$proc$top.v:3147$1467'.
  created $dff cell `$procdff$7744' with positive edge clock.
Creating register for signal `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.\refill_offset' using process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:486$2882'.
  created $dff cell `$procdff$7745' with positive edge clock.
Creating register for signal `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.\state' using process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:400$2866'.
  created $dff cell `$procdff$7746' with positive edge clock.
Creating register for signal `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.\restart_request' using process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:400$2866'.
  created $dff cell `$procdff$7747' with positive edge clock.
Creating register for signal `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.\refill_address' using process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:400$2866'.
  created $dff cell `$procdff$7748' with positive edge clock.
Creating register for signal `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.\flush_set' using process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:400$2866'.
  created $dff cell `$procdff$7749' with positive edge clock.
Creating register for signal `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.\refilling' using process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:391$2864'.
  created $dff cell `$procdff$7750' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\bus_error_d' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:934$2838'.
  created $dff cell `$procdff$7751' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\instruction_d' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:934$2838'.
  created $dff cell `$procdff$7752' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\i_adr_o' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7753' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\i_cyc_o' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7754' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\i_stb_o' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7755' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\i_cti_o' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7756' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\i_lock_o' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7757' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\icache_refill_ready' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7758' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\icache_refill_data' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7759' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\bus_error_f' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
  created $dff cell `$procdff$7760' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\restart_address' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:686$2822'.
  created $dff cell `$procdff$7761' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\pc_f' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
  created $dff cell `$procdff$7762' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\pc_d' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
  created $dff cell `$procdff$7763' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\pc_x' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
  created $dff cell `$procdff$7764' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\pc_m' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
  created $dff cell `$procdff$7765' with positive edge clock.
Creating register for signal `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.\pc_w' using process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
  created $dff cell `$procdff$7766' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\size_w' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:859$2330'.
  created $dff cell `$procdff$7767' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\sign_extend_w' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:859$2330'.
  created $dff cell `$procdff$7768' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\data_w' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:859$2330'.
  created $dff cell `$procdff$7769' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\size_m' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
  created $dff cell `$procdff$7770' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\sign_extend_m' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
  created $dff cell `$procdff$7771' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\store_data_m' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
  created $dff cell `$procdff$7772' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\byte_enable_m' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
  created $dff cell `$procdff$7773' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\wb_select_m' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
  created $dff cell `$procdff$7774' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\stall_wb_load' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7775' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_dat_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7776' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_adr_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7777' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_cyc_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7778' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_sel_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7779' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_stb_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7780' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_we_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7781' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_cti_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7782' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\d_lock_o' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7783' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\wb_data_m' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7784' with positive edge clock.
Creating register for signal `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.\wb_load_complete' using process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
  created $dff cell `$procdff$7785' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\sign_extend_x' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7786' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\divide_by_zero_x' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7787' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\result_x' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7788' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\p' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7789' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\a' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7790' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\b' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7791' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\state' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7792' with positive edge clock.
Creating register for signal `\lm32_mc_arithmetic.\cycles' using process `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
  created $dff cell `$procdff$7793' with positive edge clock.
Creating register for signal `\lm32_interrupt.\ie' using process `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:232$132'.
  created $dff cell `$procdff$7794' with positive edge clock.
Creating register for signal `\lm32_interrupt.\eie' using process `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:232$132'.
  created $dff cell `$procdff$7795' with positive edge clock.
Creating register for signal `\lm32_interrupt.\im' using process `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:232$132'.
  created $dff cell `$procdff$7796' with positive edge clock.

21.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2908'.
Removing empty process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2908'.
Found and cleaned up 1 empty switch in `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2901'.
Removing empty process `$paramod\lm32_ram\data_width=32\address_width=9.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2901'.
Found and cleaned up 1 empty switch in `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2897'.
Removing empty process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:124$2897'.
Found and cleaned up 1 empty switch in `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2890'.
Removing empty process `$paramod\lm32_ram\data_width=22\address_width=7.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:119$2890'.
Found and cleaned up 1 empty switch in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3033$2774'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3033$2774'.
Found and cleaned up 8 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2678$2744'.
Found and cleaned up 13 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2628$2720'.
Found and cleaned up 2 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2604$2716'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2604$2716'.
Found and cleaned up 3 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2555$2708'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2555$2708'.
Found and cleaned up 1 empty switch in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2544$2705'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2544$2705'.
Found and cleaned up 2 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2509$2698'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2509$2698'.
Found and cleaned up 1 empty switch in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2290$2697'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2290$2697'.
Found and cleaned up 4 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1892$2563'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1892$2563'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1661$2492'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1651$2490'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1631$2485'.
Found and cleaned up 1 empty switch in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1615$2477'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1615$2477'.
Found and cleaned up 1 empty switch in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1581$2472'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1581$2472'.
Found and cleaned up 3 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1551$2463'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1551$2463'.
Found and cleaned up 3 empty switches in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1538$2459'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1538$2459'.
Found and cleaned up 1 empty switch in `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1519$2439'.
Removing empty process `$paramod\lm32_cpu\eba_reset=537198592.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1519$2439'.
Removing empty process `top.$proc$top.v:1180$2200'.
Removing empty process `top.$proc$top.v:1179$2199'.
Removing empty process `top.$proc$top.v:1178$2198'.
Removing empty process `top.$proc$top.v:1177$2197'.
Removing empty process `top.$proc$top.v:1176$2196'.
Removing empty process `top.$proc$top.v:1175$2195'.
Removing empty process `top.$proc$top.v:1174$2194'.
Removing empty process `top.$proc$top.v:1173$2193'.
Removing empty process `top.$proc$top.v:1172$2192'.
Removing empty process `top.$proc$top.v:1171$2191'.
Removing empty process `top.$proc$top.v:1170$2190'.
Removing empty process `top.$proc$top.v:1169$2189'.
Removing empty process `top.$proc$top.v:1168$2188'.
Removing empty process `top.$proc$top.v:1167$2187'.
Removing empty process `top.$proc$top.v:1166$2186'.
Removing empty process `top.$proc$top.v:1165$2185'.
Removing empty process `top.$proc$top.v:1164$2184'.
Removing empty process `top.$proc$top.v:1163$2183'.
Removing empty process `top.$proc$top.v:1162$2182'.
Removing empty process `top.$proc$top.v:1161$2181'.
Removing empty process `top.$proc$top.v:1160$2180'.
Removing empty process `top.$proc$top.v:1159$2179'.
Removing empty process `top.$proc$top.v:1158$2178'.
Removing empty process `top.$proc$top.v:1157$2177'.
Removing empty process `top.$proc$top.v:1156$2176'.
Removing empty process `top.$proc$top.v:1155$2175'.
Removing empty process `top.$proc$top.v:1154$2174'.
Removing empty process `top.$proc$top.v:1153$2173'.
Removing empty process `top.$proc$top.v:1151$2172'.
Removing empty process `top.$proc$top.v:1150$2171'.
Removing empty process `top.$proc$top.v:1149$2170'.
Removing empty process `top.$proc$top.v:1148$2169'.
Removing empty process `top.$proc$top.v:1147$2168'.
Removing empty process `top.$proc$top.v:1146$2167'.
Removing empty process `top.$proc$top.v:1145$2166'.
Removing empty process `top.$proc$top.v:1144$2165'.
Removing empty process `top.$proc$top.v:1143$2164'.
Removing empty process `top.$proc$top.v:1142$2163'.
Removing empty process `top.$proc$top.v:1141$2162'.
Removing empty process `top.$proc$top.v:1139$2161'.
Removing empty process `top.$proc$top.v:1138$2160'.
Removing empty process `top.$proc$top.v:1135$2159'.
Removing empty process `top.$proc$top.v:1134$2158'.
Removing empty process `top.$proc$top.v:1133$2157'.
Removing empty process `top.$proc$top.v:1132$2156'.
Removing empty process `top.$proc$top.v:1098$2155'.
Removing empty process `top.$proc$top.v:1081$2154'.
Removing empty process `top.$proc$top.v:1070$2153'.
Removing empty process `top.$proc$top.v:1026$2152'.
Removing empty process `top.$proc$top.v:1012$2151'.
Removing empty process `top.$proc$top.v:899$2150'.
Removing empty process `top.$proc$top.v:895$2149'.
Removing empty process `top.$proc$top.v:891$2148'.
Removing empty process `top.$proc$top.v:862$2147'.
Removing empty process `top.$proc$top.v:858$2146'.
Removing empty process `top.$proc$top.v:855$2145'.
Removing empty process `top.$proc$top.v:854$2144'.
Removing empty process `top.$proc$top.v:853$2143'.
Removing empty process `top.$proc$top.v:852$2142'.
Removing empty process `top.$proc$top.v:846$2141'.
Removing empty process `top.$proc$top.v:842$2140'.
Removing empty process `top.$proc$top.v:809$2139'.
Removing empty process `top.$proc$top.v:808$2138'.
Removing empty process `top.$proc$top.v:807$2137'.
Removing empty process `top.$proc$top.v:806$2136'.
Removing empty process `top.$proc$top.v:805$2135'.
Removing empty process `top.$proc$top.v:804$2134'.
Removing empty process `top.$proc$top.v:803$2133'.
Removing empty process `top.$proc$top.v:802$2132'.
Removing empty process `top.$proc$top.v:801$2131'.
Removing empty process `top.$proc$top.v:800$2130'.
Removing empty process `top.$proc$top.v:799$2129'.
Removing empty process `top.$proc$top.v:798$2128'.
Removing empty process `top.$proc$top.v:797$2127'.
Removing empty process `top.$proc$top.v:796$2126'.
Removing empty process `top.$proc$top.v:795$2125'.
Removing empty process `top.$proc$top.v:794$2124'.
Removing empty process `top.$proc$top.v:793$2123'.
Removing empty process `top.$proc$top.v:792$2122'.
Removing empty process `top.$proc$top.v:791$2121'.
Removing empty process `top.$proc$top.v:790$2120'.
Removing empty process `top.$proc$top.v:789$2119'.
Removing empty process `top.$proc$top.v:788$2118'.
Removing empty process `top.$proc$top.v:787$2117'.
Removing empty process `top.$proc$top.v:786$2116'.
Removing empty process `top.$proc$top.v:780$2115'.
Removing empty process `top.$proc$top.v:779$2114'.
Removing empty process `top.$proc$top.v:778$2113'.
Removing empty process `top.$proc$top.v:776$2112'.
Removing empty process `top.$proc$top.v:765$2111'.
Removing empty process `top.$proc$top.v:764$2110'.
Removing empty process `top.$proc$top.v:762$2109'.
Removing empty process `top.$proc$top.v:760$2108'.
Removing empty process `top.$proc$top.v:759$2107'.
Removing empty process `top.$proc$top.v:757$2106'.
Removing empty process `top.$proc$top.v:749$2105'.
Removing empty process `top.$proc$top.v:748$2104'.
Removing empty process `top.$proc$top.v:747$2103'.
Removing empty process `top.$proc$top.v:746$2102'.
Removing empty process `top.$proc$top.v:744$2101'.
Removing empty process `top.$proc$top.v:743$2100'.
Removing empty process `top.$proc$top.v:741$2099'.
Removing empty process `top.$proc$top.v:740$2098'.
Removing empty process `top.$proc$top.v:736$2097'.
Removing empty process `top.$proc$top.v:734$2096'.
Removing empty process `top.$proc$top.v:733$2095'.
Removing empty process `top.$proc$top.v:729$2094'.
Removing empty process `top.$proc$top.v:727$2093'.
Removing empty process `top.$proc$top.v:726$2092'.
Removing empty process `top.$proc$top.v:723$2091'.
Removing empty process `top.$proc$top.v:720$2090'.
Removing empty process `top.$proc$top.v:719$2089'.
Removing empty process `top.$proc$top.v:718$2088'.
Removing empty process `top.$proc$top.v:716$2087'.
Removing empty process `top.$proc$top.v:715$2086'.
Removing empty process `top.$proc$top.v:714$2085'.
Removing empty process `top.$proc$top.v:711$2084'.
Removing empty process `top.$proc$top.v:710$2083'.
Removing empty process `top.$proc$top.v:709$2082'.
Removing empty process `top.$proc$top.v:696$2081'.
Removing empty process `top.$proc$top.v:695$2080'.
Removing empty process `top.$proc$top.v:693$2079'.
Removing empty process `top.$proc$top.v:691$2078'.
Removing empty process `top.$proc$top.v:690$2077'.
Removing empty process `top.$proc$top.v:688$2076'.
Removing empty process `top.$proc$top.v:685$2075'.
Removing empty process `top.$proc$top.v:681$2074'.
Removing empty process `top.$proc$top.v:680$2073'.
Removing empty process `top.$proc$top.v:679$2072'.
Removing empty process `top.$proc$top.v:677$2071'.
Removing empty process `top.$proc$top.v:675$2070'.
Removing empty process `top.$proc$top.v:674$2069'.
Removing empty process `top.$proc$top.v:672$2068'.
Removing empty process `top.$proc$top.v:671$2067'.
Removing empty process `top.$proc$top.v:667$2066'.
Removing empty process `top.$proc$top.v:665$2065'.
Removing empty process `top.$proc$top.v:664$2064'.
Removing empty process `top.$proc$top.v:660$2063'.
Removing empty process `top.$proc$top.v:658$2062'.
Removing empty process `top.$proc$top.v:657$2061'.
Removing empty process `top.$proc$top.v:654$2060'.
Removing empty process `top.$proc$top.v:651$2059'.
Removing empty process `top.$proc$top.v:650$2058'.
Removing empty process `top.$proc$top.v:649$2057'.
Removing empty process `top.$proc$top.v:647$2056'.
Removing empty process `top.$proc$top.v:646$2055'.
Removing empty process `top.$proc$top.v:645$2054'.
Removing empty process `top.$proc$top.v:642$2053'.
Removing empty process `top.$proc$top.v:641$2052'.
Removing empty process `top.$proc$top.v:640$2051'.
Removing empty process `top.$proc$top.v:638$2050'.
Removing empty process `top.$proc$top.v:627$2049'.
Removing empty process `top.$proc$top.v:626$2048'.
Removing empty process `top.$proc$top.v:624$2047'.
Removing empty process `top.$proc$top.v:622$2046'.
Removing empty process `top.$proc$top.v:621$2045'.
Removing empty process `top.$proc$top.v:619$2044'.
Removing empty process `top.$proc$top.v:611$2043'.
Removing empty process `top.$proc$top.v:610$2042'.
Removing empty process `top.$proc$top.v:609$2041'.
Removing empty process `top.$proc$top.v:608$2040'.
Removing empty process `top.$proc$top.v:606$2039'.
Removing empty process `top.$proc$top.v:605$2038'.
Removing empty process `top.$proc$top.v:603$2037'.
Removing empty process `top.$proc$top.v:602$2036'.
Removing empty process `top.$proc$top.v:598$2035'.
Removing empty process `top.$proc$top.v:596$2034'.
Removing empty process `top.$proc$top.v:595$2033'.
Removing empty process `top.$proc$top.v:591$2032'.
Removing empty process `top.$proc$top.v:589$2031'.
Removing empty process `top.$proc$top.v:588$2030'.
Removing empty process `top.$proc$top.v:585$2029'.
Removing empty process `top.$proc$top.v:582$2028'.
Removing empty process `top.$proc$top.v:581$2027'.
Removing empty process `top.$proc$top.v:580$2026'.
Removing empty process `top.$proc$top.v:578$2025'.
Removing empty process `top.$proc$top.v:577$2024'.
Removing empty process `top.$proc$top.v:576$2023'.
Removing empty process `top.$proc$top.v:573$2022'.
Removing empty process `top.$proc$top.v:572$2021'.
Removing empty process `top.$proc$top.v:571$2020'.
Removing empty process `top.$proc$top.v:570$2019'.
Removing empty process `top.$proc$top.v:569$2018'.
Removing empty process `top.$proc$top.v:568$2017'.
Removing empty process `top.$proc$top.v:567$2016'.
Removing empty process `top.$proc$top.v:566$2015'.
Removing empty process `top.$proc$top.v:565$2014'.
Removing empty process `top.$proc$top.v:564$2013'.
Removing empty process `top.$proc$top.v:563$2012'.
Removing empty process `top.$proc$top.v:562$2011'.
Removing empty process `top.$proc$top.v:561$2010'.
Removing empty process `top.$proc$top.v:559$2009'.
Removing empty process `top.$proc$top.v:548$2008'.
Removing empty process `top.$proc$top.v:547$2007'.
Removing empty process `top.$proc$top.v:545$2006'.
Removing empty process `top.$proc$top.v:543$2005'.
Removing empty process `top.$proc$top.v:542$2004'.
Removing empty process `top.$proc$top.v:540$2003'.
Removing empty process `top.$proc$top.v:532$2002'.
Removing empty process `top.$proc$top.v:531$2001'.
Removing empty process `top.$proc$top.v:530$2000'.
Removing empty process `top.$proc$top.v:529$1999'.
Removing empty process `top.$proc$top.v:527$1998'.
Removing empty process `top.$proc$top.v:526$1997'.
Removing empty process `top.$proc$top.v:524$1996'.
Removing empty process `top.$proc$top.v:519$1995'.
Removing empty process `top.$proc$top.v:517$1994'.
Removing empty process `top.$proc$top.v:516$1993'.
Removing empty process `top.$proc$top.v:512$1992'.
Removing empty process `top.$proc$top.v:510$1991'.
Removing empty process `top.$proc$top.v:509$1990'.
Removing empty process `top.$proc$top.v:506$1989'.
Removing empty process `top.$proc$top.v:503$1988'.
Removing empty process `top.$proc$top.v:502$1987'.
Removing empty process `top.$proc$top.v:501$1986'.
Removing empty process `top.$proc$top.v:499$1985'.
Removing empty process `top.$proc$top.v:498$1984'.
Removing empty process `top.$proc$top.v:497$1983'.
Removing empty process `top.$proc$top.v:494$1982'.
Removing empty process `top.$proc$top.v:493$1981'.
Removing empty process `top.$proc$top.v:492$1980'.
Removing empty process `top.$proc$top.v:479$1979'.
Removing empty process `top.$proc$top.v:478$1978'.
Removing empty process `top.$proc$top.v:476$1977'.
Removing empty process `top.$proc$top.v:474$1976'.
Removing empty process `top.$proc$top.v:473$1975'.
Removing empty process `top.$proc$top.v:471$1974'.
Removing empty process `top.$proc$top.v:468$1973'.
Removing empty process `top.$proc$top.v:464$1972'.
Removing empty process `top.$proc$top.v:463$1971'.
Removing empty process `top.$proc$top.v:462$1970'.
Removing empty process `top.$proc$top.v:460$1969'.
Removing empty process `top.$proc$top.v:458$1968'.
Removing empty process `top.$proc$top.v:457$1967'.
Removing empty process `top.$proc$top.v:455$1966'.
Removing empty process `top.$proc$top.v:450$1965'.
Removing empty process `top.$proc$top.v:448$1964'.
Removing empty process `top.$proc$top.v:447$1963'.
Removing empty process `top.$proc$top.v:443$1962'.
Removing empty process `top.$proc$top.v:441$1961'.
Removing empty process `top.$proc$top.v:440$1960'.
Removing empty process `top.$proc$top.v:437$1959'.
Removing empty process `top.$proc$top.v:434$1958'.
Removing empty process `top.$proc$top.v:433$1957'.
Removing empty process `top.$proc$top.v:432$1956'.
Removing empty process `top.$proc$top.v:430$1955'.
Removing empty process `top.$proc$top.v:429$1954'.
Removing empty process `top.$proc$top.v:428$1953'.
Removing empty process `top.$proc$top.v:424$1952'.
Removing empty process `top.$proc$top.v:422$1951'.
Removing empty process `top.$proc$top.v:421$1950'.
Removing empty process `top.$proc$top.v:419$1949'.
Removing empty process `top.$proc$top.v:416$1948'.
Removing empty process `top.$proc$top.v:413$1947'.
Removing empty process `top.$proc$top.v:411$1946'.
Removing empty process `top.$proc$top.v:406$1945'.
Removing empty process `top.$proc$top.v:405$1944'.
Removing empty process `top.$proc$top.v:404$1943'.
Removing empty process `top.$proc$top.v:403$1942'.
Removing empty process `top.$proc$top.v:402$1941'.
Removing empty process `top.$proc$top.v:401$1940'.
Removing empty process `top.$proc$top.v:400$1939'.
Removing empty process `top.$proc$top.v:399$1938'.
Removing empty process `top.$proc$top.v:398$1937'.
Removing empty process `top.$proc$top.v:397$1936'.
Removing empty process `top.$proc$top.v:396$1935'.
Removing empty process `top.$proc$top.v:395$1934'.
Removing empty process `top.$proc$top.v:394$1933'.
Removing empty process `top.$proc$top.v:393$1932'.
Removing empty process `top.$proc$top.v:392$1931'.
Removing empty process `top.$proc$top.v:391$1930'.
Removing empty process `top.$proc$top.v:390$1929'.
Removing empty process `top.$proc$top.v:389$1928'.
Removing empty process `top.$proc$top.v:388$1927'.
Removing empty process `top.$proc$top.v:387$1926'.
Removing empty process `top.$proc$top.v:385$1925'.
Removing empty process `top.$proc$top.v:384$1924'.
Removing empty process `top.$proc$top.v:383$1923'.
Removing empty process `top.$proc$top.v:382$1922'.
Removing empty process `top.$proc$top.v:381$1921'.
Removing empty process `top.$proc$top.v:380$1920'.
Removing empty process `top.$proc$top.v:379$1919'.
Removing empty process `top.$proc$top.v:376$1918'.
Removing empty process `top.$proc$top.v:375$1917'.
Removing empty process `top.$proc$top.v:373$1916'.
Removing empty process `top.$proc$top.v:372$1915'.
Removing empty process `top.$proc$top.v:369$1914'.
Removing empty process `top.$proc$top.v:368$1913'.
Removing empty process `top.$proc$top.v:365$1912'.
Removing empty process `top.$proc$top.v:364$1911'.
Removing empty process `top.$proc$top.v:361$1910'.
Removing empty process `top.$proc$top.v:360$1909'.
Removing empty process `top.$proc$top.v:359$1908'.
Removing empty process `top.$proc$top.v:358$1907'.
Removing empty process `top.$proc$top.v:357$1906'.
Removing empty process `top.$proc$top.v:356$1905'.
Removing empty process `top.$proc$top.v:355$1904'.
Removing empty process `top.$proc$top.v:354$1903'.
Removing empty process `top.$proc$top.v:353$1902'.
Removing empty process `top.$proc$top.v:352$1901'.
Removing empty process `top.$proc$top.v:348$1900'.
Removing empty process `top.$proc$top.v:347$1899'.
Removing empty process `top.$proc$top.v:346$1898'.
Removing empty process `top.$proc$top.v:345$1897'.
Removing empty process `top.$proc$top.v:344$1896'.
Removing empty process `top.$proc$top.v:343$1895'.
Removing empty process `top.$proc$top.v:342$1894'.
Removing empty process `top.$proc$top.v:341$1893'.
Removing empty process `top.$proc$top.v:340$1892'.
Removing empty process `top.$proc$top.v:339$1891'.
Removing empty process `top.$proc$top.v:338$1890'.
Removing empty process `top.$proc$top.v:337$1889'.
Removing empty process `top.$proc$top.v:336$1888'.
Removing empty process `top.$proc$top.v:335$1887'.
Removing empty process `top.$proc$top.v:334$1886'.
Removing empty process `top.$proc$top.v:333$1885'.
Removing empty process `top.$proc$top.v:330$1884'.
Removing empty process `top.$proc$top.v:329$1883'.
Removing empty process `top.$proc$top.v:328$1882'.
Removing empty process `top.$proc$top.v:327$1881'.
Removing empty process `top.$proc$top.v:326$1880'.
Removing empty process `top.$proc$top.v:325$1879'.
Removing empty process `top.$proc$top.v:324$1878'.
Removing empty process `top.$proc$top.v:323$1877'.
Removing empty process `top.$proc$top.v:322$1876'.
Removing empty process `top.$proc$top.v:321$1875'.
Removing empty process `top.$proc$top.v:320$1874'.
Removing empty process `top.$proc$top.v:319$1873'.
Removing empty process `top.$proc$top.v:318$1872'.
Removing empty process `top.$proc$top.v:317$1871'.
Removing empty process `top.$proc$top.v:316$1870'.
Removing empty process `top.$proc$top.v:315$1869'.
Removing empty process `top.$proc$top.v:314$1868'.
Removing empty process `top.$proc$top.v:313$1867'.
Removing empty process `top.$proc$top.v:312$1866'.
Removing empty process `top.$proc$top.v:311$1865'.
Removing empty process `top.$proc$top.v:310$1864'.
Removing empty process `top.$proc$top.v:309$1863'.
Removing empty process `top.$proc$top.v:308$1862'.
Removing empty process `top.$proc$top.v:307$1861'.
Removing empty process `top.$proc$top.v:306$1860'.
Removing empty process `top.$proc$top.v:305$1859'.
Removing empty process `top.$proc$top.v:304$1858'.
Removing empty process `top.$proc$top.v:303$1857'.
Removing empty process `top.$proc$top.v:302$1856'.
Removing empty process `top.$proc$top.v:301$1855'.
Removing empty process `top.$proc$top.v:300$1854'.
Removing empty process `top.$proc$top.v:299$1853'.
Removing empty process `top.$proc$top.v:298$1852'.
Removing empty process `top.$proc$top.v:297$1851'.
Removing empty process `top.$proc$top.v:296$1850'.
Removing empty process `top.$proc$top.v:292$1849'.
Removing empty process `top.$proc$top.v:290$1848'.
Removing empty process `top.$proc$top.v:286$1847'.
Removing empty process `top.$proc$top.v:285$1846'.
Removing empty process `top.$proc$top.v:281$1845'.
Removing empty process `top.$proc$top.v:280$1844'.
Removing empty process `top.$proc$top.v:279$1843'.
Removing empty process `top.$proc$top.v:278$1842'.
Removing empty process `top.$proc$top.v:277$1841'.
Removing empty process `top.$proc$top.v:276$1840'.
Removing empty process `top.$proc$top.v:275$1839'.
Removing empty process `top.$proc$top.v:273$1838'.
Removing empty process `top.$proc$top.v:272$1837'.
Removing empty process `top.$proc$top.v:271$1836'.
Removing empty process `top.$proc$top.v:269$1835'.
Removing empty process `top.$proc$top.v:268$1834'.
Removing empty process `top.$proc$top.v:264$1833'.
Removing empty process `top.$proc$top.v:254$1832'.
Removing empty process `top.$proc$top.v:251$1831'.
Removing empty process `top.$proc$top.v:250$1830'.
Removing empty process `top.$proc$top.v:246$1829'.
Removing empty process `top.$proc$top.v:242$1828'.
Removing empty process `top.$proc$top.v:240$1827'.
Removing empty process `top.$proc$top.v:233$1826'.
Removing empty process `top.$proc$top.v:232$1825'.
Removing empty process `top.$proc$top.v:230$1824'.
Removing empty process `top.$proc$top.v:227$1823'.
Removing empty process `top.$proc$top.v:226$1822'.
Removing empty process `top.$proc$top.v:223$1821'.
Removing empty process `top.$proc$top.v:221$1820'.
Removing empty process `top.$proc$top.v:220$1819'.
Removing empty process `top.$proc$top.v:218$1818'.
Removing empty process `top.$proc$top.v:217$1817'.
Removing empty process `top.$proc$top.v:215$1816'.
Removing empty process `top.$proc$top.v:214$1815'.
Removing empty process `top.$proc$top.v:199$1814'.
Removing empty process `top.$proc$top.v:198$1813'.
Removing empty process `top.$proc$top.v:197$1812'.
Removing empty process `top.$proc$top.v:196$1811'.
Removing empty process `top.$proc$top.v:195$1810'.
Removing empty process `top.$proc$top.v:188$1809'.
Removing empty process `top.$proc$top.v:162$1808'.
Removing empty process `top.$proc$top.v:161$1807'.
Removing empty process `top.$proc$top.v:160$1806'.
Removing empty process `top.$proc$top.v:159$1805'.
Removing empty process `top.$proc$top.v:158$1804'.
Removing empty process `top.$proc$top.v:151$1803'.
Removing empty process `top.$proc$top.v:143$1802'.
Removing empty process `top.$proc$top.v:142$1801'.
Removing empty process `top.$proc$top.v:136$1800'.
Removing empty process `top.$proc$top.v:134$1799'.
Removing empty process `top.$proc$top.v:133$1798'.
Removing empty process `top.$proc$top.v:130$1797'.
Removing empty process `top.$proc$top.v:127$1796'.
Removing empty process `top.$proc$top.v:126$1795'.
Removing empty process `top.$proc$top.v:124$1794'.
Removing empty process `top.$proc$top.v:122$1793'.
Removing empty process `top.$proc$top.v:121$1792'.
Removing empty process `top.$proc$top.v:119$1791'.
Removing empty process `top.$proc$top.v:111$1790'.
Removing empty process `top.$proc$top.v:110$1789'.
Removing empty process `top.$proc$top.v:109$1788'.
Removing empty process `top.$proc$top.v:108$1787'.
Removing empty process `top.$proc$top.v:106$1786'.
Removing empty process `top.$proc$top.v:105$1785'.
Removing empty process `top.$proc$top.v:104$1784'.
Removing empty process `top.$proc$top.v:103$1783'.
Removing empty process `top.$proc$top.v:102$1782'.
Removing empty process `top.$proc$top.v:100$1781'.
Removing empty process `top.$proc$top.v:99$1780'.
Removing empty process `top.$proc$top.v:98$1779'.
Removing empty process `top.$proc$top.v:97$1778'.
Removing empty process `top.$proc$top.v:96$1777'.
Removing empty process `top.$proc$top.v:95$1776'.
Removing empty process `top.$proc$top.v:91$1775'.
Removing empty process `top.$proc$top.v:89$1774'.
Removing empty process `top.$proc$top.v:87$1773'.
Removing empty process `top.$proc$top.v:86$1772'.
Removing empty process `top.$proc$top.v:85$1771'.
Removing empty process `top.$proc$top.v:81$1770'.
Removing empty process `top.$proc$top.v:77$1769'.
Removing empty process `top.$proc$top.v:73$1768'.
Removing empty process `top.$proc$top.v:72$1767'.
Removing empty process `top.$proc$top.v:71$1766'.
Removing empty process `top.$proc$top.v:69$1765'.
Removing empty process `top.$proc$top.v:66$1764'.
Removing empty process `top.$proc$top.v:62$1763'.
Removing empty process `top.$proc$top.v:53$1762'.
Removing empty process `top.$proc$top.v:29$1761'.
Removing empty process `top.$proc$top.v:25$1760'.
Removing empty process `top.$proc$top.v:23$1759'.
Removing empty process `top.$proc$top.v:22$1758'.
Removing empty process `top.$proc$top.v:4876$1743'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4870$1739'.
Removing empty process `top.$proc$top.v:4870$1739'.
Removing empty process `top.$proc$top.v:4860$1736'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4854$1732'.
Removing empty process `top.$proc$top.v:4854$1732'.
Removing empty process `top.$proc$top.v:4844$1729'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4838$1725'.
Removing empty process `top.$proc$top.v:4838$1725'.
Removing empty process `top.$proc$top.v:4828$1722'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4822$1718'.
Removing empty process `top.$proc$top.v:4822$1718'.
Removing empty process `top.$proc$top.v:4812$1715'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4806$1711'.
Removing empty process `top.$proc$top.v:4806$1711'.
Removing empty process `top.$proc$top.v:4753$1709'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4743$1707'.
Removing empty process `top.$proc$top.v:4743$1707'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4737$1702'.
Removing empty process `top.$proc$top.v:4737$1702'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4726$1700'.
Removing empty process `top.$proc$top.v:4726$1700'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:4720$1695'.
Removing empty process `top.$proc$top.v:4720$1695'.
Found and cleaned up 4 empty switches in `\top.$proc$top.v:4703$1681'.
Removing empty process `top.$proc$top.v:4703$1681'.
Found and cleaned up 68 empty switches in `\top.$proc$top.v:4267$1575'.
Removing empty process `top.$proc$top.v:4267$1575'.
Found and cleaned up 157 empty switches in `\top.$proc$top.v:3156$1470'.
Removing empty process `top.$proc$top.v:3156$1470'.
Found and cleaned up 2 empty switches in `\top.$proc$top.v:3147$1467'.
Removing empty process `top.$proc$top.v:3147$1467'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3121$1466'.
Removing empty process `top.$proc$top.v:3121$1466'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3110$1465'.
Removing empty process `top.$proc$top.v:3110$1465'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3099$1464'.
Removing empty process `top.$proc$top.v:3099$1464'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3088$1463'.
Removing empty process `top.$proc$top.v:3088$1463'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3077$1462'.
Removing empty process `top.$proc$top.v:3077$1462'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3066$1461'.
Removing empty process `top.$proc$top.v:3066$1461'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3055$1460'.
Removing empty process `top.$proc$top.v:3055$1460'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3044$1459'.
Removing empty process `top.$proc$top.v:3044$1459'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:3021$1458'.
Removing empty process `top.$proc$top.v:3021$1458'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2998$1457'.
Removing empty process `top.$proc$top.v:2998$1457'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2975$1456'.
Removing empty process `top.$proc$top.v:2975$1456'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2952$1455'.
Removing empty process `top.$proc$top.v:2952$1455'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2929$1454'.
Removing empty process `top.$proc$top.v:2929$1454'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2601$1118'.
Removing empty process `top.$proc$top.v:2601$1118'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2559$1080'.
Removing empty process `top.$proc$top.v:2559$1080'.
Removing empty process `top.$proc$top.v:2527$1068'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2502$1053'.
Removing empty process `top.$proc$top.v:2502$1053'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2493$1050'.
Removing empty process `top.$proc$top.v:2493$1050'.
Removing empty process `top.$proc$top.v:2469$1036'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2463$1034'.
Removing empty process `top.$proc$top.v:2463$1034'.
Removing empty process `top.$proc$top.v:2458$1033'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2452$1031'.
Removing empty process `top.$proc$top.v:2452$1031'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2436$1024'.
Removing empty process `top.$proc$top.v:2436$1024'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2427$1021'.
Removing empty process `top.$proc$top.v:2427$1021'.
Removing empty process `top.$proc$top.v:2403$1007'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2397$1005'.
Removing empty process `top.$proc$top.v:2397$1005'.
Removing empty process `top.$proc$top.v:2392$1004'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2386$1002'.
Removing empty process `top.$proc$top.v:2386$1002'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2370$995'.
Removing empty process `top.$proc$top.v:2370$995'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2361$992'.
Removing empty process `top.$proc$top.v:2361$992'.
Removing empty process `top.$proc$top.v:2337$978'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2331$976'.
Removing empty process `top.$proc$top.v:2331$976'.
Removing empty process `top.$proc$top.v:2326$975'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2320$973'.
Removing empty process `top.$proc$top.v:2320$973'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2304$966'.
Removing empty process `top.$proc$top.v:2304$966'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2295$963'.
Removing empty process `top.$proc$top.v:2295$963'.
Removing empty process `top.$proc$top.v:2271$949'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2265$947'.
Removing empty process `top.$proc$top.v:2265$947'.
Removing empty process `top.$proc$top.v:2260$946'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2254$944'.
Removing empty process `top.$proc$top.v:2254$944'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2238$937'.
Removing empty process `top.$proc$top.v:2238$937'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2229$934'.
Removing empty process `top.$proc$top.v:2229$934'.
Removing empty process `top.$proc$top.v:2205$920'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2199$918'.
Removing empty process `top.$proc$top.v:2199$918'.
Removing empty process `top.$proc$top.v:2194$917'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:2188$915'.
Removing empty process `top.$proc$top.v:2188$915'.
Found and cleaned up 16 empty switches in `\top.$proc$top.v:2073$902'.
Removing empty process `top.$proc$top.v:2073$902'.
Found and cleaned up 12 empty switches in `\top.$proc$top.v:2000$893'.
Removing empty process `top.$proc$top.v:2000$893'.
Found and cleaned up 14 empty switches in `\top.$proc$top.v:1933$892'.
Removing empty process `top.$proc$top.v:1933$892'.
Removing empty process `top.$proc$top.v:1911$874'.
Found and cleaned up 11 empty switches in `\top.$proc$top.v:1826$869'.
Removing empty process `top.$proc$top.v:1826$869'.
Found and cleaned up 11 empty switches in `\top.$proc$top.v:1755$865'.
Removing empty process `top.$proc$top.v:1755$865'.
Found and cleaned up 15 empty switches in `\top.$proc$top.v:1680$859'.
Removing empty process `top.$proc$top.v:1680$859'.
Found and cleaned up 14 empty switches in `\top.$proc$top.v:1613$858'.
Removing empty process `top.$proc$top.v:1613$858'.
Found and cleaned up 7 empty switches in `\top.$proc$top.v:1579$857'.
Removing empty process `top.$proc$top.v:1579$857'.
Found and cleaned up 6 empty switches in `\top.$proc$top.v:1527$852'.
Removing empty process `top.$proc$top.v:1527$852'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1515$851'.
Removing empty process `top.$proc$top.v:1515$851'.
Found and cleaned up 3 empty switches in `\top.$proc$top.v:1498$850'.
Removing empty process `top.$proc$top.v:1498$850'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1456$846'.
Removing empty process `top.$proc$top.v:1456$846'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1425$845'.
Removing empty process `top.$proc$top.v:1425$845'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1396$844'.
Removing empty process `top.$proc$top.v:1396$844'.
Found and cleaned up 2 empty switches in `\top.$proc$top.v:1353$842'.
Removing empty process `top.$proc$top.v:1353$842'.
Found and cleaned up 2 empty switches in `\top.$proc$top.v:1332$841'.
Removing empty process `top.$proc$top.v:1332$841'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1310$837'.
Removing empty process `top.$proc$top.v:1310$837'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1292$829'.
Removing empty process `top.$proc$top.v:1292$829'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1262$818'.
Removing empty process `top.$proc$top.v:1262$818'.
Removing empty process `top.$proc$top.v:1238$810'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1232$808'.
Removing empty process `top.$proc$top.v:1232$808'.
Removing empty process `top.$proc$top.v:1227$807'.
Found and cleaned up 1 empty switch in `\top.$proc$top.v:1221$805'.
Removing empty process `top.$proc$top.v:1221$805'.
Removing empty process `top.$proc$top.v:1193$788'.
Removing empty process `top.$proc$top.v:1184$787'.
Removing empty process `lm32_logic_op.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_logic_op.v:90$743'.
Found and cleaned up 5 empty switches in `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:486$2882'.
Removing empty process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:486$2882'.
Found and cleaned up 9 empty switches in `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:400$2866'.
Removing empty process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:400$2866'.
Found and cleaned up 1 empty switch in `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:391$2864'.
Removing empty process `$paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:391$2864'.
Found and cleaned up 2 empty switches in `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:934$2838'.
Removing empty process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:934$2838'.
Found and cleaned up 7 empty switches in `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
Removing empty process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:743$2825'.
Found and cleaned up 2 empty switches in `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:686$2822'.
Removing empty process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:686$2822'.
Found and cleaned up 5 empty switches in `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
Removing empty process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:649$2816'.
Found and cleaned up 4 empty switches in `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:539$2806'.
Removing empty process `$paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:539$2806'.
Found and cleaned up 1 empty switch in `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:859$2330'.
Removing empty process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:859$2330'.
Found and cleaned up 2 empty switches in `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
Removing empty process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:817$2327'.
Found and cleaned up 8 empty switches in `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
Removing empty process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:683$2303'.
Found and cleaned up 1 empty switch in `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:632$2296'.
Removing empty process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:632$2296'.
Found and cleaned up 1 empty switch in `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:518$2295'.
Removing empty process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:518$2295'.
Found and cleaned up 1 empty switch in `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:507$2294'.
Removing empty process `$paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:507$2294'.
Found and cleaned up 16 empty switches in `\lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
Removing empty process `lm32_mc_arithmetic.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:169$515'.
Found and cleaned up 1 empty switch in `\lm32_adder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_adder.v:123$140'.
Removing empty process `lm32_adder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_adder.v:123$140'.
Found and cleaned up 7 empty switches in `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:232$132'.
Removing empty process `lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:232$132'.
Found and cleaned up 1 empty switch in `\lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:181$131'.
Removing empty process `lm32_interrupt.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:181$131'.
Found and cleaned up 9 empty switches in `\lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
Removing empty process `lm32_decoder.$proc$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:429$76'.
Cleaned up 528 empty switches.

21.4. Executing FLATTEN pass (flatten design).
Mapping top.lm32_cpu using $paramod\lm32_cpu\eba_reset=537198592.
Mapping top.lm32_cpu.interrupt_unit using lm32_interrupt.
Mapping top.lm32_cpu.instruction_unit using $paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.
Mapping top.lm32_cpu.decoder using lm32_decoder.
Mapping top.lm32_cpu.mc_arithmetic using lm32_mc_arithmetic.
Mapping top.lm32_cpu.logic_op using lm32_logic_op.
Mapping top.lm32_cpu.adder using lm32_adder.
Mapping top.lm32_cpu.load_store_unit using $paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.
Mapping top.lm32_cpu.instruction_unit.icache using $paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.
Mapping top.lm32_cpu.adder.addsub using lm32_addsub.
Mapping top.lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram using $paramod\lm32_ram\data_width=22\address_width=7.
Mapping top.lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram using $paramod\lm32_ram\data_width=32\address_width=9.
No more expansions possible.
Deleting now unused module $paramod\lm32_ram\data_width=32\address_width=9.
Deleting now unused module $paramod\lm32_ram\data_width=22\address_width=7.
Deleting now unused module $paramod\lm32_cpu\eba_reset=537198592.
Deleting now unused module lm32_logic_op.
Deleting now unused module lm32_addsub.
Deleting now unused module $paramod$7c70905518e59e078352e4b78b72b31e4446d25e\lm32_icache.
Deleting now unused module $paramod$710498318592c8be5f114de8869564230145c3f7\lm32_instruction_unit.
Deleting now unused module $paramod$1796e813439a8159decab8f38b7eea89783ffd3d\lm32_load_store_unit.
Deleting now unused module lm32_mc_arithmetic.
Deleting now unused module lm32_adder.
Deleting now unused module lm32_interrupt.
Deleting now unused module lm32_decoder.

21.5. Executing TRIBUF pass.

21.6. Executing DEMINOUT pass (demote inout ports to input or output).

21.7. Executing SYNTH pass.

21.7.1. Executing PROC pass (convert processes to netlists).

21.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.7.1.3. Executing PROC_INIT pass (extract init attributes).

21.7.1.4. Executing PROC_ARST pass (detect async resets in processes).

21.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).

21.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs).

21.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.7.2. Executing OPT_EXPR pass (perform const folding).
Replacing $eq cell `$procmux$5406_CMP0' in module `top' with $logic_not.
Optimizing away select inverter for $mux cell `$procmux$6357' in module `top'.
Replacing $mux cell `$procmux$3929' (0) in module `\top' with constant driver `$procmux$3929_Y = $procmux$3926_Y'.
Replacing $eq cell `$procmux$6339_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$6310_CMP0' in module `top' with $logic_not.
Replacing $ne cell `$ne$top.v:1307$835' in module `top' with $logic_not.
Replacing $or cell `$or$top.v:1301$831' (and_or_buffer) in module `\top' with constant driver `$or$top.v:1301$831_Y = $ne$top.v:1306$834_Y'.
Replacing $mux cell `$procmux$6431' (0) in module `\top' with constant driver `$procmux$6431_Y = \usbsoc_usbsoc_uart_rx_fifo_produce'.
Replacing $ne cell `$ne$top.v:1277$824' in module `top' with $logic_not.
Replacing $or cell `$or$top.v:1271$820' (and_or_buffer) in module `\top' with constant driver `$or$top.v:1271$820_Y = $ne$top.v:1276$823_Y'.
Replacing $eq cell `$eq$top.v:2782$1292' in module `top' with $logic_not.
Replacing $mux cell `$procmux$6434' (0) in module `\top' with constant driver `$procmux$6434_Y = \usbsoc_usbsoc_uart_tx_fifo_produce'.
Replacing $eq cell `$procmux$5378_CMP0' in module `top' with inverter.
Replacing $eq cell `$procmux$5369_CMP0' in module `top' with inverter.
Replacing $eq cell `$procmux$5366_CMP0' in module `top' with inverter.
Replacing $eq cell `$procmux$5363_CMP0' in module `top' with inverter.
Replacing $eq cell `$procmux$5372_CMP0' in module `top' with inverter.
Replacing $eq cell `$procmux$5375_CMP0' in module `top' with inverter.
Replacing $mux cell `$procmux$3923' (0) in module `\top' with constant driver `$procmux$3923_Y = $procmux$3920_Y'.
Replacing $mux cell `$procmux$3534' (0) in module `\top' with constant driver `$procmux$3534_Y = $procmux$3531_Y'.
Replacing $mux cell `$procmux$3543' (0) in module `\top' with constant driver `$procmux$3543_Y = $procmux$3540_Y'.
Replacing $mux cell `$procmux$3552' (0) in module `\top' with constant driver `$procmux$3552_Y = $procmux$3549_Y'.
Replacing $mux cell `$procmux$3561' (0) in module `\top' with constant driver `$procmux$3561_Y = $procmux$3558_Y'.
Replacing $mux cell `$procmux$3570' (0) in module `\top' with constant driver `$procmux$3570_Y = $procmux$3567_Y'.
Replacing $eq cell `$procmux$5392_CMP0' in module `top' with $logic_not.
Optimizing away select inverter for $mux cell `$procmux$5828' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5839' in module `top'.
Replacing $mux cell `$procmux$3579' (0) in module `\top' with constant driver `$procmux$3579_Y = $procmux$3576_Y'.
Replacing $mux cell `$procmux$3615' (0) in module `\top' with constant driver `$procmux$3615_Y = $procmux$3612_Y'.
Replacing $mux cell `$procmux$3588' (0) in module `\top' with constant driver `$procmux$3588_Y = $procmux$3585_Y'.
Replacing $mux cell `$procmux$3624' (0) in module `\top' with constant driver `$procmux$3624_Y = $procmux$3621_Y'.
Replacing $mux cell `$procmux$3597' (0) in module `\top' with constant driver `$procmux$3597_Y = $procmux$3594_Y'.
Replacing $mux cell `$procmux$3633' (0) in module `\top' with constant driver `$procmux$3633_Y = $procmux$3630_Y'.
Replacing $mux cell `$procmux$3606' (0) in module `\top' with constant driver `$procmux$3606_Y = $procmux$3603_Y'.
Replacing $mux cell `$procmux$3690' (0) in module `\top' with constant driver `$procmux$3690_Y = \usb_endpointin0_graycounter1_q_next'.
Replacing $mux cell `$procmux$3660' (0) in module `\top' with constant driver `$procmux$3660_Y = $procmux$3657_Y'.
Replacing $mux cell `$procmux$3669' (0) in module `\top' with constant driver `$procmux$3669_Y = $procmux$3666_Y'.
Replacing $eq cell `$procmux$6284_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$3672' (0) in module `\top' with constant driver `$procmux$3672_Y = \usb_endpointin2_graycounter5_q_next'.
Replacing $mux cell `$procmux$3642' (0) in module `\top' with constant driver `$procmux$3642_Y = $procmux$3639_Y'.
Replacing $mux cell `$procmux$3675' (0) in module `\top' with constant driver `$procmux$3675_Y = \usb_endpointin2_graycounter5_q_next_binary'.
Replacing $mux cell `$procmux$3678' (0) in module `\top' with constant driver `$procmux$3678_Y = \usb_endpointout1_outbuf_graycounter2_q_next'.
Replacing $mux cell `$procmux$3681' (0) in module `\top' with constant driver `$procmux$3681_Y = \usb_endpointout1_outbuf_graycounter2_q_next_binary'.
Replacing $mux cell `$procmux$3944' (0) in module `\top' with constant driver `$procmux$3944_Y = $procmux$3941_Y'.
Replacing $mux cell `$procmux$3684' (0) in module `\top' with constant driver `$procmux$3684_Y = \usb_endpointin1_graycounter3_q_next'.
Replacing $mux cell `$procmux$3687' (0) in module `\top' with constant driver `$procmux$3687_Y = \usb_endpointin1_graycounter3_q_next_binary'.
Replacing $mux cell `$procmux$3651' (0) in module `\top' with constant driver `$procmux$3651_Y = $procmux$3648_Y'.
Replacing $eq cell `$procmux$5413_CMP0' in module `top' with $logic_not.
Replacing $ne cell `$ne$top.v:2131$907' in module `top' with $logic_not.
Replacing $mux cell `$procmux$5524' (0) in module `\top' with constant driver `$procmux$5524_Y = \state'.
Replacing $eq cell `$procmux$5526_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$3705' (0) in module `\top' with constant driver `$procmux$3705_Y = \usb_fsm_is_el1'.
Replacing $mux cell `$procmux$3708' (0) in module `\top' with constant driver `$procmux$3708_Y = \usb_fsm_is_el0'.
Replacing $mux cell `$procmux$3711' (0) in module `\top' with constant driver `$procmux$3711_Y = \usbfstx_txnrziencoder_next_state'.
Replacing $mux cell `$procmux$3714' (0) in module `\top' with constant driver `$procmux$3714_Y = \usb_tx_nrzi_usbn'.
Replacing $mux cell `$procmux$3693' (0) in module `\top' with constant driver `$procmux$3693_Y = \usb_endpointin0_graycounter1_q_next_binary'.
Replacing $mux cell `$procmux$3717' (0) in module `\top' with constant driver `$procmux$3717_Y = \usb_tx_nrzi_usbp'.
Replacing $mux cell `$procmux$3696' (0) in module `\top' with constant driver `$procmux$3696_Y = \usb_endpointout0_outbuf_graycounter0_q_next'.
Replacing $sshr cell `$sshr$top.v:4514$1666' (B=1'1, SHR=1) in module `top' with fixed wiring: { 1'0 \usb_tx_crc16_shifter_shifter [16:1] }
Replacing $mux cell `$procmux$3720' (0) in module `\top' with constant driver `$procmux$3720_Y = \usb_tx_nrzi_oe'.
Replacing $mux cell `$procmux$3699' (0) in module `\top' with constant driver `$procmux$3699_Y = \usb_endpointout0_outbuf_graycounter0_q_next_binary'.
Replacing $mux cell `$procmux$3723' (0) in module `\top' with constant driver `$procmux$3723_Y = \usbfstx_txbitstuffer_next_state'.
Optimizing away select inverter for $mux cell `$procmux$5758' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5765' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5775' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5779' in module `top'.
Replacing $mux cell `$procmux$3726' (0) in module `\top' with constant driver `$procmux$3726_Y = \usbfstx_fsm_next_state'.
Replacing $mux cell `$procmux$3702' (0) in module `\top' with constant driver `$procmux$3702_Y = \next_state'.
Replacing $mux cell `$procmux$3735' (0) in module `\top' with constant driver `$procmux$3735_Y = \usb_tx_nrzi_o_usbp'.
Replacing $mux cell `$procmux$3729' (0) in module `\top' with constant driver `$procmux$3729_Y = \usb_tx_nrzi_o_oe'.
Replacing $mux cell `$procmux$3738' (0) in module `\top' with constant driver `$procmux$3738_Y = \usb_tx_pkt_end'.
Optimizing away select inverter for $mux cell `$procmux$5856' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5867' in module `top'.
Replacing $mux cell `$procmux$3741' (0) in module `\top' with constant driver `$procmux$3741_Y = \usb_tx_load_data'.
Replacing $mux cell `$procmux$3732' (0) in module `\top' with constant driver `$procmux$3732_Y = \usb_tx_nrzi_o_usbn'.
Replacing $ne cell `$ne$top.v:1308$836' in module `top' with $logic_not.
Replacing $ne cell `$ne$top.v:1324$840' in module `top' with $logic_not.
Replacing $ne cell `$ne$top.v:1550$855' in module `top' with $logic_not.
Replacing $or cell `$or$top.v:2316$971' (and_or_buffer) in module `\top' with constant driver `$or$top.v:2316$971_Y = $not$top.v:2316$970_Y'.
Replacing $or cell `$or$top.v:2382$1000' (and_or_buffer) in module `\top' with constant driver `$or$top.v:2382$1000_Y = $not$top.v:2382$999_Y'.
Replacing $or cell `$or$top.v:2448$1029' (and_or_buffer) in module `\top' with constant driver `$or$top.v:2448$1029_Y = $not$top.v:2448$1028_Y'.
Replacing $eq cell `$eq$top.v:2522$1060' in module `top' with inverter.
Replacing $eq cell `$eq$top.v:2571$1088' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:2523$1062' (1) in module `\top' with constant driver `$eq$top.v:2523$1062_Y = \grant'.
Replacing $eq cell `$eq$top.v:2524$1064' in module `top' with inverter.
Replacing $or cell `$or$top.v:2557$1075' in module `\top' with identity for port A.
Replacing $or cell `$or$top.v:2557$1076' (and_or_buffer) in module `\top' with constant driver `$or$top.v:2557$1076_Y = $or$top.v:2557$1075_Y'.
Replacing $eq cell `$eq$top.v:2525$1066' (1) in module `\top' with constant driver `$eq$top.v:2525$1066_Y = \grant'.
Replacing $eq cell `$eq$top.v:2572$1089' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:2574$1091' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:2610$1121' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:2719$1230' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:2731$1240' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:2797$1311' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:2811$1324' in module `top' with $logic_not.
Replacing $ne cell `$ne$top.v:3148$1468' in module `top' with $logic_not.
Replacing $ne cell `$ne$top.v:3179$1479' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:3224$1495' in module `top' with $logic_not.
Replacing $not cell `$not$top.v:3250$1498' (double_invert) in module `\top' with constant driver `$not$top.v:3250$1498_Y = $ne$top.v:1276$823_Y'.
Replacing $not cell `$not$top.v:3257$1500' (double_invert) in module `\top' with constant driver `$not$top.v:3257$1500_Y = \usbsoc_usbsoc_uart_rx_fifo_readable'.
Replacing $not cell `$not$top.v:3271$1503' (1'0) in module `\top' with constant driver `$not$top.v:3271$1503_Y = 1'1'.
Replacing $and cell `$and$top.v:3271$1504' (and_or_buffer) in module `\top' with constant driver `$and$top.v:3271$1504_Y = $and$top.v:3271$1502_Y'.
Replacing $not cell `$not$top.v:3277$1508' (1'0) in module `\top' with constant driver `$not$top.v:3277$1508_Y = 1'1'.
Replacing $and cell `$and$top.v:3277$1509' (and_or_buffer) in module `\top' with constant driver `$and$top.v:3277$1509_Y = $and$top.v:3277$1507_Y'.
Replacing $not cell `$not$top.v:3293$1514' (1'0) in module `\top' with constant driver `$not$top.v:3293$1514_Y = 1'1'.
Replacing $and cell `$and$top.v:3293$1515' (and_or_buffer) in module `\top' with constant driver `$and$top.v:3293$1515_Y = $and$top.v:3293$1513_Y'.
Replacing $not cell `$not$top.v:3299$1519' (1'0) in module `\top' with constant driver `$not$top.v:3299$1519_Y = 1'1'.
Replacing $and cell `$and$top.v:3299$1520' (and_or_buffer) in module `\top' with constant driver `$and$top.v:3299$1520_Y = $and$top.v:3299$1518_Y'.
Replacing $eq cell `$eq$top.v:3325$1524' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:3347$1528' in module `top' with inverter.
Replacing $eq cell `$eq$top.v:3351$1529' (1) in module `\top' with constant driver `$eq$top.v:3351$1529_Y = \usbsoc_spiflash_i'.
Replacing $eq cell `$eq$top.v:3358$1532' (1) in module `\top' with constant driver `$eq$top.v:3358$1532_Y = \usbsoc_spiflash_i'.
Replacing $eq cell `$eq$top.v:3358$1534' in module `top' with $logic_not.
Replacing $ne cell `$ne$top.v:3379$1542' in module `top' with $logic_not.
Replacing $eq cell `$eq$top.v:3382$1545' (1) in module `\top' with constant driver `$eq$top.v:3382$1545_Y = \usbsoc_spiflash_i'.
Replacing $eq cell `$procmux$6365_CMP0' in module `top' with $logic_not.
Optimizing away select inverter for $mux cell `$procmux$6403' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$6367' in module `top'.
Replacing $sshl cell `$sshl$top.v:3441$1549' (B=1'0, SHR=0) in module `top' with fixed wiring: 2'01
Replacing $sshl cell `$sshl$top.v:3448$1550' (B=1'0, SHR=0) in module `top' with fixed wiring: $or$top.v:2184$913_Y
Optimizing away select inverter for $mux cell `$procmux$6382' in module `top'.
Replacing $sshl cell `$sshl$top.v:3487$1555' (B=1'0, SHR=0) in module `top' with fixed wiring: 2'01
Replacing $sshl cell `$sshl$top.v:3494$1556' (B=1'0, SHR=0) in module `top' with fixed wiring: $or$top.v:2250$942_Y
Optimizing away select inverter for $mux cell `$procmux$6410' in module `top'.
Replacing $or cell `$or$top.v:3502$1557' (and_or_buffer) in module `\top' with constant driver `$or$top.v:3502$1557_Y = $procmux$6410_Y'.
Replacing $sshl cell `$sshl$top.v:3529$1559' (B=1'0, SHR=0) in module `top' with fixed wiring: 2'01
Replacing $sshl cell `$sshl$top.v:3536$1560' (B=1'0, SHR=0) in module `top' with fixed wiring: $not$top.v:2316$970_Y
Optimizing away select inverter for $mux cell `$procmux$6373' in module `top'.
Replacing $or cell `$or$top.v:3544$1561' (and_or_buffer) in module `\top' with constant driver `$or$top.v:3544$1561_Y = $procmux$6373_Y'.
Replacing $sshl cell `$sshl$top.v:3571$1563' (B=1'0, SHR=0) in module `top' with fixed wiring: 2'01
Replacing $sshl cell `$sshl$top.v:3578$1564' (B=1'0, SHR=0) in module `top' with fixed wiring: $not$top.v:2382$999_Y
Replacing $eq cell `$procmux$6390_CMP0' in module `top' with $logic_not.
Optimizing away select inverter for $mux cell `$procmux$6392' in module `top'.
Replacing $or cell `$or$top.v:3590$1567' (and_or_buffer) in module `\top' with constant driver `$or$top.v:3590$1567_Y = $procmux$6392_Y'.
Replacing $sshl cell `$sshl$top.v:3617$1569' (B=1'0, SHR=0) in module `top' with fixed wiring: 2'01
Replacing $sshl cell `$sshl$top.v:3624$1570' (B=1'0, SHR=0) in module `top' with fixed wiring: $not$top.v:2448$1028_Y
Replacing $sshr cell `$sshr$top.v:4360$1589' (B=1'1, SHR=1) in module `top' with fixed wiring: { 1'0 \usb_tx_sync_shifter_shifter [8:1] }
Replacing $sshr cell `$sshr$top.v:4374$1598' (B=1'1, SHR=1) in module `top' with fixed wiring: { 1'0 \usb_tx_pid_shifter_shifter [8:1] }
Replacing $sshr cell `$sshr$top.v:4388$1607' (B=1'1, SHR=1) in module `top' with fixed wiring: { 1'0 \usb_tx_data_shifter_shifter [8:1] }
Replacing $mux cell `$procmux$3785' (0) in module `\top' with constant driver `$procmux$3785_Y = \usbfsrx_fsm_next_state'.
Replacing $mux cell `$procmux$3788' (0) in module `\top' with constant driver `$procmux$3788_Y = $and$top.v:4317$1584_Y'.
Replacing $mux cell `$procmux$3791' (0) in module `\top' with constant driver `$procmux$3791_Y = \usbfsrx_rxpacketdetect_next_state'.
Replacing $mux cell `$procmux$3794' (0) in module `\top' with constant driver `$procmux$3794_Y = \usb_rx_pkt_end0'.
Replacing $mux cell `$procmux$3758' (0) in module `\top' with constant driver `$procmux$3758_Y = $procmux$3755_Y'.
Replacing $mux cell `$procmux$3797' (0) in module `\top' with constant driver `$procmux$3797_Y = \usb_rx_pkt_active0'.
Replacing $mux cell `$procmux$3800' (0) in module `\top' with constant driver `$procmux$3800_Y = \usb_rx_pkt_start'.
Replacing $mux cell `$procmux$3953' (0) in module `\top' with constant driver `$procmux$3953_Y = $procmux$3950_Y'.
Replacing $mux cell `$procmux$3803' (0) in module `\top' with constant driver `$procmux$3803_Y = \usb_rx_o_pkt_end'.
Replacing $mux cell `$procmux$3806' (0) in module `\top' with constant driver `$procmux$3806_Y = \usb_rx_o_pkt_active'.
Replacing $mux cell `$procmux$3809' (0) in module `\top' with constant driver `$procmux$3809_Y = \usb_rx_bitstuff_o_bitstuff_error'.
Replacing $mux cell `$procmux$3812' (0) in module `\top' with constant driver `$procmux$3812_Y = \usb_rx_bitstuff_o_se0'.
Replacing $mux cell `$procmux$3776' (0) in module `\top' with constant driver `$procmux$3776_Y = $procmux$3773_Y'.
Replacing $mux cell `$procmux$3815' (0) in module `\top' with constant driver `$procmux$3815_Y = \usb_rx_bitstuff_o_data'.
Replacing $mux cell `$procmux$3779' (0) in module `\top' with constant driver `$procmux$3779_Y = \usb_tx_pkt_active'.
Replacing $mux cell `$procmux$3818' (0) in module `\top' with constant driver `$procmux$3818_Y = \usb_rx_bitstuff_o_valid'.
Replacing $mux cell `$procmux$3782' (0) in module `\top' with constant driver `$procmux$3782_Y = \usb_rx_line_state_valid'.
Replacing $mux cell `$procmux$3821' (0) in module `\top' with constant driver `$procmux$3821_Y = \usbfsrx_rxbitstuffremover_next_state'.
Replacing $mux cell `$procmux$3824' (0) in module `\top' with constant driver `$procmux$3824_Y = $and$top.v:4287$1580_Y'.
Replacing $mux cell `$procmux$3827' (0) in module `\top' with constant driver `$procmux$3827_Y = \usb_rx_nrzi_o_data1'.
Replacing $mux cell `$procmux$3866' (0) in module `\top' with constant driver `$procmux$3866_Y = $procmux$3863_Y'.
Replacing $mux cell `$procmux$3830' (0) in module `\top' with constant driver `$procmux$3830_Y = $and$top.v:4285$1579_Y'.
Replacing $mux cell `$procmux$3833' (0) in module `\top' with constant driver `$procmux$3833_Y = \usb_rx_nrzi_o_se0'.
Replacing $mux cell `$procmux$3836' (0) in module `\top' with constant driver `$procmux$3836_Y = \usbfsrx_rxnrzidecoder_next_state'.
Replacing $mux cell `$procmux$3875' (0) in module `\top' with constant driver `$procmux$3875_Y = $procmux$3872_Y'.
Replacing $mux cell `$procmux$3839' (0) in module `\top' with constant driver `$procmux$3839_Y = \usb_rx_nrzi_o_data0'.
Replacing $mux cell `$procmux$3842' (0) in module `\top' with constant driver `$procmux$3842_Y = \usb_rx_nrzi_o_valid0'.
Replacing $mux cell `$procmux$3845' (0) in module `\top' with constant driver `$procmux$3845_Y = \usb_rx_line_state_se01'.
Replacing $mux cell `$procmux$3884' (0) in module `\top' with constant driver `$procmux$3884_Y = $procmux$3881_Y'.
Replacing $eq cell `$procmux$6196_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$3848' (0) in module `\top' with constant driver `$procmux$3848_Y = \usbfsrx_rxclockdatarecovery_next_state'.
Replacing $mux cell `$procmux$3851' (0) in module `\top' with constant driver `$procmux$3851_Y = \usb_rx_line_state_se10'.
Replacing $mux cell `$procmux$3854' (0) in module `\top' with constant driver `$procmux$3854_Y = \usb_rx_line_state_se00'.
Replacing $mux cell `$procmux$3893' (0) in module `\top' with constant driver `$procmux$3893_Y = $procmux$3890_Y'.
Replacing $mux cell `$procmux$3857' (0) in module `\top' with constant driver `$procmux$3857_Y = \usb_rx_line_state_dk0'.
Replacing $eq cell `$procmux$5564_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$5584_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$3860' (0) in module `\top' with constant driver `$procmux$3860_Y = \usb_rx_line_state_dj0'.
Replacing $mux cell `$procmux$3905' (0) in module `\top' with constant driver `$procmux$3905_Y = $procmux$3902_Y'.
Replacing $mux cell `$procmux$3962' (0) in module `\top' with constant driver `$procmux$3962_Y = $procmux$3959_Y'.
Replacing $mux cell `$procmux$3911' (0) in module `\top' with constant driver `$procmux$3911_Y = $procmux$3908_Y'.
Replacing $mux cell `$procmux$3899' (0) in module `\top' with constant driver `$procmux$3899_Y = $procmux$3896_Y'.
Replacing $mux cell `$procmux$3917' (0) in module `\top' with constant driver `$procmux$3917_Y = $procmux$3914_Y'.
Replacing $mux cell `$procmux$3935' (0) in module `\top' with constant driver `$procmux$3935_Y = $procmux$3932_Y'.
Replacing $mux cell `$procmux$3998' (0) in module `\top' with constant driver `$procmux$3998_Y = $procmux$3995_Y'.
Replacing $mux cell `$procmux$4031' (0) in module `\top' with constant driver `$procmux$4031_Y = $procmux$4028_Y'.
Replacing $mux cell `$procmux$3989' (0) in module `\top' with constant driver `$procmux$3989_Y = $procmux$3986_Y'.
Replacing $mux cell `$procmux$4025' (0) in module `\top' with constant driver `$procmux$4025_Y = $procmux$4022_Y'.
Replacing $mux cell `$procmux$4019' (0) in module `\top' with constant driver `$procmux$4019_Y = $procmux$4016_Y'.
Replacing $mux cell `$procmux$3980' (0) in module `\top' with constant driver `$procmux$3980_Y = $procmux$3977_Y'.
Replacing $mux cell `$procmux$4013' (0) in module `\top' with constant driver `$procmux$4013_Y = $procmux$4010_Y'.
Replacing $eq cell `$procmux$5385_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$3971' (0) in module `\top' with constant driver `$procmux$3971_Y = $procmux$3968_Y'.
Replacing $mux cell `$procmux$4007' (0) in module `\top' with constant driver `$procmux$4007_Y = $procmux$4004_Y'.
Replacing $mux cell `$procmux$4037' (0) in module `\top' with constant driver `$procmux$4037_Y = $procmux$4034_Y'.
Replacing $mux cell `$procmux$4052' (0) in module `\top' with constant driver `$procmux$4052_Y = $procmux$4049_Y'.
Replacing $mux cell `$procmux$4046' (0) in module `\top' with constant driver `$procmux$4046_Y = $procmux$4043_Y'.
Replacing $eq cell `$procmux$4202_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$4216_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$4230_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$4264_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$4281_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$4325_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$4348_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$4442' (0) in module `\top' with constant driver `$procmux$4442_Y = \usbsoc_usbsoc_uart_eventmanager_enable0_re'.
Replacing $mux cell `$procmux$4448' (0) in module `\top' with constant driver `$procmux$4448_Y = \usbsoc_usbsoc_uart_rx_trigger'.
Replacing $mux cell `$procmux$4454' (0) in module `\top' with constant driver `$procmux$4454_Y = \usbsoc_usbsoc_uart_tx_trigger'.
Optimizing away select inverter for $mux cell `$procmux$4475' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4518' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4529' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4537' in module `top'.
Replacing $eq cell `$procmux$4539_CMP0' in module `top' with inverter.
Optimizing away select inverter for $mux cell `$procmux$4545' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4554' in module `top'.
Replacing $mux cell `$procmux$4571' (0) in module `\top' with constant driver `$procmux$4571_Y = \usb_endpointin2_respond_storage_full'.
Replacing $eq cell `$procmux$4586_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$4611' (0) in module `\top' with constant driver `$procmux$4611_Y = $procmux$4608_Y'.
Optimizing away select inverter for $mux cell `$procmux$4627' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4636' in module `top'.
Replacing $mux cell `$procmux$4653' (0) in module `\top' with constant driver `$procmux$4653_Y = \usb_endpointout1_respond_storage_full'.
Replacing $mux cell `$procmux$4689' (0) in module `\top' with constant driver `$procmux$4689_Y = $procmux$4686_Y'.
Optimizing away select inverter for $mux cell `$procmux$4696' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4705' in module `top'.
Replacing $mux cell `$procmux$4722' (0) in module `\top' with constant driver `$procmux$4722_Y = \usb_endpointin1_respond_storage_full'.
Replacing $mux cell `$procmux$4759' (0) in module `\top' with constant driver `$procmux$4759_Y = $procmux$4756_Y'.
Optimizing away select inverter for $mux cell `$procmux$4777' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4786' in module `top'.
Replacing $mux cell `$procmux$4842' (0) in module `\top' with constant driver `$procmux$4842_Y = $procmux$4839_Y'.
Optimizing away select inverter for $mux cell `$procmux$4858' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4867' in module `top'.
Replacing $eq cell `$procmux$4899_CMP0' in module `top' with $logic_not.
Replacing $mux cell `$procmux$4924' (0) in module `\top' with constant driver `$procmux$4924_Y = $procmux$4921_Y'.
Replacing $mux cell `$procmux$5056' (0) in module `\top' with constant driver `$procmux$5056_Y = $procmux$5053_Y'.
Replacing $mux cell `$procmux$5065' (0) in module `\top' with constant driver `$procmux$5065_Y = $procmux$5062_Y'.
Optimizing away select inverter for $mux cell `$procmux$5075' in module `top'.
Replacing $mux cell `$procmux$5080' (0) in module `\top' with constant driver `$procmux$5080_Y = $procmux$5077_Y'.
Replacing $mux cell `$procmux$5092' (0) in module `\top' with constant driver `$procmux$5092_Y = $procmux$5089_Y'.
Replacing $mux cell `$procmux$5101' (0) in module `\top' with constant driver `$procmux$5101_Y = $procmux$5098_Y'.
Replacing $mux cell `$procmux$5110' (0) in module `\top' with constant driver `$procmux$5110_Y = $procmux$5107_Y'.
Optimizing away select inverter for $mux cell `$procmux$5120' in module `top'.
Replacing $mux cell `$procmux$5125' (0) in module `\top' with constant driver `$procmux$5125_Y = $procmux$5122_Y'.
Replacing $mux cell `$procmux$5137' (0) in module `\top' with constant driver `$procmux$5137_Y = $procmux$5134_Y'.
Replacing $mux cell `$procmux$5146' (0) in module `\top' with constant driver `$procmux$5146_Y = $procmux$5143_Y'.
Replacing $mux cell `$procmux$5158' (0) in module `\top' with constant driver `$procmux$5158_Y = $procmux$5155_Y'.
Replacing $mux cell `$procmux$5170' (0) in module `\top' with constant driver `$procmux$5170_Y = $procmux$5167_Y'.
Optimizing away select inverter for $mux cell `$procmux$5191' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5203' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5218' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5248' in module `top'.
Replacing $eq cell `$procmux$5357_CMP0' in module `top' with inverter.
Replacing $mux cell `$procmux$5356' (?) in module `\top' with constant driver `$procmux$5356_Y = \usbsoc_usbsoc_lm32_dbus_bte'.
Replacing $eq cell `$procmux$5360_CMP0' in module `top' with inverter.
Replacing $eq cell `$procmux$5399_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$6277_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$6298_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$procmux$6355_CMP0' in module `top' with $logic_not.
Optimizing away select inverter for $mux cell `$procmux$6400' in module `top'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2139$2678' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2139$2678_Y = \lm32_cpu.valid_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2139$2677' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2139$2677_Y = \lm32_cpu.write_enable_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1515$2434' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1515$2434_Y = \lm32_cpu.write_enable_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1528$2454' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1528$2454_Y = \lm32_cpu.raw_m_1'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1528$2453' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1528$2453_Y = \lm32_cpu.read_enable_1_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1512$2425' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1512$2425_Y = \lm32_cpu.write_enable_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1527$2451' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1527$2451_Y = \lm32_cpu.raw_m_0'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1527$2450' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1527$2450_Y = \lm32_cpu.read_enable_0_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1526$2449' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1712$2528' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1712$2528_Y = \lm32_cpu.exception_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1708$2524' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1708$2524_Y = \lm32_cpu.branch_predict_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1707$2522' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1707$2522_Y = \lm32_cpu.branch_predict_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1706$2521' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1705$2520' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1705$2520_Y = \lm32_cpu.condition_met_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1704$2518' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1704$2518_Y = \lm32_cpu.valid_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1703$2517' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1703$2517_Y = \lm32_cpu.branch_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2060$2619' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2060$2619_Y = \lm32_cpu.exception_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2060$2618' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2060$2618_Y = \lm32_cpu.branch_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2060$2617' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2060$2617_Y = \lm32_cpu.I_CYC_O'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:366$2862' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2059$2615' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2059$2615_Y = \lm32_cpu.icache_stall_request'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2051$2611' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2051$2611_Y = \lm32_cpu.load_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2050$2609' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2050$2609_Y = \lm32_cpu.load_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2048$2606' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2048$2606_Y = \lm32_cpu.interrupt_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2048$2605' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2048$2605_Y = \lm32_cpu.store_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2033$2604' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2033$2604_Y = \lm32_cpu.store_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2032$2603' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2032$2603_Y = \lm32_cpu.D_CYC_O'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2028$2602' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2028$2602_Y = \lm32_cpu.stall_wb_load'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1702$2516' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2675' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2673' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2673_Y = \lm32_cpu.valid_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2672' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2672_Y = \lm32_cpu.write_enable_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1514$2431' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1514$2431_Y = \lm32_cpu.write_enable_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1523$2445' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1523$2445_Y = \lm32_cpu.raw_x_1'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1523$2444' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1523$2444_Y = \lm32_cpu.read_enable_1_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1511$2422' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1511$2422_Y = \lm32_cpu.write_enable_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1522$2442' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1522$2442_Y = \lm32_cpu.raw_x_0'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1522$2441' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1522$2441_Y = \lm32_cpu.read_enable_0_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1521$2440' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$procmux$6891_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2140$2681' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2140$2681_Y = \lm32_cpu.valid_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2140$2680' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2140$2680_Y = \lm32_cpu.write_enable_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1513$2428' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1513$2428_Y = \lm32_cpu.write_enable_q_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1544$2462' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1544$2462_Y = \lm32_cpu.raw_w_0'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1542$2461' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1542$2461_Y = \lm32_cpu.raw_m_0'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1540$2460' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1540$2460_Y = \lm32_cpu.raw_x_0'.
Replacing $eq cell `$techmap\lm32_cpu.$procmux$3338_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7144_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1602$2474' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.adder.addsub.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:92$706' (1) in module `\top' with constant driver `$techmap\lm32_cpu.adder.addsub.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:92$706_Y = \lm32_cpu.adder.addsub.Add_Sub'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1516$2437' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1516$2437_Y = \lm32_cpu.write_enable_q_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1557$2466' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1557$2466_Y = \lm32_cpu.raw_w_1'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1555$2465' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1555$2465_Y = \lm32_cpu.raw_m_1'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1553$2464' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1553$2464_Y = \lm32_cpu.raw_x_1'.
Replacing $eq cell `$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:438$77' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$procmux$3382_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:594$124' (1) in module `\top' with constant driver `$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:594$124_Y = \lm32_cpu.decoder.select_high_immediate'.
Replacing $eq cell `$techmap\lm32_cpu.$procmux$3377_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.adder.addsub.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:93$708' (1) in module `\top' with constant driver `$techmap\lm32_cpu.adder.addsub.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:93$708_Y = \lm32_cpu.adder.addsub.Add_Sub'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1928$2567' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1928$2567_Y = \lm32_cpu.interrupt_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1792$2546' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1792$2546_Y = \lm32_cpu.divide_by_zero_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1923$2566' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1923$2566_Y = \lm32_cpu.divide_by_zero_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1786$2543' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1786$2543_Y = \lm32_cpu.valid_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1785$2542' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1785$2542_Y = \lm32_cpu.bus_error_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1913$2565' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1913$2565_Y = \lm32_cpu.instruction_bus_error_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1788$2545' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1788$2545_Y = \lm32_cpu.data_bus_error_seen'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1910$2564' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1910$2564_Y = \lm32_cpu.data_bus_error_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1747$2541' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1747$2541_Y = \lm32_cpu.branch_flushX_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2014$2599' in module `top' with inverter.
Replacing $ne cell `$techmap\lm32_cpu.mc_arithmetic.$ne$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:152$511' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2013$2598' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2013$2598_Y = \lm32_cpu.mc_stall_request_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2011$2597' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2011$2597_Y = \lm32_cpu.stall_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2703' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2092$2642' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2092$2641' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2092$2641_Y = \lm32_cpu.valid_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2093$2645' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2093$2645_Y = \lm32_cpu.q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2093$2644' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2093$2644_Y = \lm32_cpu.csr_write_enable_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2094$2647' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2094$2647_Y = \lm32_cpu.csr_write_enable_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2700' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2700_Y = \lm32_cpu.csr_write_enable_k_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2511$2699' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2511$2699_Y = \lm32_cpu.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2546$2706' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2546$2706_Y = \lm32_cpu.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2562$2711' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2562$2711_Y = \lm32_cpu.D_CYC_O'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2562$2710' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2562$2710_Y = \lm32_cpu.D_ERR_I'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2565$2714' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2565$2713' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2565$2713_Y = \lm32_cpu.exception_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2557$2709' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2557$2709_Y = \lm32_cpu.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2608$2718' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2608$2718_Y = \lm32_cpu.icache_restart_request'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:367$2863' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:367$2863_Y = \lm32_cpu.instruction_unit.icache.refill'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2606$2717' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2606$2717_Y = \lm32_cpu.icache_refill_request'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2114$2653' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2114$2653_Y = \lm32_cpu.q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2113$2652' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2113$2652_Y = \lm32_cpu.load_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2007$2594' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2007$2594_Y = \lm32_cpu.load_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2006$2593' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2006$2593_Y = \lm32_cpu.csr_write_enable_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1738$2539' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1738$2539_Y = \lm32_cpu.icache_refill_request'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1693$2508' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1693$2508_Y = \lm32_cpu.exception_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1689$2504' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1689$2504_Y = \lm32_cpu.branch_predict_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1688$2502' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1688$2502_Y = \lm32_cpu.branch_predict_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1687$2501' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1685$2499' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1684$2498' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1684$2498_Y = \lm32_cpu.condition_met_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1683$2496' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1683$2496_Y = \lm32_cpu.valid_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1682$2495' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1682$2495_Y = \lm32_cpu.branch_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1681$2494' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1733$2538' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1733$2538_Y = \lm32_cpu.branch_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1991$2590' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1989$2587' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1989$2587_Y = \lm32_cpu.D_CYC_O'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2661' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2659' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2658' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2658_Y = \lm32_cpu.valid_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2130$2667' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2130$2667_Y = \lm32_cpu.q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2130$2666' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2130$2666_Y = \lm32_cpu.store_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1988$2585' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1988$2585_Y = \lm32_cpu.store_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2120$2656' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2120$2656_Y = \lm32_cpu.q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2119$2655' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2119$2655_Y = \lm32_cpu.store_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1987$2583' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1987$2583_Y = \lm32_cpu.store_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2129$2664' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2129$2664_Y = \lm32_cpu.q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2129$2663' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2129$2663_Y = \lm32_cpu.load_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1986$2581' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1986$2581_Y = \lm32_cpu.load_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1985$2580' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1985$2580_Y = \lm32_cpu.load_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1982$2578' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1982$2578_Y = \lm32_cpu.bus_error_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1980$2576' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1980$2576_Y = \lm32_cpu.scall_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1979$2575' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1979$2575_Y = \lm32_cpu.eret_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1977$2572' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1976$2571' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1976$2571_Y = \lm32_cpu.interlock'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1975$2570' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1975$2570_Y = \lm32_cpu.stall_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1957$2569' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1957$2569_Y = \lm32_cpu.stall_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2646$2725' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1955$2568' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1955$2568_Y = \lm32_cpu.stall_f'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2640$2723' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1724$2536' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1724$2536_Y = \lm32_cpu.icache_refill_request'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1719$2534' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1719$2534_Y = \lm32_cpu.branch_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1717$2532' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1717$2532_Y = \lm32_cpu.branch_predict_taken_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1716$2531' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1716$2531_Y = \lm32_cpu.valid_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2640$2722' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2640$2722_Y = \lm32_cpu.kill_f'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2630$2721' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2630$2721_Y = \lm32_cpu.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2653$2730' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2651$2727' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2649$2726' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2649$2726_Y = \lm32_cpu.kill_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2660$2735' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2658$2734' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2658$2734_Y = \lm32_cpu.kill_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2656$2731' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2667$2740' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2665$2737' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2663$2736' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2663$2736_Y = \lm32_cpu.kill_m'.
Replacing $mux cell `$techmap\lm32_cpu.$procmux$3268' (0) in module `\top' with constant driver `$techmap\lm32_cpu.$procmux$3268_Y = $techmap\lm32_cpu.$procmux$3265_Y'.
Replacing $logic_not cell `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2671$2742' (1'0) in module `\top' with constant driver `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2671$2742_Y = 1'1'.
Replacing $and cell `$techmap\lm32_cpu.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2671$2743' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2671$2743_Y = \lm32_cpu.valid_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2670$2741' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2792$2746' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2680$2745' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2680$2745_Y = \lm32_cpu.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2859$2750' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2800$2747' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2800$2747_Y = \lm32_cpu.branch_reg_d'.
Replacing $eq cell `$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:598$126' (1) in module `\top' with constant driver `$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:598$126_Y = \lm32_cpu.decoder.select_call_immediate'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1879$2560' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1878$2558' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1873$2557' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1873$2557_Y = \lm32_cpu.interrupt_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1870$2555' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1870$2555_Y = \lm32_cpu.divide_by_zero_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1867$2553' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1867$2553_Y = \lm32_cpu.data_bus_error_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1866$2551' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1866$2551_Y = \lm32_cpu.instruction_bus_error_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1797$2548' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1797$2548_Y = \lm32_cpu.valid_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1795$2547' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1795$2547_Y = \lm32_cpu.scall_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1864$2550' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1864$2550_Y = \lm32_cpu.system_call_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2924$2753' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2924$2753_Y = \lm32_cpu.exception_x'.
Replacing $eq cell `$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:389$39' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2866$2751' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2866$2751_Y = \lm32_cpu.exception_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2936$2755' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2936$2755_Y = \lm32_cpu.exception_x'.
Replacing $eq cell `$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:548$100' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2903$2752' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2903$2752_Y = \lm32_cpu.exception_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2099$2649' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2099$2649_Y = \lm32_cpu.q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2099$2648' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2099$2648_Y = \lm32_cpu.eret_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2100$2651' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2100$2651_Y = \lm32_cpu.eret_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2951$2763' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2951$2763_Y = \lm32_cpu.data_bus_error_exception'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2944$2757' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2990$2771' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2990$2771_Y = \lm32_cpu.store_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2989$2770' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2989$2770_Y = \lm32_cpu.load_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2988$2768' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2987$2767' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2963$2764' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2963$2764_Y = \lm32_cpu.exception_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2761' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2759' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2759_Y = \lm32_cpu.q_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2758' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2758_Y = \lm32_cpu.exception_x'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2686' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2686_Y = \lm32_cpu.valid_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2684' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2683' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2683_Y = \lm32_cpu.write_enable_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3036$2778' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3036$2778_Y = \lm32_cpu.reg_write_enable_q_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2265$2695' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2265$2695_Y = \lm32_cpu.valid_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2264$2693' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2263$2691' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2261$2688' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2261$2688_Y = \lm32_cpu.csr_write_enable_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2135$2670' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2135$2670_Y = \lm32_cpu.valid_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2135$2669' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2135$2669_Y = \lm32_cpu.exception_w'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079$2624' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079$2623' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079$2623_Y = \lm32_cpu.valid_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2090$2639' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2090$2639_Y = \lm32_cpu.q_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2090$2638' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2090$2638_Y = \lm32_cpu.modulus_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2089$2636' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2089$2636_Y = \lm32_cpu.q_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2089$2635' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2089$2635_Y = \lm32_cpu.divide_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2086$2633' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2086$2633_Y = \lm32_cpu.q_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2086$2632' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2086$2632_Y = \lm32_cpu.multiply_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2083$2630' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2083$2630_Y = \lm32_cpu.q_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2083$2629' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2083$2629_Y = \lm32_cpu.shift_right_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2082$2627' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2082$2627_Y = \lm32_cpu.q_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2082$2626' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2082$2626_Y = \lm32_cpu.shift_left_d'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1699$2514' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1699$2514_Y = \lm32_cpu.branch_predict_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1698$2512' (1) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1698$2512_Y = \lm32_cpu.branch_predict_m'.
Replacing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1697$2511' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:286$138' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:283$137' (1) in module `\top' with constant driver `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:283$137_Y = \lm32_cpu.interrupt_unit.csr_write_enable'.
Replacing $eq cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:275$136' (1) in module `\top' with constant driver `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:275$136_Y = \lm32_cpu.interrupt_unit.eret_q_x'.
Replacing $eq cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:273$135' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:266$134' (1) in module `\top' with constant driver `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:266$134_Y = \lm32_cpu.interrupt_unit.exception'.
Replacing $eq cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:234$133' (1) in module `\top' with constant driver `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:234$133_Y = \lm32_cpu.interrupt_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:548$2809' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:548$2808' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:548$2808_Y = \lm32_cpu.instruction_unit.branch_mispredict_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:547$2807' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:547$2807_Y = \lm32_cpu.instruction_unit.branch_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:561$2814' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:561$2814_Y = \lm32_cpu.instruction_unit.icache_restart_request'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:557$2812' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:557$2812_Y = \lm32_cpu.instruction_unit.branch_predict_taken_d'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:557$2811' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:557$2811_Y = \lm32_cpu.instruction_unit.valid_d'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:672$2818' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:651$2817' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:651$2817_Y = \lm32_cpu.instruction_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:674$2819' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:676$2820' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:678$2821' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:705$2824' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:705$2824_Y = \lm32_cpu.instruction_unit.icache_refill_request'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:688$2823' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:688$2823_Y = \lm32_cpu.instruction_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:799$2833' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:799$2833_Y = \lm32_cpu.instruction_unit.i_err_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:808$2835' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:808$2834' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:808$2834_Y = \lm32_cpu.instruction_unit.icache_refill_request'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:851$2837' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:851$2837_Y = \lm32_cpu.instruction_unit.branch_taken_m'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:767$2827' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:767$2827_Y = \lm32_cpu.instruction_unit.i_cyc_o'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:745$2826' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:745$2826_Y = \lm32_cpu.instruction_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:633$2844' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:633$2844_Y = $techmap\lm32_cpu.instruction_unit.$reduce_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:633$2843_Y'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:783$2831' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:783$2831_Y = \lm32_cpu.instruction_unit.last_word'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:770$2829' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:770$2829_Y = \lm32_cpu.instruction_unit.i_err_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:770$2828' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:770$2828_Y = \lm32_cpu.instruction_unit.i_ack_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:632$2841' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:632$2841_Y = \lm32_cpu.instruction_unit.i_adr_o [3]'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:945$2840' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:936$2839' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:936$2839_Y = \lm32_cpu.instruction_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:525$2804' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:524$2803' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:524$2803_Y = \lm32_cpu.instruction_unit.valid_f'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7079_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:211$521' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:211$521_Y = \lm32_cpu.mc_arithmetic.shift_left_d'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:219$522' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:219$522_Y = \lm32_cpu.mc_arithmetic.shift_right_d'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:194$517' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:171$516' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:171$516_Y = \lm32_cpu.mc_arithmetic.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:247$527' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$525' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$525_Y = \lm32_cpu.mc_arithmetic.kill_x'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:268$533' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$531' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$531_Y = \lm32_cpu.mc_arithmetic.kill_x'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$530' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7033_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:233$523' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:254$529' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:277$535' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:277$535_Y = \lm32_cpu.mc_arithmetic.b [0]'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7010_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6986_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:161$513' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:161$513_Y = \lm32_cpu.mc_arithmetic.sign_extend_x'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6969_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:201$518' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:201$518_Y = \lm32_cpu.mc_arithmetic.divide_d'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:203$519' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:203$519_Y = \lm32_cpu.mc_arithmetic.modulus_d'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:207$520' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:207$520_Y = \lm32_cpu.mc_arithmetic.multiply_d'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$538' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$538_Y = \lm32_cpu.mc_arithmetic.kill_x'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$537' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$542' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$542_Y = \lm32_cpu.mc_arithmetic.kill_x'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$541' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$546' (1) in module `\top' with constant driver `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$546_Y = \lm32_cpu.mc_arithmetic.kill_x'.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$545' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$procmux$6908_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$procmux$6900_CMP0' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:784$2316' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:783$2314' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:783$2314_Y = \lm32_cpu.load_store_unit.wb_select_m'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:782$2313' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:782$2313_Y = \lm32_cpu.load_store_unit.load_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:760$2311' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:759$2310' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:759$2310_Y = \lm32_cpu.load_store_unit.store_q_m'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:709$2305' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:709$2305_Y = \lm32_cpu.load_store_unit.d_cyc_o'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2322' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2320' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2320_Y = \lm32_cpu.load_store_unit.wb_select_x'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2319' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2319_Y = \lm32_cpu.load_store_unit.load_q_x'.
Replacing $logic_and cell `$techmap\lm32_cpu.load_store_unit.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2321' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2321_Y = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2118$2654_Y'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:809$2325' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:809$2325_Y = \lm32_cpu.load_store_unit.exception_m'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:809$2324' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:809$2324_Y = \lm32_cpu.load_store_unit.kill_m'.
Replacing $logic_or cell `$techmap\lm32_cpu.load_store_unit.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:809$2326' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:809$2326_Y = \lm32_cpu.exception_m'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:685$2304' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:685$2304_Y = \lm32_cpu.load_store_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:712$2307' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:712$2307_Y = \lm32_cpu.load_store_unit.d_err_i'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:712$2306' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:712$2306_Y = \lm32_cpu.load_store_unit.d_ack_i'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:803$2318' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:838$2329' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:819$2328' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:819$2328_Y = \lm32_cpu.load_store_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:861$2331' (1) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:861$2331_Y = \lm32_cpu.load_store_unit.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:393$2865' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:393$2865_Y = \lm32_cpu.instruction_unit.icache.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:419$2868' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:427$2870' in module `top' with $logic_not.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2857' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2855' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2855_Y = \lm32_cpu.instruction_unit.icache.read_enable_f'.
Replacing $reduce_or cell `$techmap\lm32_cpu.instruction_unit.icache.$reduce_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2853' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$reduce_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2853_Y = $techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:294$2878_Y'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:453$2874' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:453$2874_Y = \lm32_cpu.instruction_unit.icache.miss'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:443$2873' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:443$2873_Y = \lm32_cpu.instruction_unit.icache.iflush'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:470$2876' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:470$2876_Y = \lm32_cpu.instruction_unit.icache.last_refill'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:468$2875' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:468$2875_Y = \lm32_cpu.instruction_unit.icache.refill_ready'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:402$2867' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:402$2867_Y = \lm32_cpu.instruction_unit.icache.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:441$2872' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:499$2885' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:499$2885_Y = \lm32_cpu.instruction_unit.icache.miss'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:497$2884' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:497$2884_Y = \lm32_cpu.instruction_unit.icache.iflush'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:506$2886' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:506$2886_Y = \lm32_cpu.instruction_unit.icache.refill_ready'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:488$2883' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:488$2883_Y = \lm32_cpu.instruction_unit.icache.rst_i'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:342$2881' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:342$2881_Y = \lm32_cpu.instruction_unit.icache.refill_ready'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:336$2849' in module `top' with inverter.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2895' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2895_Y = \lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.enable_write'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2894' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2894_Y = \lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.write_enable'.
Replacing $logic_and cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2896' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2896_Y = $techmap\lm32_cpu.instruction_unit.icache.$or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:273$2877_Y'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2906' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2906_Y = \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.enable_write'.
Replacing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2905' (1) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2905_Y = \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.write_enable'.
Replacing $logic_and cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2907' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:120$2907_Y = \lm32_cpu.instruction_unit.icache_refill_ready'.
Optimizing away select inverter for $mux cell `$procmux$5377' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5368' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5365' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5362' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5371' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5374' in module `top'.
Replacing $pos cell `$or$top.v:2557$1075' (1'0) in module `\top' with constant driver `$or$top.v:2557$1075_Y = 1'0'.
Replacing $and cell `$and$top.v:2524$1065' (const_and) in module `\top' with constant driver `$and$top.v:2524$1065_Y = 1'0'.
Replacing $and cell `$and$top.v:2525$1067' (const_and) in module `\top' with constant driver `$and$top.v:2525$1067_Y = 1'0'.
Optimizing away select inverter for $mux cell `$procmux$4948' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4966' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$5359' in module `top'.
Replacing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2562$2712' (const_and) in module `\top' with constant driver `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2562$2712_Y = 1'0'.
Replacing $mux cell `$techmap\lm32_cpu.$procmux$3316' (0) in module `\top' with constant driver `$techmap\lm32_cpu.$procmux$3316_Y = \lm32_cpu.data_bus_error_seen'.
Replacing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2565$2714' (1'0) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2565$2714_Y = 1'1'.
Replacing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2565$2715' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2565$2715_Y = \lm32_cpu.exception_m'.
Replacing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2659' (1'0) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2659_Y = 1'1'.
Replacing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2660' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2660_Y = \lm32_cpu.valid_m'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3298' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3286' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3289' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3274' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3280' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3262' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3265' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3256' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3250' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3244' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3238' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3232' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3226' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3220' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3214' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3208' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3202' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3196' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3190' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3184' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3178' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3172' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3166' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3160' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3154' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3148' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3142' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3136' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3130' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3124' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3118' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3112' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3106' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3100' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3088' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3082' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3076' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3070' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3064' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3058' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.decoder.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:549$101' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3049' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3043' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3031' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3025' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3019' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3013' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3007' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$3001' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$2995' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$2989' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$2977' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$2971' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$2962' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$2956' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.$procmux$2950' in module `top'.
Replacing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2684' (1'0) in module `\top' with constant driver `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2684_Y = 1'1'.
Replacing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2685' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2685_Y = \lm32_cpu.write_enable_w'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7132' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7114' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7096' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.$procmux$6683' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.$procmux$6677' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.$procmux$6671' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.$procmux$6665' in module `top'.
Replacing $mux cell `$techmap\lm32_cpu.instruction_unit.$procmux$6648' (0) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$procmux$6648_Y = \lm32_cpu.instruction_unit.bus_error_f'.
Replacing $logic_or cell `$techmap\lm32_cpu.instruction_unit.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:770$2830' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.instruction_unit.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:770$2830_Y = $and$top.v:2522$1061_Y'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.$procmux$6533' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.$procmux$6527' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7076' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7031' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7027' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7023' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7008' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7000' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6996' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6984' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6967' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6923' in module `top'.
Replacing $logic_or cell `$techmap\lm32_cpu.load_store_unit.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:712$2308' (and_or_buffer) in module `\top' with constant driver `$techmap\lm32_cpu.load_store_unit.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:712$2308_Y = $and$top.v:2523$1063_Y'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.load_store_unit.$procmux$6758' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.load_store_unit.$procmux$6746' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.load_store_unit.$procmux$6740' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.load_store_unit.$procmux$6734' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.load_store_unit.$procmux$6728' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.load_store_unit.$procmux$6722' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6490' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2923' in module `top'.
Optimizing away select inverter for $mux cell `$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2911' in module `top'.

21.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removing unused `$add' cell `$add$top.v:1261$817'.
  removing unused `$sub' cell `$sub$top.v:1265$819'.
  removing unused `$add' cell `$add$top.v:1291$828'.
  removing unused `$sub' cell `$sub$top.v:1295$830'.
  removing unused `$not' cell `$not$top.v:1362$843'.
  removing unused `$or' cell `$or$top.v:1490$847'.
  removing unused `$not' cell `$not$top.v:1905$870'.
  removing unused `$not' cell `$not$top.v:1907$871'.
  removing unused `$not' cell `$not$top.v:1909$872'.
  removing unused `$not' cell `$not$top.v:1931$891'.
  removing unused `$and' cell `$and$top.v:2210$921'.
  removing unused `$and' cell `$and$top.v:2210$922'.
  removing unused `$or' cell `$or$top.v:2210$923'.
  removing unused `$and' cell `$and$top.v:2276$950'.
  removing unused `$and' cell `$and$top.v:2276$951'.
  removing unused `$or' cell `$or$top.v:2276$952'.
  removing unused `$and' cell `$and$top.v:2342$979'.
  removing unused `$and' cell `$and$top.v:2342$980'.
  removing unused `$or' cell `$or$top.v:2342$981'.
  removing unused `$and' cell `$and$top.v:2408$1008'.
  removing unused `$and' cell `$and$top.v:2408$1009'.
  removing unused `$or' cell `$or$top.v:2408$1010'.
  removing unused `$and' cell `$and$top.v:2474$1037'.
  removing unused `$and' cell `$and$top.v:2474$1038'.
  removing unused `$or' cell `$or$top.v:2474$1039'.
  removing unused `$or' cell `$or$top.v:2511$1056'.
  removing unused `$or' cell `$or$top.v:2511$1057'.
  removing unused `$or' cell `$or$top.v:2511$1058'.
  removing unused `$or' cell `$or$top.v:2511$1059'.
  removing unused `$not' cell `$eq$top.v:2524$1064'.
  removing unused `$and' cell `$and$top.v:2584$1105'.
  removing unused `$eq' cell `$eq$top.v:2584$1106'.
  removing unused `$and' cell `$and$top.v:2584$1107'.
  removing unused `$and' cell `$and$top.v:2586$1108'.
  removing unused `$eq' cell `$eq$top.v:2586$1109'.
  removing unused `$and' cell `$and$top.v:2586$1110'.
  removing unused `$and' cell `$and$top.v:2588$1111'.
  removing unused `$eq' cell `$eq$top.v:2588$1112'.
  removing unused `$and' cell `$and$top.v:2588$1113'.
  removing unused `$and' cell `$and$top.v:2590$1114'.
  removing unused `$eq' cell `$eq$top.v:2590$1115'.
  removing unused `$and' cell `$and$top.v:2590$1116'.
  removing unused `$and' cell `$and$top.v:2610$1120'.
  removing unused `$logic_not' cell `$eq$top.v:2610$1121'.
  removing unused `$and' cell `$and$top.v:2610$1122'.
  removing unused `$and' cell `$and$top.v:2612$1123'.
  removing unused `$eq' cell `$eq$top.v:2612$1124'.
  removing unused `$and' cell `$and$top.v:2612$1125'.
  removing unused `$and' cell `$and$top.v:2614$1126'.
  removing unused `$eq' cell `$eq$top.v:2614$1127'.
  removing unused `$and' cell `$and$top.v:2614$1128'.
  removing unused `$and' cell `$and$top.v:2616$1129'.
  removing unused `$eq' cell `$eq$top.v:2616$1130'.
  removing unused `$and' cell `$and$top.v:2616$1131'.
  removing unused `$and' cell `$and$top.v:2618$1132'.
  removing unused `$eq' cell `$eq$top.v:2618$1133'.
  removing unused `$and' cell `$and$top.v:2618$1134'.
  removing unused `$and' cell `$and$top.v:2620$1135'.
  removing unused `$eq' cell `$eq$top.v:2620$1136'.
  removing unused `$and' cell `$and$top.v:2620$1137'.
  removing unused `$and' cell `$and$top.v:2622$1138'.
  removing unused `$eq' cell `$eq$top.v:2622$1139'.
  removing unused `$and' cell `$and$top.v:2622$1140'.
  removing unused `$and' cell `$and$top.v:2624$1141'.
  removing unused `$eq' cell `$eq$top.v:2624$1142'.
  removing unused `$and' cell `$and$top.v:2624$1143'.
  removing unused `$and' cell `$and$top.v:2626$1144'.
  removing unused `$eq' cell `$eq$top.v:2626$1145'.
  removing unused `$and' cell `$and$top.v:2626$1146'.
  removing unused `$and' cell `$and$top.v:2628$1147'.
  removing unused `$eq' cell `$eq$top.v:2628$1148'.
  removing unused `$and' cell `$and$top.v:2628$1149'.
  removing unused `$and' cell `$and$top.v:2630$1150'.
  removing unused `$eq' cell `$eq$top.v:2630$1151'.
  removing unused `$and' cell `$and$top.v:2630$1152'.
  removing unused `$and' cell `$and$top.v:2632$1153'.
  removing unused `$eq' cell `$eq$top.v:2632$1154'.
  removing unused `$and' cell `$and$top.v:2632$1155'.
  removing unused `$and' cell `$and$top.v:2634$1156'.
  removing unused `$eq' cell `$eq$top.v:2634$1157'.
  removing unused `$and' cell `$and$top.v:2634$1158'.
  removing unused `$and' cell `$and$top.v:2636$1159'.
  removing unused `$eq' cell `$eq$top.v:2636$1160'.
  removing unused `$and' cell `$and$top.v:2636$1161'.
  removing unused `$and' cell `$and$top.v:2638$1162'.
  removing unused `$eq' cell `$eq$top.v:2638$1163'.
  removing unused `$and' cell `$and$top.v:2638$1164'.
  removing unused `$and' cell `$and$top.v:2640$1165'.
  removing unused `$eq' cell `$eq$top.v:2640$1166'.
  removing unused `$and' cell `$and$top.v:2640$1167'.
  removing unused `$and' cell `$and$top.v:2642$1168'.
  removing unused `$eq' cell `$eq$top.v:2642$1169'.
  removing unused `$and' cell `$and$top.v:2642$1170'.
  removing unused `$and' cell `$and$top.v:2644$1171'.
  removing unused `$eq' cell `$eq$top.v:2644$1172'.
  removing unused `$and' cell `$and$top.v:2644$1173'.
  removing unused `$and' cell `$and$top.v:2646$1174'.
  removing unused `$eq' cell `$eq$top.v:2646$1175'.
  removing unused `$and' cell `$and$top.v:2646$1176'.
  removing unused `$and' cell `$and$top.v:2648$1177'.
  removing unused `$eq' cell `$eq$top.v:2648$1178'.
  removing unused `$and' cell `$and$top.v:2648$1179'.
  removing unused `$and' cell `$and$top.v:2650$1180'.
  removing unused `$eq' cell `$eq$top.v:2650$1181'.
  removing unused `$and' cell `$and$top.v:2650$1182'.
  removing unused `$and' cell `$and$top.v:2652$1183'.
  removing unused `$eq' cell `$eq$top.v:2652$1184'.
  removing unused `$and' cell `$and$top.v:2652$1185'.
  removing unused `$and' cell `$and$top.v:2654$1186'.
  removing unused `$eq' cell `$eq$top.v:2654$1187'.
  removing unused `$and' cell `$and$top.v:2654$1188'.
  removing unused `$and' cell `$and$top.v:2656$1189'.
  removing unused `$eq' cell `$eq$top.v:2656$1190'.
  removing unused `$and' cell `$and$top.v:2656$1191'.
  removing unused `$and' cell `$and$top.v:2658$1192'.
  removing unused `$eq' cell `$eq$top.v:2658$1193'.
  removing unused `$and' cell `$and$top.v:2658$1194'.
  removing unused `$and' cell `$and$top.v:2660$1195'.
  removing unused `$eq' cell `$eq$top.v:2660$1196'.
  removing unused `$and' cell `$and$top.v:2660$1197'.
  removing unused `$and' cell `$and$top.v:2662$1198'.
  removing unused `$eq' cell `$eq$top.v:2662$1199'.
  removing unused `$and' cell `$and$top.v:2662$1200'.
  removing unused `$and' cell `$and$top.v:2664$1201'.
  removing unused `$eq' cell `$eq$top.v:2664$1202'.
  removing unused `$and' cell `$and$top.v:2664$1203'.
  removing unused `$and' cell `$and$top.v:2666$1204'.
  removing unused `$eq' cell `$eq$top.v:2666$1205'.
  removing unused `$and' cell `$and$top.v:2666$1206'.
  removing unused `$and' cell `$and$top.v:2668$1207'.
  removing unused `$eq' cell `$eq$top.v:2668$1208'.
  removing unused `$and' cell `$and$top.v:2668$1209'.
  removing unused `$and' cell `$and$top.v:2670$1210'.
  removing unused `$eq' cell `$eq$top.v:2670$1211'.
  removing unused `$and' cell `$and$top.v:2670$1212'.
  removing unused `$and' cell `$and$top.v:2672$1213'.
  removing unused `$eq' cell `$eq$top.v:2672$1214'.
  removing unused `$and' cell `$and$top.v:2672$1215'.
  removing unused `$and' cell `$and$top.v:2674$1216'.
  removing unused `$eq' cell `$eq$top.v:2674$1217'.
  removing unused `$and' cell `$and$top.v:2674$1218'.
  removing unused `$and' cell `$and$top.v:2676$1219'.
  removing unused `$eq' cell `$eq$top.v:2676$1220'.
  removing unused `$and' cell `$and$top.v:2676$1221'.
  removing unused `$and' cell `$and$top.v:2678$1222'.
  removing unused `$eq' cell `$eq$top.v:2678$1223'.
  removing unused `$and' cell `$and$top.v:2678$1224'.
  removing unused `$and' cell `$and$top.v:2680$1225'.
  removing unused `$eq' cell `$eq$top.v:2680$1226'.
  removing unused `$and' cell `$and$top.v:2680$1227'.
  removing unused `$and' cell `$and$top.v:2721$1232'.
  removing unused `$eq' cell `$eq$top.v:2721$1233'.
  removing unused `$and' cell `$and$top.v:2721$1234'.
  removing unused `$and' cell `$and$top.v:2751$1269'.
  removing unused `$eq' cell `$eq$top.v:2751$1270'.
  removing unused `$and' cell `$and$top.v:2751$1271'.
  removing unused `$and' cell `$and$top.v:2753$1272'.
  removing unused `$eq' cell `$eq$top.v:2753$1273'.
  removing unused `$and' cell `$and$top.v:2753$1274'.
  removing unused `$and' cell `$and$top.v:2755$1275'.
  removing unused `$eq' cell `$eq$top.v:2755$1276'.
  removing unused `$and' cell `$and$top.v:2755$1277'.
  removing unused `$and' cell `$and$top.v:2757$1278'.
  removing unused `$eq' cell `$eq$top.v:2757$1279'.
  removing unused `$and' cell `$and$top.v:2757$1280'.
  removing unused `$and' cell `$and$top.v:2759$1281'.
  removing unused `$eq' cell `$eq$top.v:2759$1282'.
  removing unused `$and' cell `$and$top.v:2759$1283'.
  removing unused `$and' cell `$and$top.v:2784$1294'.
  removing unused `$eq' cell `$eq$top.v:2784$1295'.
  removing unused `$and' cell `$and$top.v:2784$1296'.
  removing unused `$and' cell `$and$top.v:2786$1297'.
  removing unused `$eq' cell `$eq$top.v:2786$1298'.
  removing unused `$and' cell `$and$top.v:2786$1299'.
  removing unused `$and' cell `$and$top.v:2788$1300'.
  removing unused `$eq' cell `$eq$top.v:2788$1301'.
  removing unused `$and' cell `$and$top.v:2788$1302'.
  removing unused `$and' cell `$and$top.v:2813$1326'.
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  removing unused `$not' cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:233$523'.
  removing unused `$not' cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:194$517'.
  removing unused `$dff' cell `$techmap\lm32_cpu.load_store_unit.$procdff$7783'.
  removing unused `$dff' cell `$techmap\lm32_cpu.load_store_unit.$procdff$7782'.
  removing unused `$mux' cell `$techmap\lm32_cpu.load_store_unit.$procmux$6791'.
  removing unused `$mux' cell `$techmap\lm32_cpu.load_store_unit.$procmux$6788'.
  removing unused `$mux' cell `$techmap\lm32_cpu.load_store_unit.$procmux$6785'.
  removing unused `$mux' cell `$techmap\lm32_cpu.load_store_unit.$procmux$6782'.
  removing unused `$mux' cell `$techmap\lm32_cpu.load_store_unit.$procmux$6779'.
  removing unused `$mux' cell `$techmap\lm32_cpu.load_store_unit.$procmux$6776'.
  removing unused `$mux' cell `$techmap\lm32_cpu.load_store_unit.$procmux$6774'.
  removing unused `$not' cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:838$2329'.
  removing unused `$not' cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:803$2318'.
  removing unused `$not' cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:441$2872'.
  removing unused `$not' cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:336$2849'.
  removing unused non-port wire \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.enable_read.
  removing unused non-port wire \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.enable_write.
  removing unused non-port wire \lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.enable_read.
  removing unused non-port wire \lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.enable_write.
  removing unused non-port wire \lm32_cpu.instruction_unit.icache.enable.
  removing unused non-port wire \lm32_cpu.instruction_unit.icache.refill_way_select.
  removing unused non-port wire \lm32_cpu.load_store_unit.kill_m.
  removing unused non-port wire \lm32_cpu.load_store_unit.d_err_i.
  removing unused non-port wire \lm32_cpu.load_store_unit.d_rty_i.
  removing unused non-port wire \lm32_cpu.load_store_unit.d_cti_o.
  removing unused non-port wire \lm32_cpu.load_store_unit.d_lock_o.
  removing unused non-port wire \lm32_cpu.load_store_unit.d_bte_o.
  removing unused non-port wire \lm32_cpu.load_store_unit.wb_select_x.
  removing unused non-port wire \lm32_cpu.logic_op.logic_idx.
  removing unused non-port wire \lm32_cpu.decoder.x_result_sel_logic.
  removing unused non-port wire \lm32_cpu.decoder.op_user.
  removing unused non-port wire \lm32_cpu.decoder.shift.
  removing unused non-port wire \lm32_cpu.instruction_unit.i_err_i.
  removing unused non-port wire \lm32_cpu.instruction_unit.pc_w.
  removing unused non-port wire \lm32_cpu.instruction_unit.i_dat_o.
  removing unused non-port wire \lm32_cpu.instruction_unit.i_sel_o.
  removing unused non-port wire \lm32_cpu.instruction_unit.i_we_o.
  removing unused non-port wire \lm32_cpu.instruction_unit.i_cti_o.
  removing unused non-port wire \lm32_cpu.instruction_unit.i_lock_o.
  removing unused non-port wire \lm32_cpu.instruction_unit.i_bte_o.
  removing unused non-port wire \lm32_cpu.instruction_unit.first_cycle_type.
  removing unused non-port wire \lm32_cpu.instruction_unit.next_cycle_type.
  removing unused non-port wire \lm32_cpu.interrupt_unit.ip_csr_read_data.
  removing unused non-port wire \lm32_cpu.I_ERR_I.
  removing unused non-port wire \lm32_cpu.I_RTY_I.
  removing unused non-port wire \lm32_cpu.D_ERR_I.
  removing unused non-port wire \lm32_cpu.D_RTY_I.
  removing unused non-port wire \lm32_cpu.I_DAT_O.
  removing unused non-port wire \lm32_cpu.I_SEL_O.
  removing unused non-port wire \lm32_cpu.I_WE_O.
  removing unused non-port wire \lm32_cpu.I_CTI_O.
  removing unused non-port wire \lm32_cpu.I_LOCK_O.
  removing unused non-port wire \lm32_cpu.I_BTE_O.
  removing unused non-port wire \lm32_cpu.D_CTI_O.
  removing unused non-port wire \lm32_cpu.D_LOCK_O.
  removing unused non-port wire \lm32_cpu.D_BTE_O.
  removing unused non-port wire \lm32_cpu.x_result_sel_logic_d.
  removing unused non-port wire \lm32_cpu.x_result_sel_logic_x.
  removing unused non-port wire \lm32_cpu.eret_m.
  removing unused non-port wire \lm32_cpu.multiplier_result_w.
  removing unused non-port wire \lm32_cpu.cfg.
  removing unused non-port wire \lm32_cpu.cfg2.
  removing unused non-port wire \lm32_cpu.pc_w.
  removing unused non-port wire \lm32_cpu.kill_m.
  removing unused non-port wire \lm32_cpu.kill_w.
  removing unused non-port wire \memadr_10.
  removing unused non-port wire \memadr_8.
  removing unused non-port wire \memadr_6.
  removing unused non-port wire \memadr_4.
  removing unused non-port wire \memadr_2.
  removing unused non-port wire \memdat_2.
  removing unused non-port wire \memdat.
  removing unused non-port wire \array_muxed.
  removing unused non-port wire \rhs_array_muxed12.
  removing unused non-port wire \rhs_array_muxed11.
  removing unused non-port wire \rhs_array_muxed2.
  removing unused non-port wire \slice_proxy0.
  removing unused non-port wire \csrbank6_ep_2_in_ibuf_empty_re.
  removing unused non-port wire \csrbank6_ep_2_in_last_tok_re.
  removing unused non-port wire \csrbank6_ep_2_out_obuf_empty_re.
  removing unused non-port wire \csrbank6_ep_2_out_last_tok_re.
  removing unused non-port wire \csrbank6_ep_1_in_ibuf_empty_re.
  removing unused non-port wire \csrbank6_ep_1_in_last_tok_re.
  removing unused non-port wire \csrbank6_ep_0_in_ibuf_empty_re.
  removing unused non-port wire \csrbank6_ep_0_in_last_tok_re.
  removing unused non-port wire \csrbank6_ep_0_out_obuf_empty_re.
  removing unused non-port wire \csrbank6_ep_0_out_last_tok_re.
  removing unused non-port wire \csrbank4_rxempty_re.
  removing unused non-port wire \csrbank4_txfull_re.
  removing unused non-port wire \csrbank3_value0_re.
  removing unused non-port wire \csrbank3_value1_re.
  removing unused non-port wire \csrbank3_value2_re.
  removing unused non-port wire \csrbank3_value3_re.
  removing unused non-port wire \csrbank2_miso_re.
  removing unused non-port wire \csrbank1_platform_target0_w.
  removing unused non-port wire \csrbank1_platform_target0_re.
  removing unused non-port wire \csrbank1_platform_target1_w.
  removing unused non-port wire \csrbank1_platform_target1_re.
  removing unused non-port wire \csrbank1_platform_target2_w.
  removing unused non-port wire \csrbank1_platform_target2_re.
  removing unused non-port wire \csrbank1_platform_target3_w.
  removing unused non-port wire \csrbank1_platform_target3_re.
  removing unused non-port wire \csrbank1_platform_target4_w.
  removing unused non-port wire \csrbank1_platform_target4_re.
  removing unused non-port wire \csrbank1_platform_target5_w.
  removing unused non-port wire \csrbank1_platform_target5_re.
  removing unused non-port wire \csrbank1_platform_target6_w.
  removing unused non-port wire \csrbank1_platform_target6_re.
  removing unused non-port wire \csrbank1_platform_target7_w.
  removing unused non-port wire \csrbank1_platform_target7_re.
  removing unused non-port wire \csrbank1_platform_platform0_w.
  removing unused non-port wire \csrbank1_platform_platform0_re.
  removing unused non-port wire \csrbank1_platform_platform1_w.
  removing unused non-port wire \csrbank1_platform_platform1_re.
  removing unused non-port wire \csrbank1_platform_platform2_w.
  removing unused non-port wire \csrbank1_platform_platform2_re.
  removing unused non-port wire \csrbank1_platform_platform3_w.
  removing unused non-port wire \csrbank1_platform_platform3_re.
  removing unused non-port wire \csrbank1_platform_platform4_w.
  removing unused non-port wire \csrbank1_platform_platform4_re.
  removing unused non-port wire \csrbank1_platform_platform5_w.
  removing unused non-port wire \csrbank1_platform_platform5_re.
  removing unused non-port wire \csrbank1_platform_platform6_w.
  removing unused non-port wire \csrbank1_platform_platform6_re.
  removing unused non-port wire \csrbank1_platform_platform7_w.
  removing unused non-port wire \csrbank1_platform_platform7_re.
  removing unused non-port wire \csrbank1_git_commit0_w.
  removing unused non-port wire \csrbank1_git_commit0_re.
  removing unused non-port wire \csrbank1_git_commit1_w.
  removing unused non-port wire \csrbank1_git_commit1_re.
  removing unused non-port wire \csrbank1_git_commit2_w.
  removing unused non-port wire \csrbank1_git_commit2_re.
  removing unused non-port wire \csrbank1_git_commit3_w.
  removing unused non-port wire \csrbank1_git_commit3_re.
  removing unused non-port wire \csrbank1_git_commit4_w.
  removing unused non-port wire \csrbank1_git_commit4_re.
  removing unused non-port wire \csrbank1_git_commit5_w.
  removing unused non-port wire \csrbank1_git_commit5_re.
  removing unused non-port wire \csrbank1_git_commit6_w.
  removing unused non-port wire \csrbank1_git_commit6_re.
  removing unused non-port wire \csrbank1_git_commit7_w.
  removing unused non-port wire \csrbank1_git_commit7_re.
  removing unused non-port wire \csrbank1_git_commit8_w.
  removing unused non-port wire \csrbank1_git_commit8_re.
  removing unused non-port wire \csrbank1_git_commit9_w.
  removing unused non-port wire \csrbank1_git_commit9_re.
  removing unused non-port wire \csrbank1_git_commit10_w.
  removing unused non-port wire \csrbank1_git_commit10_re.
  removing unused non-port wire \csrbank1_git_commit11_w.
  removing unused non-port wire \csrbank1_git_commit11_re.
  removing unused non-port wire \csrbank1_git_commit12_w.
  removing unused non-port wire \csrbank1_git_commit12_re.
  removing unused non-port wire \csrbank1_git_commit13_w.
  removing unused non-port wire \csrbank1_git_commit13_re.
  removing unused non-port wire \csrbank1_git_commit14_w.
  removing unused non-port wire \csrbank1_git_commit14_re.
  removing unused non-port wire \csrbank1_git_commit15_w.
  removing unused non-port wire \csrbank1_git_commit15_re.
  removing unused non-port wire \csrbank1_git_commit16_w.
  removing unused non-port wire \csrbank1_git_commit16_re.
  removing unused non-port wire \csrbank1_git_commit17_w.
  removing unused non-port wire \csrbank1_git_commit17_re.
  removing unused non-port wire \csrbank1_git_commit18_w.
  removing unused non-port wire \csrbank1_git_commit18_re.
  removing unused non-port wire \csrbank1_git_commit19_w.
  removing unused non-port wire \csrbank1_git_commit19_re.
  removing unused non-port wire \csrbank0_bus_errors0_re.
  removing unused non-port wire \csrbank0_bus_errors1_re.
  removing unused non-port wire \csrbank0_bus_errors2_re.
  removing unused non-port wire \csrbank0_bus_errors3_re.
  removing unused non-port wire \shared_err.
  removing unused non-port wire \shared_bte.
  removing unused non-port wire \shared_cti.
  removing unused non-port wire \usb_irq.
  removing unused non-port wire \usb_endpointin2_we.
  removing unused non-port wire \usb_endpointin2_writable.
  removing unused non-port wire \usb_endpointin2_din.
  removing unused non-port wire \usb_endpointin2_ibuf_head_w.
  removing unused non-port wire \usb_endpointin2_wrport_dat_r.
  removing unused non-port wire \usb_endpointin2_dtb_re.
  removing unused non-port wire \usb_endpointin2_reset.
  removing unused non-port wire \usb_endpointin2_respond_dat_w.
  removing unused non-port wire \usb_endpointin2_respond_we.
  removing unused non-port wire \usb_endpointin2_respond_re.
  removing unused non-port wire \usb_endpointin2_eventmanager2_re.
  removing unused non-port wire \usb_endpointin2_eventmanager2_status_w.
  removing unused non-port wire \usb_endpointin2_eventmanager2_status_re.
  removing unused non-port wire \usb_endpointin2_packet_status.
  removing unused non-port wire \usb_endpointin2_error_trigger.
  removing unused non-port wire \usb_endpointin2_error_status.
  removing unused non-port wire \usb_endpointin2_irq.
  removing unused non-port wire \usb_endpointout1_ibuf_re.
  removing unused non-port wire \usb_endpointout1_ibuf_readable.
  removing unused non-port wire \usb_endpointout1_ibuf_dout.
  removing unused non-port wire \usb_endpointout1_outbuf_wrport_dat_r.
  removing unused non-port wire \usb_endpointout1_dtb_re.
  removing unused non-port wire \usb_endpointout1_reset.
  removing unused non-port wire \usb_endpointout1_respond_dat_w.
  removing unused non-port wire \usb_endpointout1_respond_we.
  removing unused non-port wire \usb_endpointout1_respond_re.
  removing unused non-port wire \usb_endpointout1_eventmanager1_re.
  removing unused non-port wire \usb_endpointout1_eventmanager1_status_w.
  removing unused non-port wire \usb_endpointout1_eventmanager1_status_re.
  removing unused non-port wire \usb_endpointout1_packet_status.
  removing unused non-port wire \usb_endpointout1_error_trigger.
  removing unused non-port wire \usb_endpointout1_error_status.
  removing unused non-port wire \usb_endpointout1_irq.
  removing unused non-port wire \usb_endpointin1_we.
  removing unused non-port wire \usb_endpointin1_writable.
  removing unused non-port wire \usb_endpointin1_din.
  removing unused non-port wire \usb_endpointin1_ibuf_head_w.
  removing unused non-port wire \usb_endpointin1_wrport_dat_r.
  removing unused non-port wire \usb_endpointin1_dtb_re.
  removing unused non-port wire \usb_endpointin1_reset.
  removing unused non-port wire \usb_endpointin1_respond_dat_w.
  removing unused non-port wire \usb_endpointin1_respond_we.
  removing unused non-port wire \usb_endpointin1_respond_re.
  removing unused non-port wire \usb_endpointin1_eventmanager1_re.
  removing unused non-port wire \usb_endpointin1_eventmanager1_status_w.
  removing unused non-port wire \usb_endpointin1_eventmanager1_status_re.
  removing unused non-port wire \usb_endpointin1_packet_status.
  removing unused non-port wire \usb_endpointin1_error_trigger.
  removing unused non-port wire \usb_endpointin1_error_status.
  removing unused non-port wire \usb_endpointin1_irq.
  removing unused non-port wire \usb_oep_storage.
  removing unused non-port wire \usb_oep_status.
  removing unused non-port wire \usb_oep_trigger.
  removing unused non-port wire \usb_oep_response.
  removing unused non-port wire \usb_oep_we.
  removing unused non-port wire \usb_oep_writable.
  removing unused non-port wire \usb_oep_din.
  removing unused non-port wire \usb_oep_re.
  removing unused non-port wire \usb_oep_readable.
  removing unused non-port wire \usb_oep_dout.
  removing unused non-port wire \usb_endpointin0_we.
  removing unused non-port wire \usb_endpointin0_writable.
  removing unused non-port wire \usb_endpointin0_din.
  removing unused non-port wire \usb_endpointin0_ibuf_head_w.
  removing unused non-port wire \usb_endpointin0_wrport_dat_r.
  removing unused non-port wire \usb_endpointin0_dtb_re.
  removing unused non-port wire \usb_endpointin0_respond_dat_w.
  removing unused non-port wire \usb_endpointin0_respond_re.
  removing unused non-port wire \usb_endpointin0_eventmanager0_re.
  removing unused non-port wire \usb_endpointin0_eventmanager0_status_w.
  removing unused non-port wire \usb_endpointin0_eventmanager0_status_re.
  removing unused non-port wire \usb_endpointin0_packet_status.
  removing unused non-port wire \usb_endpointin0_error_trigger.
  removing unused non-port wire \usb_endpointin0_error_status.
  removing unused non-port wire \usb_endpointin0_irq.
  removing unused non-port wire \usb_endpointout0_ibuf_re.
  removing unused non-port wire \usb_endpointout0_ibuf_readable.
  removing unused non-port wire \usb_endpointout0_ibuf_dout.
  removing unused non-port wire \usb_endpointout0_outbuf_wrport_dat_r.
  removing unused non-port wire \usb_endpointout0_dtb_re.
  removing unused non-port wire \usb_endpointout0_respond_dat_w.
  removing unused non-port wire \usb_endpointout0_respond_re.
  removing unused non-port wire \usb_endpointout0_eventmanager0_re.
  removing unused non-port wire \usb_endpointout0_eventmanager0_status_w.
  removing unused non-port wire \usb_endpointout0_eventmanager0_status_re.
  removing unused non-port wire \usb_endpointout0_packet_status.
  removing unused non-port wire \usb_endpointout0_error_trigger.
  removing unused non-port wire \usb_endpointout0_error_status.
  removing unused non-port wire \usb_endpointout0_irq.
  removing unused non-port wire \usb_data_recv_ready.
  removing unused non-port wire \usb_transfer_end.
  removing unused non-port wire \usb_transfer_abort.
  removing unused non-port wire \usb_transfer_start.
  removing unused non-port wire \usb_reset.
  removing unused non-port wire \usb_tx_crc16_shifter_o_empty.
  removing unused non-port wire \usb_tx_data_shifter_o_empty.
  removing unused non-port wire \usb_tx_pid_shifter_o_empty.
  removing unused non-port wire \usb_tx_sync_shifter_o_empty.
  removing unused non-port wire \usb_rx_o_addr.
  removing unused non-port wire \usb_rx_end_data.
  removing unused non-port wire \usb_rx_start_data.
  removing unused non-port wire \usb_rx_start_token.
  removing unused non-port wire \usb_rx_end_handshake.
  removing unused non-port wire \usb_rx_pkt_active1.
  removing unused non-port wire \usb_rx_o_pkt_active.
  removing unused non-port wire \usb_rx_pkt_active0.
  removing unused non-port wire \usb_rx_bitstuff_error.
  removing unused non-port wire \usb_rx_se0.
  removing unused non-port wire \usb_rx_data.
  removing unused non-port wire \usb_rx_valid.
  removing unused non-port wire \usb_rx_bitstuff_o_bitstuff_error.
  removing unused non-port wire \usb_rx_line_state_se11.
  removing unused non-port wire \usb_rx_line_state_se10.
  removing unused non-port wire \usb_pullup_re.
  removing unused non-port wire \usbsoc_spiflash_bitbang_en_re.
  removing unused non-port wire \usbsoc_spiflash_bitbang_re.
  removing unused non-port wire \usbsoc_spiflash_bus_err.
  removing unused non-port wire \usbsoc_spiflash_bus_bte.
  removing unused non-port wire \usbsoc_spiflash_bus_cti.
  removing unused non-port wire \usbsoc_target_status.
  removing unused non-port wire \usbsoc_platform_status.
  removing unused non-port wire \usbsoc_status.
  removing unused non-port wire \usbsoc_reset.
  removing unused non-port wire \usb_48_rst.
  removing unused non-port wire \usbsoc_usbsoc_timer0_eventmanager_re.
  removing unused non-port wire \usbsoc_usbsoc_timer0_eventmanager_status_re.
  removing unused non-port wire \usbsoc_usbsoc_timer0_update_value_w.
  removing unused non-port wire \usbsoc_usbsoc_timer0_en_re.
  removing unused non-port wire \usbsoc_usbsoc_timer0_reload_re.
  removing unused non-port wire \usbsoc_usbsoc_timer0_load_re.
  removing unused non-port wire \usbsoc_usbsoc_uart_reset.
  removing unused non-port wire \usbsoc_usbsoc_uart_rx_fifo_fifo_in_last.
  removing unused non-port wire \usbsoc_usbsoc_uart_rx_fifo_fifo_in_first.
  removing unused non-port wire \usbsoc_usbsoc_uart_rx_fifo_level1.
  removing unused non-port wire \usbsoc_usbsoc_uart_rx_fifo_wrport_dat_r.
  removing unused non-port wire \usbsoc_usbsoc_uart_rx_fifo_replace.
  removing unused non-port wire \usbsoc_usbsoc_uart_rx_fifo_sink_last.
  removing unused non-port wire \usbsoc_usbsoc_uart_rx_fifo_sink_first.
  removing unused non-port wire \usbsoc_usbsoc_uart_tx_fifo_fifo_in_last.
  removing unused non-port wire \usbsoc_usbsoc_uart_tx_fifo_fifo_in_first.
  removing unused non-port wire \usbsoc_usbsoc_uart_tx_fifo_level1.
  removing unused non-port wire \usbsoc_usbsoc_uart_tx_fifo_wrport_dat_r.
  removing unused non-port wire \usbsoc_usbsoc_uart_tx_fifo_replace.
  removing unused non-port wire \usbsoc_usbsoc_uart_tx_fifo_sink_last.
  removing unused non-port wire \usbsoc_usbsoc_uart_tx_fifo_sink_first.
  removing unused non-port wire \usbsoc_usbsoc_uart_eventmanager_re.
  removing unused non-port wire \usbsoc_usbsoc_uart_eventmanager_status_re.
  removing unused non-port wire \usbsoc_usbsoc_uart_phy_source_last.
  removing unused non-port wire \usbsoc_usbsoc_uart_phy_source_first.
  removing unused non-port wire \usbsoc_usbsoc_uart_phy_re.
  removing unused non-port wire \usbsoc_usbsoc_bus_wishbone_err.
  removing unused non-port wire \usbsoc_usbsoc_bus_wishbone_bte.
  removing unused non-port wire \usbsoc_usbsoc_bus_wishbone_cti.
  removing unused non-port wire \usbsoc_usbsoc_sram_bus_err.
  removing unused non-port wire \usbsoc_usbsoc_sram_bus_bte.
  removing unused non-port wire \usbsoc_usbsoc_sram_bus_cti.
  removing unused non-port wire \usbsoc_usbsoc_lm32_dbus_err.
  removing unused non-port wire \usbsoc_usbsoc_lm32_dbus_bte.
  removing unused non-port wire \usbsoc_usbsoc_lm32_dbus_cti.
  removing unused non-port wire \usbsoc_usbsoc_lm32_ibus_err.
  removing unused non-port wire \usbsoc_usbsoc_lm32_ibus_bte.
  removing unused non-port wire \usbsoc_usbsoc_lm32_ibus_cti.
  removing unused non-port wire \usbsoc_usbsoc_lm32_ibus_we.
  removing unused non-port wire \usbsoc_usbsoc_lm32_ibus_sel.
  removing unused non-port wire \usbsoc_usbsoc_lm32_ibus_dat_w.
  removing unused non-port wire \usbsoc_usbsoc_ctrl_re.
  removing unused non-port wire \usbsoc_usbsoc_ctrl_reset_reset_w.
  removed 3974 unused temporary wires.
Removed 475 unused cells and 3974 unused wires.

21.7.4. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.

21.7.5. Executing OPT pass (performing simple optimizations).

21.7.5.1. Executing OPT_EXPR pass (perform const folding).

21.7.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
  Cell `$and$top.v:1196$792' is identical to cell `$and$top.v:1195$789'.
    Redirecting output \Y: $and$top.v:1196$792_Y = $and$top.v:1195$789_Y
    Removing $and cell `$and$top.v:1196$792' from module `\top'.
  Cell `$and$top.v:1196$793' is identical to cell `$and$top.v:1195$790'.
    Redirecting output \Y: $and$top.v:1196$793_Y = $and$top.v:1195$790_Y
    Removing $and cell `$and$top.v:1196$793' from module `\top'.
  Cell `$and$top.v:1197$795' is identical to cell `$and$top.v:1195$789'.
    Redirecting output \Y: $and$top.v:1197$795_Y = $and$top.v:1195$789_Y
    Removing $and cell `$and$top.v:1197$795' from module `\top'.
  Cell `$and$top.v:1197$796' is identical to cell `$and$top.v:1195$790'.
    Redirecting output \Y: $and$top.v:1197$796_Y = $and$top.v:1195$790_Y
    Removing $and cell `$and$top.v:1197$796' from module `\top'.
  Cell `$and$top.v:1198$798' is identical to cell `$and$top.v:1195$789'.
    Redirecting output \Y: $and$top.v:1198$798_Y = $and$top.v:1195$789_Y
    Removing $and cell `$and$top.v:1198$798' from module `\top'.
  Cell `$and$top.v:1198$799' is identical to cell `$and$top.v:1195$790'.
    Redirecting output \Y: $and$top.v:1198$799_Y = $and$top.v:1195$790_Y
    Removing $and cell `$and$top.v:1198$799' from module `\top'.
  Cell `$and$top.v:2576$1093' is identical to cell `$and$top.v:2574$1090'.
    Redirecting output \Y: $and$top.v:2576$1093_Y = $and$top.v:2574$1090_Y
    Removing $and cell `$and$top.v:2576$1093' from module `\top'.
  Cell `$and$top.v:2578$1096' is identical to cell `$and$top.v:2574$1090'.
    Redirecting output \Y: $and$top.v:2578$1096_Y = $and$top.v:2574$1090_Y
    Removing $and cell `$and$top.v:2578$1096' from module `\top'.
  Cell `$and$top.v:2580$1099' is identical to cell `$and$top.v:2574$1090'.
    Redirecting output \Y: $and$top.v:2580$1099_Y = $and$top.v:2574$1090_Y
    Removing $and cell `$and$top.v:2580$1099' from module `\top'.
  Cell `$and$top.v:2582$1102' is identical to cell `$and$top.v:2574$1090'.
    Redirecting output \Y: $and$top.v:2582$1102_Y = $and$top.v:2574$1090_Y
    Removing $and cell `$and$top.v:2582$1102' from module `\top'.
  Cell `$and$top.v:2723$1235' is identical to cell `$and$top.v:2719$1229'.
    Redirecting output \Y: $and$top.v:2723$1235_Y = $and$top.v:2719$1229_Y
    Removing $and cell `$and$top.v:2723$1235' from module `\top'.
  Cell `$and$top.v:2733$1242' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2733$1242_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2733$1242' from module `\top'.
  Cell `$and$top.v:2735$1245' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2735$1245_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2735$1245' from module `\top'.
  Cell `$and$top.v:2737$1248' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2737$1248_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2737$1248' from module `\top'.
  Cell `$and$top.v:2739$1251' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2739$1251_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2739$1251' from module `\top'.
  Cell `$and$top.v:2741$1254' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2741$1254_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2741$1254' from module `\top'.
  Cell `$and$top.v:2743$1257' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2743$1257_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2743$1257' from module `\top'.
  Cell `$and$top.v:2745$1260' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2745$1260_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2745$1260' from module `\top'.
  Cell `$and$top.v:2747$1263' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2747$1263_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2747$1263' from module `\top'.
  Cell `$and$top.v:2749$1266' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2749$1266_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2749$1266' from module `\top'.
  Cell `$and$top.v:2761$1284' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2761$1284_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2761$1284' from module `\top'.
  Cell `$and$top.v:2763$1287' is identical to cell `$and$top.v:2731$1239'.
    Redirecting output \Y: $and$top.v:2763$1287_Y = $and$top.v:2731$1239_Y
    Removing $and cell `$and$top.v:2763$1287' from module `\top'.
  Cell `$and$top.v:2790$1303' is identical to cell `$and$top.v:2782$1291'.
    Redirecting output \Y: $and$top.v:2790$1303_Y = $and$top.v:2782$1291_Y
    Removing $and cell `$and$top.v:2790$1303' from module `\top'.
  Cell `$and$top.v:2792$1306' is identical to cell `$and$top.v:2782$1291'.
    Redirecting output \Y: $and$top.v:2792$1306_Y = $and$top.v:2782$1291_Y
    Removing $and cell `$and$top.v:2792$1306' from module `\top'.
  Cell `$and$top.v:2799$1313' is identical to cell `$and$top.v:2797$1310'.
    Redirecting output \Y: $and$top.v:2799$1313_Y = $and$top.v:2797$1310_Y
    Removing $and cell `$and$top.v:2799$1313' from module `\top'.
  Cell `$and$top.v:2801$1316' is identical to cell `$and$top.v:2797$1310'.
    Redirecting output \Y: $and$top.v:2801$1316_Y = $and$top.v:2797$1310_Y
    Removing $and cell `$and$top.v:2801$1316' from module `\top'.
  Cell `$and$top.v:2803$1319' is identical to cell `$and$top.v:2797$1310'.
    Redirecting output \Y: $and$top.v:2803$1319_Y = $and$top.v:2797$1310_Y
    Removing $and cell `$and$top.v:2803$1319' from module `\top'.
  Cell `$and$top.v:2815$1329' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2815$1329_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2815$1329' from module `\top'.
  Cell `$and$top.v:2817$1332' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2817$1332_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2817$1332' from module `\top'.
  Cell `$and$top.v:2821$1338' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2821$1338_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2821$1338' from module `\top'.
  Cell `$and$top.v:2823$1341' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2823$1341_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2823$1341' from module `\top'.
  Cell `$and$top.v:2825$1344' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2825$1344_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2825$1344' from module `\top'.
  Cell `$and$top.v:2831$1353' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2831$1353_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2831$1353' from module `\top'.
  Cell `$and$top.v:2833$1356' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2833$1356_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2833$1356' from module `\top'.
  Cell `$and$top.v:2837$1362' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2837$1362_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2837$1362' from module `\top'.
  Cell `$and$top.v:2839$1365' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2839$1365_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2839$1365' from module `\top'.
  Cell `$and$top.v:2841$1368' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2841$1368_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2841$1368' from module `\top'.
  Cell `$and$top.v:2847$1377' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2847$1377_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2847$1377' from module `\top'.
  Cell `$and$top.v:2849$1380' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2849$1380_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2849$1380' from module `\top'.
  Cell `$and$top.v:2853$1386' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2853$1386_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2853$1386' from module `\top'.
  Cell `$and$top.v:2855$1389' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2855$1389_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2855$1389' from module `\top'.
  Cell `$and$top.v:2857$1392' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2857$1392_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2857$1392' from module `\top'.
  Cell `$and$top.v:2863$1401' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2863$1401_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2863$1401' from module `\top'.
  Cell `$and$top.v:2865$1404' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2865$1404_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2865$1404' from module `\top'.
  Cell `$and$top.v:2869$1410' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2869$1410_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2869$1410' from module `\top'.
  Cell `$and$top.v:2871$1413' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2871$1413_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2871$1413' from module `\top'.
  Cell `$and$top.v:2873$1416' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2873$1416_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2873$1416' from module `\top'.
  Cell `$and$top.v:2879$1425' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2879$1425_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2879$1425' from module `\top'.
  Cell `$and$top.v:2881$1428' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2881$1428_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2881$1428' from module `\top'.
  Cell `$and$top.v:2885$1434' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2885$1434_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2885$1434' from module `\top'.
  Cell `$and$top.v:2887$1437' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2887$1437_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2887$1437' from module `\top'.
  Cell `$and$top.v:2889$1440' is identical to cell `$and$top.v:2811$1323'.
    Redirecting output \Y: $and$top.v:2889$1440_Y = $and$top.v:2811$1323_Y
    Removing $and cell `$and$top.v:2889$1440' from module `\top'.
  Cell `$and$top.v:3163$1473' is identical to cell `$and$top.v:1195$789'.
    Redirecting output \Y: $and$top.v:3163$1473_Y = $and$top.v:1195$789_Y
    Removing $and cell `$and$top.v:3163$1473' from module `\top'.
  Cell `$and$top.v:3271$1502' is identical to cell `$and$top.v:1271$821'.
    Redirecting output \Y: $and$top.v:3271$1502_Y = \usbsoc_usbsoc_uart_tx_fifo_wrport_we
    Removing $and cell `$and$top.v:3271$1502' from module `\top'.
  Cell `$and$top.v:3277$1507' is identical to cell `$and$top.v:1271$821'.
    Redirecting output \Y: $and$top.v:3277$1507_Y = \usbsoc_usbsoc_uart_tx_fifo_wrport_we
    Removing $and cell `$and$top.v:3277$1507' from module `\top'.
  Cell `$and$top.v:3293$1513' is identical to cell `$and$top.v:1301$832'.
    Redirecting output \Y: $and$top.v:3293$1513_Y = \usbsoc_usbsoc_uart_rx_fifo_wrport_we
    Removing $and cell `$and$top.v:3293$1513' from module `\top'.
  Cell `$and$top.v:3299$1518' is identical to cell `$and$top.v:1301$832'.
    Redirecting output \Y: $and$top.v:3299$1518_Y = \usbsoc_usbsoc_uart_rx_fifo_wrport_we
    Removing $and cell `$and$top.v:3299$1518' from module `\top'.
  Cell `$and$top.v:3382$1544' is identical to cell `$and$top.v:3358$1531'.
    Redirecting output \Y: $and$top.v:3382$1544_Y = $and$top.v:3358$1531_Y
    Removing $and cell `$and$top.v:3382$1544' from module `\top'.
  Cell `$and$top.v:3382$1546' is identical to cell `$and$top.v:3358$1533'.
    Redirecting output \Y: $and$top.v:3382$1546_Y = $and$top.v:3358$1533_Y
    Removing $and cell `$and$top.v:3382$1546' from module `\top'.
  Cell `$and$top.v:4363$1591' is identical to cell `$and$top.v:4359$1586'.
    Redirecting output \Y: $and$top.v:4363$1591_Y = $and$top.v:4359$1586_Y
    Removing $and cell `$and$top.v:4363$1591' from module `\top'.
  Cell `$and$top.v:4377$1600' is identical to cell `$and$top.v:4373$1595'.
    Redirecting output \Y: $and$top.v:4377$1600_Y = $and$top.v:4373$1595_Y
    Removing $and cell `$and$top.v:4377$1600' from module `\top'.
  Cell `$and$top.v:4391$1609' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4391$1609_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4391$1609' from module `\top'.
  Cell `$and$top.v:4401$1613' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4401$1613_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4401$1613' from module `\top'.
  Cell `$and$top.v:4408$1616' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4408$1616_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4408$1616' from module `\top'.
  Cell `$and$top.v:4415$1619' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4415$1619_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4415$1619' from module `\top'.
  Cell `$and$top.v:4422$1623' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4422$1623_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4422$1623' from module `\top'.
  Cell `$and$top.v:4429$1626' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4429$1626_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4429$1626' from module `\top'.
  Cell `$and$top.v:4436$1629' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4436$1629_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4436$1629' from module `\top'.
  Cell `$and$top.v:4443$1632' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4443$1632_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4443$1632' from module `\top'.
  Cell `$and$top.v:4450$1635' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4450$1635_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4450$1635' from module `\top'.
  Cell `$and$top.v:4457$1638' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4457$1638_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4457$1638' from module `\top'.
  Cell `$and$top.v:4464$1641' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4464$1641_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4464$1641' from module `\top'.
  Cell `$and$top.v:4471$1644' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4471$1644_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4471$1644' from module `\top'.
  Cell `$and$top.v:4478$1647' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4478$1647_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4478$1647' from module `\top'.
  Cell `$and$top.v:4485$1650' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4485$1650_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4485$1650' from module `\top'.
  Cell `$and$top.v:4492$1653' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4492$1653_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4492$1653' from module `\top'.
  Cell `$and$top.v:4499$1656' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4499$1656_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4499$1656' from module `\top'.
  Cell `$and$top.v:4506$1659' is identical to cell `$and$top.v:4387$1604'.
    Redirecting output \Y: $and$top.v:4506$1659_Y = $and$top.v:4387$1604_Y
    Removing $and cell `$and$top.v:4506$1659' from module `\top'.
  Cell `$and$top.v:4517$1668' is identical to cell `$and$top.v:4513$1663'.
    Redirecting output \Y: $and$top.v:4517$1668_Y = $and$top.v:4513$1663_Y
    Removing $and cell `$and$top.v:4517$1668' from module `\top'.
  Cell `$eq$top.v:2124$904' is identical to cell `$eq$top.v:2101$903'.
    Redirecting output \Y: $eq$top.v:2124$904_Y = $eq$top.v:2101$903_Y
    Removing $eq cell `$eq$top.v:2124$904' from module `\top'.
  Cell `$eq$top.v:2130$906' is identical to cell `$eq$top.v:1492$848'.
    Redirecting output \Y: $eq$top.v:2130$906_Y = \usb_fast_ep_dir
    Removing $eq cell `$eq$top.v:2130$906' from module `\top'.
  Cell `$eq$top.v:2165$910' is identical to cell `$eq$top.v:2144$908'.
    Redirecting output \Y: $eq$top.v:2165$910_Y = $eq$top.v:2144$908_Y
    Removing $eq cell `$eq$top.v:2165$910' from module `\top'.
  Cell `$eq$top.v:2797$1311' is identical to cell `$eq$top.v:2719$1230'.
    Redirecting output \Y: $eq$top.v:2797$1311_Y = $eq$top.v:2719$1230_Y
    Removing $logic_not cell `$eq$top.v:2797$1311' from module `\top'.
  Cell `$eq$top.v:2801$1317' is identical to cell `$eq$top.v:2723$1236'.
    Redirecting output \Y: $eq$top.v:2801$1317_Y = $eq$top.v:2723$1236_Y
    Removing $eq cell `$eq$top.v:2801$1317' from module `\top'.
  Cell `$ne$top.v:3148$1468' is identical to cell `$ne$top.v:1324$840'.
    Redirecting output \Y: $ne$top.v:3148$1468_Y = \sys_rst
    Removing $reduce_bool cell `$ne$top.v:3148$1468' from module `\top'.
  Cell `$not$top.v:1211$802' is identical to cell `$not$top.v:1205$801'.
    Redirecting output \Y: \usbsoc_usbsoc_uart_tx_status = \csrbank4_txfull_w
    Removing $not cell `$not$top.v:1211$802' from module `\top'.
  Cell `$not$top.v:1220$804' is identical to cell `$not$top.v:1217$803'.
    Redirecting output \Y: \usbsoc_usbsoc_uart_rx_status = \csrbank4_rxempty_w
    Removing $not cell `$not$top.v:1220$804' from module `\top'.
  Cell `$not$top.v:1290$825' is identical to cell `$not$top.v:1217$803'.
    Redirecting output \Y: $not$top.v:1290$825_Y = \csrbank4_rxempty_w
    Removing $not cell `$not$top.v:1290$825' from module `\top'.
  Cell `$not$top.v:2219$924' is identical to cell `$not$top.v:2187$914'.
    Redirecting output \Y: $not$top.v:2219$924_Y = \csrbank6_ep_0_out_obuf_empty_w
    Removing $not cell `$not$top.v:2219$924' from module `\top'.
  Cell `$not$top.v:2285$953' is identical to cell `$not$top.v:2253$943'.
    Redirecting output \Y: $not$top.v:2285$953_Y = \csrbank6_ep_0_in_ibuf_empty_w
    Removing $not cell `$not$top.v:2285$953' from module `\top'.
  Cell `$not$top.v:2351$982' is identical to cell `$not$top.v:2319$972'.
    Redirecting output \Y: $not$top.v:2351$982_Y = \csrbank6_ep_1_in_ibuf_empty_w
    Removing $not cell `$not$top.v:2351$982' from module `\top'.
  Cell `$not$top.v:2417$1011' is identical to cell `$not$top.v:2385$1001'.
    Redirecting output \Y: $not$top.v:2417$1011_Y = \csrbank6_ep_2_out_obuf_empty_w
    Removing $not cell `$not$top.v:2417$1011' from module `\top'.
  Cell `$not$top.v:2483$1040' is identical to cell `$not$top.v:2451$1030'.
    Redirecting output \Y: $not$top.v:2483$1040_Y = \csrbank6_ep_2_in_ibuf_empty_w
    Removing $not cell `$not$top.v:2483$1040' from module `\top'.
  Cell `$not$top.v:3454$1551' is identical to cell `$not$top.v:2187$914'.
    Redirecting output \Y: $not$top.v:3454$1551_Y = \csrbank6_ep_0_out_obuf_empty_w
    Removing $not cell `$not$top.v:3454$1551' from module `\top'.
  Cell `$not$top.v:3584$1565' is identical to cell `$not$top.v:2385$1001'.
    Redirecting output \Y: $not$top.v:3584$1565_Y = \csrbank6_ep_2_out_obuf_empty_w
    Removing $not cell `$not$top.v:3584$1565' from module `\top'.
  Cell `$not$top.v:4363$1592' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4363$1592_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4363$1592' from module `\top'.
  Cell `$not$top.v:4373$1596' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4373$1596_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4373$1596' from module `\top'.
  Cell `$not$top.v:4377$1601' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4377$1601_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4377$1601' from module `\top'.
  Cell `$not$top.v:4387$1605' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4387$1605_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4387$1605' from module `\top'.
  Cell `$not$top.v:4391$1610' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4391$1610_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4391$1610' from module `\top'.
  Cell `$not$top.v:4401$1614' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4401$1614_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4401$1614' from module `\top'.
  Cell `$not$top.v:4408$1617' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4408$1617_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4408$1617' from module `\top'.
  Cell `$not$top.v:4415$1620' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4415$1620_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4415$1620' from module `\top'.
  Cell `$not$top.v:4422$1624' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4422$1624_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4422$1624' from module `\top'.
  Cell `$not$top.v:4429$1627' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4429$1627_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4429$1627' from module `\top'.
  Cell `$not$top.v:4436$1630' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4436$1630_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4436$1630' from module `\top'.
  Cell `$not$top.v:4443$1633' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4443$1633_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4443$1633' from module `\top'.
  Cell `$not$top.v:4450$1636' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4450$1636_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4450$1636' from module `\top'.
  Cell `$not$top.v:4457$1639' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4457$1639_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4457$1639' from module `\top'.
  Cell `$not$top.v:4464$1642' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4464$1642_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4464$1642' from module `\top'.
  Cell `$not$top.v:4471$1645' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4471$1645_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4471$1645' from module `\top'.
  Cell `$not$top.v:4478$1648' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4478$1648_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4478$1648' from module `\top'.
  Cell `$not$top.v:4485$1651' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4485$1651_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4485$1651' from module `\top'.
  Cell `$not$top.v:4492$1654' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4492$1654_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4492$1654' from module `\top'.
  Cell `$not$top.v:4499$1657' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4499$1657_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4499$1657' from module `\top'.
  Cell `$not$top.v:4506$1660' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4506$1660_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4506$1660' from module `\top'.
  Cell `$not$top.v:4513$1664' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4513$1664_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4513$1664' from module `\top'.
  Cell `$not$top.v:4517$1669' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4517$1669_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4517$1669' from module `\top'.
  Cell `$not$top.v:4525$1672' is identical to cell `$not$top.v:4359$1587'.
    Redirecting output \Y: $not$top.v:4525$1672_Y = $not$top.v:4359$1587_Y
    Removing $not cell `$not$top.v:4525$1672' from module `\top'.
  Cell `$not$top.v:4548$1674' is identical to cell `$not$top.v:2253$943'.
    Redirecting output \Y: $not$top.v:4548$1674_Y = \csrbank6_ep_0_in_ibuf_empty_w
    Removing $not cell `$not$top.v:4548$1674' from module `\top'.
  Cell `$not$top.v:4554$1676' is identical to cell `$not$top.v:2319$972'.
    Redirecting output \Y: $not$top.v:4554$1676_Y = \csrbank6_ep_1_in_ibuf_empty_w
    Removing $not cell `$not$top.v:4554$1676' from module `\top'.
  Cell `$not$top.v:4562$1678' is identical to cell `$not$top.v:2451$1030'.
    Redirecting output \Y: $not$top.v:4562$1678_Y = \csrbank6_ep_2_in_ibuf_empty_w
    Removing $not cell `$not$top.v:4562$1678' from module `\top'.
  Cell `$or$top.v:1698$861' is identical to cell `$or$top.v:1689$860'.
    Redirecting output \Y: $or$top.v:1698$861_Y = $or$top.v:1689$860_Y
    Removing $or cell `$or$top.v:1698$861' from module `\top'.
  Cell `$or$top.v:1707$862' is identical to cell `$or$top.v:1689$860'.
    Redirecting output \Y: $or$top.v:1707$862_Y = $or$top.v:1689$860_Y
    Removing $or cell `$or$top.v:1707$862' from module `\top'.
  Cell `$or$top.v:1716$863' is identical to cell `$or$top.v:1689$860'.
    Redirecting output \Y: $or$top.v:1716$863_Y = $or$top.v:1689$860_Y
    Removing $or cell `$or$top.v:1716$863' from module `\top'.
  Cell `$or$top.v:1744$864' is identical to cell `$or$top.v:1689$860'.
    Redirecting output \Y: $or$top.v:1744$864_Y = $or$top.v:1689$860_Y
    Removing $or cell `$or$top.v:1744$864' from module `\top'.
  Cell `$or$top.v:3454$1552' is identical to cell `$or$top.v:2219$925'.
    Redirecting output \Y: $or$top.v:3454$1552_Y = \usb_endpointout0_outbuf_asyncfifo0_re
    Removing $or cell `$or$top.v:3454$1552' from module `\top'.
  Cell `$or$top.v:3584$1566' is identical to cell `$or$top.v:2417$1012'.
    Redirecting output \Y: $or$top.v:3584$1566_Y = \usb_endpointout1_outbuf_asyncfifo1_re
    Removing $or cell `$or$top.v:3584$1566' from module `\top'.
  Cell `$or$top.v:4548$1675' is identical to cell `$or$top.v:2285$954'.
    Redirecting output \Y: $or$top.v:4548$1675_Y = \usb_endpointin0_asyncfifo0_re
    Removing $or cell `$or$top.v:4548$1675' from module `\top'.
  Cell `$or$top.v:4554$1677' is identical to cell `$or$top.v:2351$983'.
    Redirecting output \Y: $or$top.v:4554$1677_Y = \usb_endpointin1_asyncfifo1_re
    Removing $or cell `$or$top.v:4554$1677' from module `\top'.
  Cell `$or$top.v:4562$1679' is identical to cell `$or$top.v:2483$1041'.
    Redirecting output \Y: $or$top.v:4562$1679_Y = \usb_endpointin2_asyncfifo2_re
    Removing $or cell `$or$top.v:4562$1679' from module `\top'.
  Cell `$procmux$4163_CMP0' is identical to cell `$eq$top.v:2889$1441'.
    Redirecting output \Y: $procmux$4163_CMP = $eq$top.v:2889$1441_Y
    Removing $eq cell `$procmux$4163_CMP0' from module `\top'.
  Cell `$procmux$4164_CMP0' is identical to cell `$eq$top.v:2887$1438'.
    Redirecting output \Y: $procmux$4164_CMP = $eq$top.v:2887$1438_Y
    Removing $eq cell `$procmux$4164_CMP0' from module `\top'.
  Cell `$procmux$4165_CMP0' is identical to cell `$eq$top.v:2885$1435'.
    Redirecting output \Y: $procmux$4165_CMP = $eq$top.v:2885$1435_Y
    Removing $eq cell `$procmux$4165_CMP0' from module `\top'.
  Cell `$procmux$4167_CMP0' is identical to cell `$eq$top.v:2881$1429'.
    Redirecting output \Y: $procmux$4167_CMP = $eq$top.v:2881$1429_Y
    Removing $eq cell `$procmux$4167_CMP0' from module `\top'.
  Cell `$procmux$4168_CMP0' is identical to cell `$eq$top.v:2879$1426'.
    Redirecting output \Y: $procmux$4168_CMP = $eq$top.v:2879$1426_Y
    Removing $eq cell `$procmux$4168_CMP0' from module `\top'.
  Cell `$procmux$4202_CMP0' is identical to cell `$eq$top.v:2811$1324'.
    Redirecting output \Y: $procmux$4202_CMP = $eq$top.v:2811$1324_Y
    Removing $logic_not cell `$procmux$4202_CMP0' from module `\top'.
  Cell `$procmux$4213_CMP0' is identical to cell `$eq$top.v:2803$1320'.
    Redirecting output \Y: $procmux$4213_CMP = $eq$top.v:2803$1320_Y
    Removing $eq cell `$procmux$4213_CMP0' from module `\top'.
  Cell `$procmux$4214_CMP0' is identical to cell `$eq$top.v:2723$1236'.
    Redirecting output \Y: $procmux$4214_CMP = $eq$top.v:2723$1236_Y
    Removing $eq cell `$procmux$4214_CMP0' from module `\top'.
  Cell `$procmux$4216_CMP0' is identical to cell `$eq$top.v:2719$1230'.
    Redirecting output \Y: $procmux$4216_CMP = $eq$top.v:2719$1230_Y
    Removing $logic_not cell `$procmux$4216_CMP0' from module `\top'.
  Cell `$procmux$4225_CMP0' is identical to cell `$eq$top.v:2792$1307'.
    Redirecting output \Y: $procmux$4225_CMP = $eq$top.v:2792$1307_Y
    Removing $eq cell `$procmux$4225_CMP0' from module `\top'.
  Cell `$procmux$4226_CMP0' is identical to cell `$eq$top.v:2790$1304'.
    Redirecting output \Y: $procmux$4226_CMP = $eq$top.v:2790$1304_Y
    Removing $eq cell `$procmux$4226_CMP0' from module `\top'.
  Cell `$procmux$4230_CMP0' is identical to cell `$eq$top.v:2782$1292'.
    Redirecting output \Y: $procmux$4230_CMP = $eq$top.v:2782$1292_Y
    Removing $logic_not cell `$procmux$4230_CMP0' from module `\top'.
  Cell `$procmux$4248_CMP0' is identical to cell `$eq$top.v:2763$1288'.
    Redirecting output \Y: $procmux$4248_CMP = $eq$top.v:2763$1288_Y
    Removing $eq cell `$procmux$4248_CMP0' from module `\top'.
  Cell `$procmux$4264_CMP0' is identical to cell `$eq$top.v:2731$1240'.
    Redirecting output \Y: $procmux$4264_CMP = $eq$top.v:2731$1240_Y
    Removing $logic_not cell `$procmux$4264_CMP0' from module `\top'.
  Cell `$procmux$4279_CMP0' is identical to cell `$eq$top.v:2723$1236'.
    Redirecting output \Y: $procmux$4279_CMP = $eq$top.v:2723$1236_Y
    Removing $eq cell `$procmux$4279_CMP0' from module `\top'.
  Cell `$procmux$4280_CMP0' is identical to cell `$procmux$4215_CMP0'.
    Redirecting output \Y: $procmux$4280_CMP = $procmux$4215_CMP
    Removing $eq cell `$procmux$4280_CMP0' from module `\top'.
  Cell `$procmux$4281_CMP0' is identical to cell `$eq$top.v:2719$1230'.
    Redirecting output \Y: $procmux$4281_CMP = $eq$top.v:2719$1230_Y
    Removing $logic_not cell `$procmux$4281_CMP0' from module `\top'.
  Cell `$procmux$4290_CMP0' is identical to cell `$eq$top.v:2881$1429'.
    Redirecting output \Y: $procmux$4290_CMP = $eq$top.v:2881$1429_Y
    Removing $eq cell `$procmux$4290_CMP0' from module `\top'.
  Cell `$procmux$4291_CMP0' is identical to cell `$eq$top.v:2879$1426'.
    Redirecting output \Y: $procmux$4291_CMP = $eq$top.v:2879$1426_Y
    Removing $eq cell `$procmux$4291_CMP0' from module `\top'.
  Cell `$procmux$4292_CMP0' is identical to cell `$procmux$4169_CMP0'.
    Redirecting output \Y: $procmux$4292_CMP = $procmux$4169_CMP
    Removing $eq cell `$procmux$4292_CMP0' from module `\top'.
  Cell `$procmux$4293_CMP0' is identical to cell `$procmux$4170_CMP0'.
    Redirecting output \Y: $procmux$4293_CMP = $procmux$4170_CMP
    Removing $eq cell `$procmux$4293_CMP0' from module `\top'.
  Cell `$procmux$4294_CMP0' is identical to cell `$procmux$4171_CMP0'.
    Redirecting output \Y: $procmux$4294_CMP = $procmux$4171_CMP
    Removing $eq cell `$procmux$4294_CMP0' from module `\top'.
  Cell `$procmux$4295_CMP0' is identical to cell `$procmux$4172_CMP0'.
    Redirecting output \Y: $procmux$4295_CMP = $procmux$4172_CMP
    Removing $eq cell `$procmux$4295_CMP0' from module `\top'.
  Cell `$procmux$4296_CMP0' is identical to cell `$procmux$4173_CMP0'.
    Redirecting output \Y: $procmux$4296_CMP = $procmux$4173_CMP
    Removing $eq cell `$procmux$4296_CMP0' from module `\top'.
  Cell `$procmux$4297_CMP0' is identical to cell `$procmux$4174_CMP0'.
    Redirecting output \Y: $procmux$4297_CMP = $procmux$4174_CMP
    Removing $eq cell `$procmux$4297_CMP0' from module `\top'.
  Cell `$procmux$4298_CMP0' is identical to cell `$procmux$4175_CMP0'.
    Redirecting output \Y: $procmux$4298_CMP = $procmux$4175_CMP
    Removing $eq cell `$procmux$4298_CMP0' from module `\top'.
  Cell `$procmux$4299_CMP0' is identical to cell `$procmux$4176_CMP0'.
    Redirecting output \Y: $procmux$4299_CMP = $procmux$4176_CMP
    Removing $eq cell `$procmux$4299_CMP0' from module `\top'.
  Cell `$procmux$4300_CMP0' is identical to cell `$procmux$4177_CMP0'.
    Redirecting output \Y: $procmux$4300_CMP = $procmux$4177_CMP
    Removing $eq cell `$procmux$4300_CMP0' from module `\top'.
  Cell `$procmux$4301_CMP0' is identical to cell `$procmux$4178_CMP0'.
    Redirecting output \Y: $procmux$4301_CMP = $procmux$4178_CMP
    Removing $eq cell `$procmux$4301_CMP0' from module `\top'.
  Cell `$procmux$4302_CMP0' is identical to cell `$procmux$4179_CMP0'.
    Redirecting output \Y: $procmux$4302_CMP = $procmux$4179_CMP
    Removing $eq cell `$procmux$4302_CMP0' from module `\top'.
  Cell `$procmux$4303_CMP0' is identical to cell `$procmux$4180_CMP0'.
    Redirecting output \Y: $procmux$4303_CMP = $procmux$4180_CMP
    Removing $eq cell `$procmux$4303_CMP0' from module `\top'.
  Cell `$procmux$4304_CMP0' is identical to cell `$procmux$4181_CMP0'.
    Redirecting output \Y: $procmux$4304_CMP = $procmux$4181_CMP
    Removing $eq cell `$procmux$4304_CMP0' from module `\top'.
  Cell `$procmux$4305_CMP0' is identical to cell `$procmux$4182_CMP0'.
    Redirecting output \Y: $procmux$4305_CMP = $procmux$4182_CMP
    Removing $eq cell `$procmux$4305_CMP0' from module `\top'.
  Cell `$procmux$4306_CMP0' is identical to cell `$procmux$4183_CMP0'.
    Redirecting output \Y: $procmux$4306_CMP = $procmux$4183_CMP
    Removing $eq cell `$procmux$4306_CMP0' from module `\top'.
  Cell `$procmux$4307_CMP0' is identical to cell `$procmux$4184_CMP0'.
    Redirecting output \Y: $procmux$4307_CMP = $procmux$4184_CMP
    Removing $eq cell `$procmux$4307_CMP0' from module `\top'.
  Cell `$procmux$4308_CMP0' is identical to cell `$procmux$4185_CMP0'.
    Redirecting output \Y: $procmux$4308_CMP = $procmux$4185_CMP
    Removing $eq cell `$procmux$4308_CMP0' from module `\top'.
  Cell `$procmux$4309_CMP0' is identical to cell `$procmux$4186_CMP0'.
    Redirecting output \Y: $procmux$4309_CMP = $procmux$4186_CMP
    Removing $eq cell `$procmux$4309_CMP0' from module `\top'.
  Cell `$procmux$4310_CMP0' is identical to cell `$procmux$4187_CMP0'.
    Redirecting output \Y: $procmux$4310_CMP = $procmux$4187_CMP
    Removing $eq cell `$procmux$4310_CMP0' from module `\top'.
  Cell `$procmux$4311_CMP0' is identical to cell `$procmux$4188_CMP0'.
    Redirecting output \Y: $procmux$4311_CMP = $procmux$4188_CMP
    Removing $eq cell `$procmux$4311_CMP0' from module `\top'.
  Cell `$procmux$4312_CMP0' is identical to cell `$procmux$4189_CMP0'.
    Redirecting output \Y: $procmux$4312_CMP = $procmux$4189_CMP
    Removing $eq cell `$procmux$4312_CMP0' from module `\top'.
  Cell `$procmux$4313_CMP0' is identical to cell `$procmux$4190_CMP0'.
    Redirecting output \Y: $procmux$4313_CMP = $procmux$4190_CMP
    Removing $eq cell `$procmux$4313_CMP0' from module `\top'.
  Cell `$procmux$4314_CMP0' is identical to cell `$procmux$4191_CMP0'.
    Redirecting output \Y: $procmux$4314_CMP = $procmux$4191_CMP
    Removing $eq cell `$procmux$4314_CMP0' from module `\top'.
  Cell `$procmux$4315_CMP0' is identical to cell `$procmux$4192_CMP0'.
    Redirecting output \Y: $procmux$4315_CMP = $procmux$4192_CMP
    Removing $eq cell `$procmux$4315_CMP0' from module `\top'.
  Cell `$procmux$4316_CMP0' is identical to cell `$procmux$4193_CMP0'.
    Redirecting output \Y: $procmux$4316_CMP = $procmux$4193_CMP
    Removing $eq cell `$procmux$4316_CMP0' from module `\top'.
  Cell `$procmux$4317_CMP0' is identical to cell `$procmux$4194_CMP0'.
    Redirecting output \Y: $procmux$4317_CMP = $procmux$4194_CMP
    Removing $eq cell `$procmux$4317_CMP0' from module `\top'.
  Cell `$procmux$4318_CMP0' is identical to cell `$procmux$4195_CMP0'.
    Redirecting output \Y: $procmux$4318_CMP = $procmux$4195_CMP
    Removing $eq cell `$procmux$4318_CMP0' from module `\top'.
  Cell `$procmux$4319_CMP0' is identical to cell `$procmux$4196_CMP0'.
    Redirecting output \Y: $procmux$4319_CMP = $procmux$4196_CMP
    Removing $eq cell `$procmux$4319_CMP0' from module `\top'.
  Cell `$procmux$4320_CMP0' is identical to cell `$procmux$4197_CMP0'.
    Redirecting output \Y: $procmux$4320_CMP = $procmux$4197_CMP
    Removing $eq cell `$procmux$4320_CMP0' from module `\top'.
  Cell `$procmux$4321_CMP0' is identical to cell `$procmux$4198_CMP0'.
    Redirecting output \Y: $procmux$4321_CMP = $procmux$4198_CMP
    Removing $eq cell `$procmux$4321_CMP0' from module `\top'.
  Cell `$procmux$4322_CMP0' is identical to cell `$procmux$4199_CMP0'.
    Redirecting output \Y: $procmux$4322_CMP = $procmux$4199_CMP
    Removing $eq cell `$procmux$4322_CMP0' from module `\top'.
  Cell `$procmux$4323_CMP0' is identical to cell `$procmux$4200_CMP0'.
    Redirecting output \Y: $procmux$4323_CMP = $procmux$4200_CMP
    Removing $eq cell `$procmux$4323_CMP0' from module `\top'.
  Cell `$procmux$4324_CMP0' is identical to cell `$procmux$4201_CMP0'.
    Redirecting output \Y: $procmux$4324_CMP = $procmux$4201_CMP
    Removing $eq cell `$procmux$4324_CMP0' from module `\top'.
  Cell `$procmux$4325_CMP0' is identical to cell `$eq$top.v:2811$1324'.
    Redirecting output \Y: $procmux$4325_CMP = $eq$top.v:2811$1324_Y
    Removing $logic_not cell `$procmux$4325_CMP0' from module `\top'.
  Cell `$procmux$4348_CMP0' is identical to cell `$eq$top.v:2574$1091'.
    Redirecting output \Y: $procmux$4348_CMP = $eq$top.v:2574$1091_Y
    Removing $logic_not cell `$procmux$4348_CMP0' from module `\top'.
  Cell `$procmux$4539_CMP0' is identical to cell `$eq$top.v:2522$1060'.
    Redirecting output \Y: $procmux$4539_CMP = $eq$top.v:2522$1060_Y
    Removing $not cell `$procmux$4539_CMP0' from module `\top'.
  Cell `$procmux$4664_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$4664_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$4664_CMP0' from module `\top'.
  Cell `$procmux$4734_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$4734_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$4734_CMP0' from module `\top'.
  Cell `$procmux$4817_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$4817_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$4817_CMP0' from module `\top'.
  Cell `$procmux$4899_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$4899_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$4899_CMP0' from module `\top'.
  Cell `$procmux$5381_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$5381_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$5381_CMP0' from module `\top'.
  Cell `$procmux$5382_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$5382_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$5382_CMP0' from module `\top'.
  Cell `$procmux$5383_CMP0' is identical to cell `$procmux$4584_CMP0'.
    Redirecting output \Y: $procmux$5383_CMP = $procmux$4584_CMP
    Removing $eq cell `$procmux$5383_CMP0' from module `\top'.
  Cell `$procmux$5384_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$5384_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$5384_CMP0' from module `\top'.
  Cell `$procmux$5385_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$5385_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$5385_CMP0' from module `\top'.
  Cell `$procmux$5388_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$5388_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$5388_CMP0' from module `\top'.
  Cell `$procmux$5389_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$5389_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$5389_CMP0' from module `\top'.
  Cell `$procmux$5390_CMP0' is identical to cell `$procmux$4584_CMP0'.
    Redirecting output \Y: $procmux$5390_CMP = $procmux$4584_CMP
    Removing $eq cell `$procmux$5390_CMP0' from module `\top'.
  Cell `$procmux$5391_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$5391_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$5391_CMP0' from module `\top'.
  Cell `$procmux$5392_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$5392_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$5392_CMP0' from module `\top'.
  Cell `$procmux$5402_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$5402_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$5402_CMP0' from module `\top'.
  Cell `$procmux$5403_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$5403_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$5403_CMP0' from module `\top'.
  Cell `$procmux$5404_CMP0' is identical to cell `$procmux$4584_CMP0'.
    Redirecting output \Y: $procmux$5404_CMP = $procmux$4584_CMP
    Removing $eq cell `$procmux$5404_CMP0' from module `\top'.
  Cell `$procmux$5405_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$5405_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$5405_CMP0' from module `\top'.
  Cell `$procmux$5406_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$5406_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$5406_CMP0' from module `\top'.
  Cell `$procmux$5494_CMP0' is identical to cell `$eq$top.v:2072$898'.
    Redirecting output \Y: $procmux$5494_CMP = $eq$top.v:2072$898_Y
    Removing $eq cell `$procmux$5494_CMP0' from module `\top'.
  Cell `$procmux$5502_CMP0' is identical to cell `$eq$top.v:2071$894'.
    Redirecting output \Y: $procmux$5502_CMP = $eq$top.v:2071$894_Y
    Removing $eq cell `$procmux$5502_CMP0' from module `\top'.
  Cell `$procmux$5531_CMP0' is identical to cell `$eq$top.v:2071$894'.
    Redirecting output \Y: $procmux$5531_CMP = $eq$top.v:2071$894_Y
    Removing $eq cell `$procmux$5531_CMP0' from module `\top'.
  Cell `$procmux$5540_CMP0' is identical to cell `$procmux$5506_CMP0'.
    Redirecting output \Y: $procmux$5540_CMP = $procmux$5506_CMP
    Removing $eq cell `$procmux$5540_CMP0' from module `\top'.
  Cell `$procmux$5552_CMP0' is identical to cell `$eq$top.v:2072$898'.
    Redirecting output \Y: $procmux$5552_CMP = $eq$top.v:2072$898_Y
    Removing $eq cell `$procmux$5552_CMP0' from module `\top'.
  Cell `$procmux$5553_CMP0' is identical to cell `$procmux$5498_CMP0'.
    Redirecting output \Y: $procmux$5553_CMP = $procmux$5498_CMP
    Removing $eq cell `$procmux$5553_CMP0' from module `\top'.
  Cell `$procmux$5571_CMP0' is identical to cell `$procmux$5522_CMP0'.
    Redirecting output \Y: $procmux$5571_CMP = $procmux$5522_CMP
    Removing $eq cell `$procmux$5571_CMP0' from module `\top'.
  Cell `$procmux$5574_CMP0' is identical to cell `$eq$top.v:2072$898'.
    Redirecting output \Y: $procmux$5574_CMP = $eq$top.v:2072$898_Y
    Removing $eq cell `$procmux$5574_CMP0' from module `\top'.
  Cell `$procmux$5582_CMP0' is identical to cell `$procmux$5561_CMP0'.
    Redirecting output \Y: $procmux$5582_CMP = $procmux$5561_CMP
    Removing $eq cell `$procmux$5582_CMP0' from module `\top'.
  Cell `$procmux$5583_CMP0' is identical to cell `$procmux$5563_CMP0'.
    Redirecting output \Y: $procmux$5583_CMP = $procmux$5563_CMP
    Removing $eq cell `$procmux$5583_CMP0' from module `\top'.
  Cell `$procmux$5584_CMP0' is identical to cell `$procmux$5564_CMP0'.
    Redirecting output \Y: $procmux$5584_CMP = $procmux$5564_CMP
    Removing $logic_not cell `$procmux$5584_CMP0' from module `\top'.
  Cell `$procmux$5591_CMP0' is identical to cell `$procmux$5522_CMP0'.
    Redirecting output \Y: $procmux$5591_CMP = $procmux$5522_CMP
    Removing $eq cell `$procmux$5591_CMP0' from module `\top'.
  Cell `$procmux$5608_CMP0' is identical to cell `$procmux$5522_CMP0'.
    Redirecting output \Y: $procmux$5608_CMP = $procmux$5522_CMP
    Removing $eq cell `$procmux$5608_CMP0' from module `\top'.
  Cell `$procmux$5618_CMP0' is identical to cell `$procmux$5522_CMP0'.
    Redirecting output \Y: $procmux$5618_CMP = $procmux$5522_CMP
    Removing $eq cell `$procmux$5618_CMP0' from module `\top'.
  Cell `$procmux$5628_CMP0' is identical to cell `$procmux$5522_CMP0'.
    Redirecting output \Y: $procmux$5628_CMP = $procmux$5522_CMP
    Removing $eq cell `$procmux$5628_CMP0' from module `\top'.
  Cell `$procmux$5638_CMP0' is identical to cell `$procmux$5522_CMP0'.
    Redirecting output \Y: $procmux$5638_CMP = $procmux$5522_CMP
    Removing $eq cell `$procmux$5638_CMP0' from module `\top'.
  Cell `$procmux$5680_CMP0' is identical to cell `$procmux$5650_CMP0'.
    Redirecting output \Y: $procmux$5680_CMP = $procmux$5650_CMP
    Removing $eq cell `$procmux$5680_CMP0' from module `\top'.
  Cell `$procmux$5681_CMP0' is identical to cell `$procmux$5657_CMP0'.
    Redirecting output \Y: $procmux$5681_CMP = $procmux$5657_CMP
    Removing $eq cell `$procmux$5681_CMP0' from module `\top'.
  Cell `$procmux$5682_CMP0' is identical to cell `$procmux$5667_CMP0'.
    Redirecting output \Y: $procmux$5682_CMP = $procmux$5667_CMP
    Removing $eq cell `$procmux$5682_CMP0' from module `\top'.
  Cell `$procmux$5683_CMP0' is identical to cell `$procmux$5677_CMP0'.
    Redirecting output \Y: $procmux$5683_CMP = $procmux$5677_CMP
    Removing $eq cell `$procmux$5683_CMP0' from module `\top'.
  Cell `$procmux$5688_CMP0' is identical to cell `$procmux$5667_CMP0'.
    Redirecting output \Y: $procmux$5688_CMP = $procmux$5667_CMP
    Removing $eq cell `$procmux$5688_CMP0' from module `\top'.
  Cell `$procmux$5692_CMP0' is identical to cell `$procmux$5657_CMP0'.
    Redirecting output \Y: $procmux$5692_CMP = $procmux$5657_CMP
    Removing $eq cell `$procmux$5692_CMP0' from module `\top'.
  Cell `$procmux$5693_CMP0' is identical to cell `$procmux$5667_CMP0'.
    Redirecting output \Y: $procmux$5693_CMP = $procmux$5667_CMP
    Removing $eq cell `$procmux$5693_CMP0' from module `\top'.
  Cell `$procmux$5743_CMP0' is identical to cell `$procmux$5705_CMP0'.
    Redirecting output \Y: $procmux$5743_CMP = $procmux$5705_CMP
    Removing $eq cell `$procmux$5743_CMP0' from module `\top'.
  Cell `$procmux$5784_CMP0' is identical to cell `$procmux$5752_CMP0'.
    Redirecting output \Y: $procmux$5784_CMP = $procmux$5752_CMP
    Removing $eq cell `$procmux$5784_CMP0' from module `\top'.
  Cell `$procmux$5785_CMP0' is identical to cell `$procmux$5756_CMP0'.
    Redirecting output \Y: $procmux$5785_CMP = $procmux$5756_CMP
    Removing $eq cell `$procmux$5785_CMP0' from module `\top'.
  Cell `$procmux$5792_CMP0' is identical to cell `$procmux$5777_CMP0'.
    Redirecting output \Y: $procmux$5792_CMP = $procmux$5777_CMP
    Removing $eq cell `$procmux$5792_CMP0' from module `\top'.
  Cell `$procmux$5800_CMP0' is identical to cell `$procmux$5781_CMP0'.
    Redirecting output \Y: $procmux$5800_CMP = $procmux$5781_CMP
    Removing $eq cell `$procmux$5800_CMP0' from module `\top'.
  Cell `$procmux$5803_CMP0' is identical to cell `$procmux$5752_CMP0'.
    Redirecting output \Y: $procmux$5803_CMP = $procmux$5752_CMP
    Removing $eq cell `$procmux$5803_CMP0' from module `\top'.
  Cell `$procmux$5804_CMP0' is identical to cell `$procmux$5756_CMP0'.
    Redirecting output \Y: $procmux$5804_CMP = $procmux$5756_CMP
    Removing $eq cell `$procmux$5804_CMP0' from module `\top'.
  Cell `$procmux$5805_CMP0' is identical to cell `$procmux$5760_CMP0'.
    Redirecting output \Y: $procmux$5805_CMP = $procmux$5760_CMP
    Removing $eq cell `$procmux$5805_CMP0' from module `\top'.
  Cell `$procmux$5806_CMP0' is identical to cell `$procmux$5767_CMP0'.
    Redirecting output \Y: $procmux$5806_CMP = $procmux$5767_CMP
    Removing $eq cell `$procmux$5806_CMP0' from module `\top'.
  Cell `$procmux$5807_CMP0' is identical to cell `$procmux$5777_CMP0'.
    Redirecting output \Y: $procmux$5807_CMP = $procmux$5777_CMP
    Removing $eq cell `$procmux$5807_CMP0' from module `\top'.
  Cell `$procmux$5808_CMP0' is identical to cell `$procmux$5781_CMP0'.
    Redirecting output \Y: $procmux$5808_CMP = $procmux$5781_CMP
    Removing $eq cell `$procmux$5808_CMP0' from module `\top'.
  Cell `$procmux$5814_CMP0' is identical to cell `$procmux$5752_CMP0'.
    Redirecting output \Y: $procmux$5814_CMP = $procmux$5752_CMP
    Removing $eq cell `$procmux$5814_CMP0' from module `\top'.
  Cell `$procmux$5819_CMP0' is identical to cell `$procmux$5760_CMP0'.
    Redirecting output \Y: $procmux$5819_CMP = $procmux$5760_CMP
    Removing $eq cell `$procmux$5819_CMP0' from module `\top'.
  Cell `$procmux$5831_CMP0' is identical to cell `$procmux$5767_CMP0'.
    Redirecting output \Y: $procmux$5831_CMP = $procmux$5767_CMP
    Removing $eq cell `$procmux$5831_CMP0' from module `\top'.
  Cell `$procmux$5841_CMP0' is identical to cell `$procmux$5777_CMP0'.
    Redirecting output \Y: $procmux$5841_CMP = $procmux$5777_CMP
    Removing $eq cell `$procmux$5841_CMP0' from module `\top'.
  Cell `$procmux$5847_CMP0' is identical to cell `$procmux$5767_CMP0'.
    Redirecting output \Y: $procmux$5847_CMP = $procmux$5767_CMP
    Removing $eq cell `$procmux$5847_CMP0' from module `\top'.
  Cell `$procmux$5859_CMP0' is identical to cell `$procmux$5767_CMP0'.
    Redirecting output \Y: $procmux$5859_CMP = $procmux$5767_CMP
    Removing $eq cell `$procmux$5859_CMP0' from module `\top'.
  Cell `$procmux$5869_CMP0' is identical to cell `$procmux$5777_CMP0'.
    Redirecting output \Y: $procmux$5869_CMP = $procmux$5777_CMP
    Removing $eq cell `$procmux$5869_CMP0' from module `\top'.
  Cell `$procmux$5913_CMP0' is identical to cell `$procmux$5878_CMP0'.
    Redirecting output \Y: $procmux$5913_CMP = $procmux$5878_CMP
    Removing $eq cell `$procmux$5913_CMP0' from module `\top'.
  Cell `$procmux$5914_CMP0' is identical to cell `$procmux$5882_CMP0'.
    Redirecting output \Y: $procmux$5914_CMP = $procmux$5882_CMP
    Removing $eq cell `$procmux$5914_CMP0' from module `\top'.
  Cell `$procmux$5915_CMP0' is identical to cell `$procmux$5886_CMP0'.
    Redirecting output \Y: $procmux$5915_CMP = $procmux$5886_CMP
    Removing $eq cell `$procmux$5915_CMP0' from module `\top'.
  Cell `$procmux$5916_CMP0' is identical to cell `$procmux$5890_CMP0'.
    Redirecting output \Y: $procmux$5916_CMP = $procmux$5890_CMP
    Removing $eq cell `$procmux$5916_CMP0' from module `\top'.
  Cell `$procmux$5917_CMP0' is identical to cell `$procmux$5894_CMP0'.
    Redirecting output \Y: $procmux$5917_CMP = $procmux$5894_CMP
    Removing $eq cell `$procmux$5917_CMP0' from module `\top'.
  Cell `$procmux$5918_CMP0' is identical to cell `$procmux$5907_CMP0'.
    Redirecting output \Y: $procmux$5918_CMP = $procmux$5907_CMP
    Removing $eq cell `$procmux$5918_CMP0' from module `\top'.
  Cell `$procmux$5924_CMP0' is identical to cell `$procmux$5878_CMP0'.
    Redirecting output \Y: $procmux$5924_CMP = $procmux$5878_CMP
    Removing $eq cell `$procmux$5924_CMP0' from module `\top'.
  Cell `$procmux$5925_CMP0' is identical to cell `$procmux$5882_CMP0'.
    Redirecting output \Y: $procmux$5925_CMP = $procmux$5882_CMP
    Removing $eq cell `$procmux$5925_CMP0' from module `\top'.
  Cell `$procmux$5926_CMP0' is identical to cell `$procmux$5886_CMP0'.
    Redirecting output \Y: $procmux$5926_CMP = $procmux$5886_CMP
    Removing $eq cell `$procmux$5926_CMP0' from module `\top'.
  Cell `$procmux$5927_CMP0' is identical to cell `$procmux$5890_CMP0'.
    Redirecting output \Y: $procmux$5927_CMP = $procmux$5890_CMP
    Removing $eq cell `$procmux$5927_CMP0' from module `\top'.
  Cell `$procmux$5928_CMP0' is identical to cell `$procmux$5894_CMP0'.
    Redirecting output \Y: $procmux$5928_CMP = $procmux$5894_CMP
    Removing $eq cell `$procmux$5928_CMP0' from module `\top'.
  Cell `$procmux$5929_CMP0' is identical to cell `$procmux$5907_CMP0'.
    Redirecting output \Y: $procmux$5929_CMP = $procmux$5907_CMP
    Removing $eq cell `$procmux$5929_CMP0' from module `\top'.
  Cell `$procmux$5938_CMP0' is identical to cell `$procmux$5878_CMP0'.
    Redirecting output \Y: $procmux$5938_CMP = $procmux$5878_CMP
    Removing $eq cell `$procmux$5938_CMP0' from module `\top'.
  Cell `$procmux$5967_CMP0' is identical to cell `$procmux$5890_CMP0'.
    Redirecting output \Y: $procmux$5967_CMP = $procmux$5890_CMP
    Removing $eq cell `$procmux$5967_CMP0' from module `\top'.
  Cell `$procmux$6009_CMP0' is identical to cell `$procmux$5907_CMP0'.
    Redirecting output \Y: $procmux$6009_CMP = $procmux$5907_CMP
    Removing $eq cell `$procmux$6009_CMP0' from module `\top'.
  Cell `$procmux$6068_CMP0' is identical to cell `$procmux$6024_CMP0'.
    Redirecting output \Y: $procmux$6068_CMP = $procmux$6024_CMP
    Removing $eq cell `$procmux$6068_CMP0' from module `\top'.
  Cell `$procmux$6094_CMP0' is identical to cell `$procmux$6031_CMP0'.
    Redirecting output \Y: $procmux$6094_CMP = $procmux$6031_CMP
    Removing $eq cell `$procmux$6094_CMP0' from module `\top'.
  Cell `$procmux$6144_CMP0' is identical to cell `$procmux$6106_CMP0'.
    Redirecting output \Y: $procmux$6144_CMP = $procmux$6106_CMP
    Removing $eq cell `$procmux$6144_CMP0' from module `\top'.
  Cell `$procmux$6220_CMP0' is identical to cell `$procmux$6214_CMP0'.
    Redirecting output \Y: $procmux$6220_CMP = $procmux$6214_CMP
    Removing $eq cell `$procmux$6220_CMP0' from module `\top'.
  Cell `$procmux$6223_CMP0' is identical to cell `$procmux$6202_CMP0'.
    Redirecting output \Y: $procmux$6223_CMP = $procmux$6202_CMP
    Removing $eq cell `$procmux$6223_CMP0' from module `\top'.
  Cell `$procmux$6224_CMP0' is identical to cell `$procmux$6206_CMP0'.
    Redirecting output \Y: $procmux$6224_CMP = $procmux$6206_CMP
    Removing $eq cell `$procmux$6224_CMP0' from module `\top'.
  Cell `$procmux$6225_CMP0' is identical to cell `$procmux$6210_CMP0'.
    Redirecting output \Y: $procmux$6225_CMP = $procmux$6210_CMP
    Removing $eq cell `$procmux$6225_CMP0' from module `\top'.
  Cell `$procmux$6226_CMP0' is identical to cell `$procmux$6214_CMP0'.
    Redirecting output \Y: $procmux$6226_CMP = $procmux$6214_CMP
    Removing $eq cell `$procmux$6226_CMP0' from module `\top'.
  Cell `$procmux$6233_CMP0' is identical to cell `$procmux$6206_CMP0'.
    Redirecting output \Y: $procmux$6233_CMP = $procmux$6206_CMP
    Removing $eq cell `$procmux$6233_CMP0' from module `\top'.
  Cell `$procmux$6238_CMP0' is identical to cell `$procmux$6210_CMP0'.
    Redirecting output \Y: $procmux$6238_CMP = $procmux$6210_CMP
    Removing $eq cell `$procmux$6238_CMP0' from module `\top'.
  Cell `$procmux$6270_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$6270_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$6270_CMP0' from module `\top'.
  Cell `$procmux$6280_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$6280_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$6280_CMP0' from module `\top'.
  Cell `$procmux$6281_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$6281_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$6281_CMP0' from module `\top'.
  Cell `$procmux$6282_CMP0' is identical to cell `$procmux$4584_CMP0'.
    Redirecting output \Y: $procmux$6282_CMP = $procmux$4584_CMP
    Removing $eq cell `$procmux$6282_CMP0' from module `\top'.
  Cell `$procmux$6283_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$6283_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$6283_CMP0' from module `\top'.
  Cell `$procmux$6284_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$6284_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$6284_CMP0' from module `\top'.
  Cell `$procmux$6291_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$6291_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$6291_CMP0' from module `\top'.
  Cell `$procmux$6310_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$6310_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$6310_CMP0' from module `\top'.
  Cell `$procmux$6317_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$6317_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$6317_CMP0' from module `\top'.
  Cell `$procmux$6339_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$6339_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$6339_CMP0' from module `\top'.
  Cell `$procmux$6342_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$6342_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$6342_CMP0' from module `\top'.
  Cell `$procmux$6365_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$6365_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$6365_CMP0' from module `\top'.
  Cell `$procmux$6371_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$6371_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$6371_CMP0' from module `\top'.
  Cell `$procmux$6380_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$6380_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$6380_CMP0' from module `\top'.
  Cell `$procmux$6386_CMP0' is identical to cell `$procmux$4582_CMP0'.
    Redirecting output \Y: $procmux$6386_CMP = $procmux$4582_CMP
    Removing $eq cell `$procmux$6386_CMP0' from module `\top'.
  Cell `$procmux$6387_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$6387_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$6387_CMP0' from module `\top'.
  Cell `$procmux$6388_CMP0' is identical to cell `$procmux$4584_CMP0'.
    Redirecting output \Y: $procmux$6388_CMP = $procmux$4584_CMP
    Removing $eq cell `$procmux$6388_CMP0' from module `\top'.
  Cell `$procmux$6389_CMP0' is identical to cell `$procmux$4585_CMP0'.
    Redirecting output \Y: $procmux$6389_CMP = $procmux$4585_CMP
    Removing $eq cell `$procmux$6389_CMP0' from module `\top'.
  Cell `$procmux$6390_CMP0' is identical to cell `$procmux$4586_CMP0'.
    Redirecting output \Y: $procmux$6390_CMP = $procmux$4586_CMP
    Removing $logic_not cell `$procmux$6390_CMP0' from module `\top'.
  Cell `$procmux$6408_CMP0' is identical to cell `$procmux$4583_CMP0'.
    Redirecting output \Y: $procmux$6408_CMP = $procmux$4583_CMP
    Removing $eq cell `$procmux$6408_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1624$2484' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1622$2480'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1624$2484_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1622$2480_Y
    Removing $eq cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1624$2484' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1697$2511' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1687$2501'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1697$2511_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1687$2501_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1697$2511' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1702$2516' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1681$2494'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1702$2516_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1681$2494_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1702$2516' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1706$2521' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1687$2501'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1706$2521_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1687$2501_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1706$2521' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1991$2590' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1977$2572'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1991$2590_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1977$2572_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1991$2590' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079$2624' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1977$2572'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079$2624_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1977$2572_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2079$2624' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2092$2642' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2014$2599'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2092$2642_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2014$2599_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2092$2642' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2675' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2014$2599'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2675_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2014$2599_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2138$2675' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2264$2693' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1977$2572'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2264$2693_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1977$2572_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2264$2693' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2640$2723' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2263$2691'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2640$2723_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2263$2691_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2640$2723' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2761' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2703'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2761_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2703_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2946$2761' from module `\top'.
  Cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2987$2767' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1681$2494'.
    Redirecting output \Y: $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2987$2767_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1681$2494_Y
    Removing $not cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2987$2767' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1699$2513' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1689$2503'.
    Redirecting output \Y: $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1699$2513_Y = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1689$2503_Y
    Removing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1699$2513' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1699$2515' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1690$2505'.
    Redirecting output \Y: \lm32_cpu.branch_mispredict_taken_m = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1690$2505_Y
    Removing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1699$2515' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1705$2519' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1684$2497'.
    Redirecting output \Y: $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1705$2519_Y = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1684$2497_Y
    Removing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1705$2519' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1708$2523' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1689$2503'.
    Redirecting output \Y: $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1708$2523_Y = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1689$2503_Y
    Removing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1708$2523' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1709$2525' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1690$2505'.
    Redirecting output \Y: $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1709$2525_Y = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1690$2505_Y
    Removing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1709$2525' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2687' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2140$2682'.
    Redirecting output \Y: \lm32_cpu.reg_write_enable_q_w = \lm32_cpu.write_enable_q_w
    Removing $logic_and cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2142$2687' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1622$2479' is identical to cell `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1621$2478'.
    Redirecting output \Y: $techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1622$2479_Y = $techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1621$2478_Y
    Removing $logic_not cell `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1622$2479' from module `\top'.
  Cell `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1623$2482' is identical to cell `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1621$2478'.
    Redirecting output \Y: $techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1623$2482_Y = $techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1621$2478_Y
    Removing $logic_not cell `$techmap\lm32_cpu.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1623$2482' from module `\top'.
  Cell `$techmap\lm32_cpu.$procmux$3335_CMP0' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2701'.
    Redirecting output \Y: $techmap\lm32_cpu.$procmux$3335_CMP = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2701_Y
    Removing $eq cell `$techmap\lm32_cpu.$procmux$3335_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.decoder.$or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:541$93' is identical to cell `$techmap\lm32_cpu.decoder.$or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:538$91'.
    Redirecting output \Y: $techmap\lm32_cpu.decoder.$or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:541$93_Y = $techmap\lm32_cpu.decoder.$or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:538$91_Y
    Removing $or cell `$techmap\lm32_cpu.decoder.$or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:541$93' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:548$2809' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2661'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:548$2809_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2128$2661_Y
    Removing $not cell `$techmap\lm32_cpu.instruction_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:548$2809' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:557$2813' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1718$2533'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:557$2813_Y = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1718$2533_Y
    Removing $logic_and cell `$techmap\lm32_cpu.instruction_unit.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:557$2813' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2857' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2263$2691'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2857_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2263$2691_Y
    Removing $not cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2857' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:427$2870' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:419$2868'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:427$2870_Y = $techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:419$2868_Y
    Removing $logic_not cell `$techmap\lm32_cpu.instruction_unit.icache.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:427$2870' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2859' is identical to cell `$techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1718$2533'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2859_Y = $techmap\lm32_cpu.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1718$2533_Y
    Removing $logic_and cell `$techmap\lm32_cpu.instruction_unit.icache.$logic_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:365$2859' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6476_CMP0' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6476_CMP = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP
    Removing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6476_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6488_CMP0' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6447_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6488_CMP = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6447_CMP
    Removing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6488_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6492_CMP0' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6492_CMP = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP
    Removing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6492_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6504_CMP0' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6447_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6504_CMP = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6447_CMP
    Removing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6504_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6511_CMP0' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6511_CMP = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP
    Removing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6511_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6515_CMP0' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6462_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6515_CMP = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6462_CMP
    Removing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6515_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6519_CMP0' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6463_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6519_CMP = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6463_CMP
    Removing $eq cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6519_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:435$2871' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:421$2869'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:435$2871_Y = $techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:421$2869_Y
    Removing $sub cell `$techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:435$2871' from module `\top'.
  Cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:286$138' is identical to cell `$techmap\lm32_cpu.$procmux$3338_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:286$138_Y = $techmap\lm32_cpu.$procmux$3338_CMP [0]
    Removing $logic_not cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:286$138' from module `\top'.
  Cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:298$139' is identical to cell `$techmap\lm32_cpu.$procmux$3338_CMP1'.
    Redirecting output \Y: $techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:298$139_Y = $techmap\lm32_cpu.$procmux$3338_CMP [1]
    Removing $eq cell `$techmap\lm32_cpu.interrupt_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:298$139' from module `\top'.
  Cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7142_CMP0' is identical to cell `$techmap\lm32_cpu.$procmux$3338_CMP1'.
    Redirecting output \Y: $techmap\lm32_cpu.interrupt_unit.$procmux$7142_CMP = $techmap\lm32_cpu.$procmux$3338_CMP [1]
    Removing $eq cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7142_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7143_CMP0' is identical to cell `$techmap\lm32_cpu.$procmux$3338_CMP2'.
    Redirecting output \Y: $techmap\lm32_cpu.interrupt_unit.$procmux$7143_CMP = $techmap\lm32_cpu.$procmux$3338_CMP [2]
    Removing $eq cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7143_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7144_CMP0' is identical to cell `$techmap\lm32_cpu.$procmux$3338_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.interrupt_unit.$procmux$7144_CMP = $techmap\lm32_cpu.$procmux$3338_CMP [0]
    Removing $logic_not cell `$techmap\lm32_cpu.interrupt_unit.$procmux$7144_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:639$2301' is identical to cell `$techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:636$2298'.
    Redirecting output \Y: $techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:639$2301_Y = $techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:636$2298_Y
    Removing $and cell `$techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:639$2301' from module `\top'.
  Cell `$techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:640$2302' is identical to cell `$techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:638$2300'.
    Redirecting output \Y: $techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:640$2302_Y = $techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:638$2300_Y
    Removing $and cell `$techmap\lm32_cpu.load_store_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:640$2302' from module `\top'.
  Cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:760$2311' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1681$2494'.
    Redirecting output \Y: $techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:760$2311_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1681$2494_Y
    Removing $not cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:760$2311' from module `\top'.
  Cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2322' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2703'.
    Redirecting output \Y: $techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2322_Y = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2515$2703_Y
    Removing $not cell `$techmap\lm32_cpu.load_store_unit.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_load_store_unit.v:806$2322' from module `\top'.
  Cell `$techmap\lm32_cpu.load_store_unit.$procmux$6906_CMP0' is identical to cell `$techmap\lm32_cpu.load_store_unit.$procmux$6897_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.load_store_unit.$procmux$6906_CMP = $techmap\lm32_cpu.load_store_unit.$procmux$6897_CMP
    Removing $eq cell `$techmap\lm32_cpu.load_store_unit.$procmux$6906_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.load_store_unit.$procmux$6908_CMP0' is identical to cell `$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1602$2474'.
    Redirecting output \Y: $techmap\lm32_cpu.load_store_unit.$procmux$6908_CMP = $techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1602$2474_Y
    Removing $logic_not cell `$techmap\lm32_cpu.load_store_unit.$procmux$6908_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$530' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$530_Y = $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524_Y
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$530' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:268$533' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:247$527'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:268$533_Y = $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:247$527_Y
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:268$533' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$537' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$537_Y = $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524_Y
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$537' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$541' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$541_Y = $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524_Y
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$541' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$545' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$545_Y = $techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$524_Y
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$545' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$532' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$532_Y = $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526_Y
    Removing $logic_or cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:265$532' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$539' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$539_Y = $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526_Y
    Removing $logic_or cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:282$539' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$543' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$543_Y = $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526_Y
    Removing $logic_or cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:292$543' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$547' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$547_Y = $techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:244$526_Y
    Removing $logic_or cell `$techmap\lm32_cpu.mc_arithmetic.$logic_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:300$547' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6934_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6911_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6934_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6911_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6934_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6938_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6912_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6938_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6912_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6938_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6942_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6942_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6942_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6946_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6946_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6946_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6950_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6950_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6950_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6969_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6969_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6969_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6975_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6911_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6975_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6911_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6975_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6976_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6976_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6976_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6986_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6986_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6986_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6993_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6912_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6993_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6912_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6993_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6994_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6994_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6994_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6998_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6998_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6998_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7002_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7002_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7002_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7010_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7010_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7010_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7021_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7021_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7021_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7025_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7025_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7025_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7029_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7029_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7029_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7033_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7033_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7033_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7039_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6911_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7039_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6911_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7039_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7040_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6912_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7040_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6912_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7040_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7041_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7041_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7041_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7042_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7042_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7042_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7043_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7043_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7043_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7055_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7055_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7055_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7059_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7059_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP
    Removing $eq cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7059_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7079_CMP0' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP0'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7079_CMP = $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP
    Removing $logic_not cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7079_CMP0' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:271$534' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:271$534_Y = $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528_Y
    Removing $sub cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:271$534' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:284$540' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:284$540_Y = $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528_Y
    Removing $sub cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:284$540' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:294$544' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:294$544_Y = $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528_Y
    Removing $sub cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:294$544' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:302$548' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:302$548_Y = $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528_Y
    Removing $sub cell `$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:302$548' from module `\top'.
  Cell `$and$top.v:4363$1593' is identical to cell `$and$top.v:4359$1588'.
    Redirecting output \Y: $and$top.v:4363$1593_Y = $and$top.v:4359$1588_Y
    Removing $and cell `$and$top.v:4363$1593' from module `\top'.
  Cell `$and$top.v:4377$1602' is identical to cell `$and$top.v:4373$1597'.
    Redirecting output \Y: $and$top.v:4377$1602_Y = $and$top.v:4373$1597_Y
    Removing $and cell `$and$top.v:4377$1602' from module `\top'.
  Cell `$and$top.v:4391$1611' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4391$1611_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4391$1611' from module `\top'.
  Cell `$and$top.v:4401$1615' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4401$1615_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4401$1615' from module `\top'.
  Cell `$and$top.v:4408$1618' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4408$1618_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4408$1618' from module `\top'.
  Cell `$and$top.v:4415$1621' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4415$1621_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4415$1621' from module `\top'.
  Cell `$and$top.v:4422$1625' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4422$1625_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4422$1625' from module `\top'.
  Cell `$and$top.v:4429$1628' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4429$1628_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4429$1628' from module `\top'.
  Cell `$and$top.v:4436$1631' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4436$1631_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4436$1631' from module `\top'.
  Cell `$and$top.v:4443$1634' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4443$1634_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4443$1634' from module `\top'.
  Cell `$and$top.v:4450$1637' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4450$1637_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4450$1637' from module `\top'.
  Cell `$and$top.v:4457$1640' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4457$1640_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4457$1640' from module `\top'.
  Cell `$and$top.v:4464$1643' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4464$1643_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4464$1643' from module `\top'.
  Cell `$and$top.v:4471$1646' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4471$1646_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4471$1646' from module `\top'.
  Cell `$and$top.v:4478$1649' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4478$1649_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4478$1649' from module `\top'.
  Cell `$and$top.v:4485$1652' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4485$1652_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4485$1652' from module `\top'.
  Cell `$and$top.v:4492$1655' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4492$1655_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4492$1655' from module `\top'.
  Cell `$and$top.v:4499$1658' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4499$1658_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4499$1658' from module `\top'.
  Cell `$and$top.v:4506$1661' is identical to cell `$and$top.v:4387$1606'.
    Redirecting output \Y: $and$top.v:4506$1661_Y = $and$top.v:4387$1606_Y
    Removing $and cell `$and$top.v:4506$1661' from module `\top'.
  Cell `$and$top.v:4517$1670' is identical to cell `$and$top.v:4513$1665'.
    Redirecting output \Y: $and$top.v:4517$1670_Y = $and$top.v:4513$1665_Y
    Removing $and cell `$and$top.v:4517$1670' from module `\top'.
Removed a total of 396 cells.

21.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$3423 (pure)
    Root of a mux tree: $procmux$3426 (pure)
    Root of a mux tree: $procmux$3429 (pure)
    Root of a mux tree: $procmux$3432 (pure)
    Root of a mux tree: $procmux$3435 (pure)
    Root of a mux tree: $procmux$3438 (pure)
    Root of a mux tree: $procmux$3441 (pure)
    Root of a mux tree: $procmux$3444 (pure)
    Root of a mux tree: $procmux$3447 (pure)
    Root of a mux tree: $procmux$3450 (pure)
    Root of a mux tree: $procmux$3453 (pure)
    Root of a mux tree: $procmux$3456 (pure)
    Root of a mux tree: $procmux$3459 (pure)
    Root of a mux tree: $procmux$3462 (pure)
    Root of a mux tree: $procmux$3465 (pure)
    Root of a mux tree: $procmux$3468 (pure)
    Root of a mux tree: $procmux$3471 (pure)
    Root of a mux tree: $procmux$3474 (pure)
    Root of a mux tree: $procmux$3477 (pure)
    Root of a mux tree: $procmux$3480 (pure)
    Root of a mux tree: $procmux$3483 (pure)
    Root of a mux tree: $procmux$3486 (pure)
    Root of a mux tree: $procmux$3489 (pure)
    Root of a mux tree: $procmux$3492 (pure)
    Root of a mux tree: $procmux$3495 (pure)
    Root of a mux tree: $procmux$3498 (pure)
    Root of a mux tree: $procmux$3501 (pure)
    Root of a mux tree: $procmux$3504 (pure)
    Root of a mux tree: $procmux$3507 (pure)
    Root of a mux tree: $procmux$3510 (pure)
    Root of a mux tree: $procmux$3513 (pure)
    Root of a mux tree: $procmux$3516 (pure)
    Root of a mux tree: $procmux$3519 (pure)
    Root of a mux tree: $procmux$3522 (pure)
    Root of a mux tree: $procmux$3525 (pure)
    Root of a mux tree: $procmux$3531 (pure)
    Root of a mux tree: $procmux$3540 (pure)
    Root of a mux tree: $procmux$3549 (pure)
    Root of a mux tree: $procmux$3558 (pure)
    Root of a mux tree: $procmux$3567 (pure)
    Root of a mux tree: $procmux$3576 (pure)
    Root of a mux tree: $procmux$3585 (pure)
    Root of a mux tree: $procmux$3594 (pure)
    Root of a mux tree: $procmux$3603 (pure)
    Root of a mux tree: $procmux$3612 (pure)
    Root of a mux tree: $procmux$3621 (pure)
    Root of a mux tree: $procmux$3630 (pure)
    Root of a mux tree: $procmux$3639 (pure)
    Root of a mux tree: $procmux$3648 (pure)
    Root of a mux tree: $procmux$3657 (pure)
    Root of a mux tree: $procmux$3666 (pure)
    Root of a mux tree: $procmux$3755 (pure)
    Root of a mux tree: $procmux$3773 (pure)
    Root of a mux tree: $procmux$3863 (pure)
    Root of a mux tree: $procmux$3869 (pure)
    Root of a mux tree: $procmux$3872 (pure)
    Root of a mux tree: $procmux$3878 (pure)
    Root of a mux tree: $procmux$3881 (pure)
    Root of a mux tree: $procmux$3887 (pure)
    Root of a mux tree: $procmux$3890 (pure)
    Root of a mux tree: $procmux$3896 (pure)
    Root of a mux tree: $procmux$3902 (pure)
    Root of a mux tree: $procmux$3908 (pure)
    Root of a mux tree: $procmux$3914 (pure)
    Root of a mux tree: $procmux$3920 (pure)
    Root of a mux tree: $procmux$3926 (pure)
    Root of a mux tree: $procmux$3932 (pure)
    Root of a mux tree: $procmux$3941 (pure)
    Root of a mux tree: $procmux$3950 (pure)
    Root of a mux tree: $procmux$3959 (pure)
    Root of a mux tree: $procmux$3968 (pure)
    Root of a mux tree: $procmux$3977 (pure)
    Root of a mux tree: $procmux$3986 (pure)
    Root of a mux tree: $procmux$3995 (pure)
    Root of a mux tree: $procmux$4004 (pure)
    Root of a mux tree: $procmux$4010 (pure)
    Root of a mux tree: $procmux$4022 (pure)
    Root of a mux tree: $procmux$4028 (pure)
    Root of a mux tree: $procmux$4034 (pure)
    Root of a mux tree: $procmux$4043 (pure)
    Root of a mux tree: $procmux$4049 (pure)
    Root of a mux tree: $procmux$4064 (pure)
    Root of a mux tree: $procmux$4070 (pure)
    Root of a mux tree: $procmux$4076 (pure)
    Root of a mux tree: $procmux$4082 (pure)
    Root of a mux tree: $procmux$4088 (pure)
    Root of a mux tree: $procmux$4094 (pure)
    Root of a mux tree: $procmux$4100 (pure)
    Root of a mux tree: $procmux$4106 (pure)
    Root of a mux tree: $procmux$4112 (pure)
    Root of a mux tree: $procmux$4118 (pure)
    Root of a mux tree: $procmux$4124 (pure)
    Root of a mux tree: $procmux$4130 (pure)
    Root of a mux tree: $procmux$4136 (pure)
    Root of a mux tree: $procmux$4145 (pure)
    Root of a mux tree: $procmux$4151 (pure)
    Root of a mux tree: $procmux$4157 (pure)
    Root of a mux tree: $procmux$4206 (pure)
    Root of a mux tree: $procmux$4220 (pure)
    Root of a mux tree: $procmux$4234 (pure)
    Root of a mux tree: $procmux$4268 (pure)
    Root of a mux tree: $procmux$4285 (pure)
    Root of a mux tree: $procmux$4329 (pure)
    Root of a mux tree: $procmux$4332 (pure)
    Root of a mux tree: $procmux$4352 (pure)
    Root of a mux tree: $procmux$4355 (pure)
    Root of a mux tree: $procmux$4358 (pure)
    Root of a mux tree: $procmux$4361 (pure)
    Root of a mux tree: $procmux$4373 (pure)
    Root of a mux tree: $procmux$4376 (pure)
    Root of a mux tree: $procmux$4388 (pure)
    Root of a mux tree: $procmux$4391 (pure)
    Root of a mux tree: $procmux$4403 (pure)
    Root of a mux tree: $procmux$4406 (pure)
    Root of a mux tree: $procmux$4418 (pure)
    Root of a mux tree: $procmux$4421 (pure)
    Root of a mux tree: $procmux$4439 (pure)
    Root of a mux tree: $procmux$4451 (pure)
    Root of a mux tree: $procmux$4457 (pure)
    Root of a mux tree: $procmux$4460 (pure)
    Root of a mux tree: $procmux$4478 (pure)
    Root of a mux tree: $procmux$4493 (pure)
    Root of a mux tree: $procmux$4496 (pure)
    Root of a mux tree: $procmux$4499 (pure)
    Root of a mux tree: $procmux$4502 (pure)
    Root of a mux tree: $procmux$4508 (pure)
    Root of a mux tree: $procmux$4514 (pure)
    Root of a mux tree: $procmux$4523 (pure)
    Root of a mux tree: $procmux$4541 (pure)
      Replacing known input bits on port A of cell $procmux$4531: \grant -> 1'0
      Replacing known input bits on port B of cell $procmux$4529: \grant -> 1'1
      Replacing known input bits on port A of cell $procmux$4527: \grant -> 1'1
      Replacing known input bits on port B of cell $procmux$4537: \grant -> 1'0
      Replacing known input bits on port A of cell $procmux$4535: \grant -> 1'0
    Root of a mux tree: $procmux$4550 (pure)
      Replacing known input bits on port B of cell $procmux$4545: \usb_endpointin2_toggle -> 1'1
    Root of a mux tree: $procmux$4559 (pure)
    Root of a mux tree: $procmux$4568 (pure)
    Root of a mux tree: $procmux$4577 (pure)
    Root of a mux tree: $procmux$4590 (pure)
    Root of a mux tree: $procmux$4596 (pure)
    Root of a mux tree: $procmux$4605 (pure)
    Root of a mux tree: $procmux$4614 (pure)
    Root of a mux tree: $procmux$4617 (pure)
    Root of a mux tree: $procmux$4623 (pure)
    Root of a mux tree: $procmux$4632 (pure)
      Replacing known input bits on port B of cell $procmux$4627: \usb_endpointout1_toggle -> 1'1
    Root of a mux tree: $procmux$4641 (pure)
    Root of a mux tree: $procmux$4650 (pure)
    Root of a mux tree: $procmux$4659 (pure)
    Root of a mux tree: $procmux$4668 (pure)
    Root of a mux tree: $procmux$4674 (pure)
    Root of a mux tree: $procmux$4683 (pure)
    Root of a mux tree: $procmux$4692 (pure)
    Root of a mux tree: $procmux$4701 (pure)
      Replacing known input bits on port B of cell $procmux$4696: \usb_endpointin1_toggle -> 1'1
    Root of a mux tree: $procmux$4710 (pure)
    Root of a mux tree: $procmux$4719 (pure)
    Root of a mux tree: $procmux$4728 (pure)
    Root of a mux tree: $procmux$4738 (pure)
    Root of a mux tree: $procmux$4744 (pure)
    Root of a mux tree: $procmux$4753 (pure)
    Root of a mux tree: $procmux$4762 (pure)
    Root of a mux tree: $procmux$4782 (pure)
      Replacing known input bits on port B of cell $procmux$4777: \usb_endpointin0_toggle -> 1'1
    Root of a mux tree: $procmux$4791 (pure)
    Root of a mux tree: $procmux$4800 (pure)
    Root of a mux tree: $procmux$4809 (pure)
    Root of a mux tree: $procmux$4821 (pure)
    Root of a mux tree: $procmux$4827 (pure)
    Root of a mux tree: $procmux$4836 (pure)
    Root of a mux tree: $procmux$4845 (pure)
    Root of a mux tree: $procmux$4848 (pure)
    Root of a mux tree: $procmux$4854 (pure)
    Root of a mux tree: $procmux$4863 (pure)
      Replacing known input bits on port B of cell $procmux$4858: \usb_endpointout0_toggle -> 1'1
    Root of a mux tree: $procmux$4872 (pure)
    Root of a mux tree: $procmux$4881 (pure)
    Root of a mux tree: $procmux$4890 (pure)
    Root of a mux tree: $procmux$4903 (pure)
    Root of a mux tree: $procmux$4909 (pure)
    Root of a mux tree: $procmux$4918 (pure)
    Root of a mux tree: $procmux$4927 (pure)
    Root of a mux tree: $procmux$4933 (pure)
    Root of a mux tree: $procmux$4945 (pure)
    Root of a mux tree: $procmux$4951 (pure)
    Root of a mux tree: $procmux$4957 (pure)
    Root of a mux tree: $procmux$4963 (pure)
    Root of a mux tree: $procmux$4972 (pure)
    Root of a mux tree: $procmux$4981 (pure)
    Root of a mux tree: $procmux$4987 (pure)
    Root of a mux tree: $procmux$4993 (pure)
    Root of a mux tree: $procmux$5002 (pure)
    Root of a mux tree: $procmux$5011 (pure)
    Root of a mux tree: $procmux$5017 (pure)
    Root of a mux tree: $procmux$5026 (pure)
    Root of a mux tree: $procmux$5032 (pure)
    Root of a mux tree: $procmux$5038 (pure)
    Root of a mux tree: $procmux$5044 (pure)
    Root of a mux tree: $procmux$5050 (pure)
    Root of a mux tree: $procmux$5059 (pure)
    Root of a mux tree: $procmux$5068 (pure)
    Root of a mux tree: $procmux$5083 (pure)
    Root of a mux tree: $procmux$5095 (pure)
    Root of a mux tree: $procmux$5104 (pure)
    Root of a mux tree: $procmux$5113 (pure)
    Root of a mux tree: $procmux$5128 (pure)
    Root of a mux tree: $procmux$5140 (pure)
    Root of a mux tree: $procmux$5149 (pure)
    Root of a mux tree: $procmux$5161 (pure)
    Root of a mux tree: $procmux$5173 (pure)
    Root of a mux tree: $procmux$5194 (pure)
      Replacing known input bits on port A of cell $procmux$5185: \usbsoc_usbsoc_uart_phy_rx_busy -> 1'1
      Replacing known input bits on port A of cell $procmux$5181: \usbsoc_usbsoc_uart_phy_rx_busy -> 1'1
      Replacing known input bits on port A of cell $procmux$5177: \usbsoc_usbsoc_uart_phy_rx_busy -> 1'1
      Replacing known input bits on port A of cell $procmux$5189: \usbsoc_usbsoc_uart_phy_rx_busy -> 1'0
    Root of a mux tree: $procmux$5206 (pure)
    Root of a mux tree: $procmux$5221 (pure)
    Root of a mux tree: $procmux$5227 (pure)
    Root of a mux tree: $procmux$5233 (pure)
    Root of a mux tree: $procmux$5251 (pure)
    Root of a mux tree: $procmux$5266 (pure)
    Root of a mux tree: $procmux$5275 (pure)
    Root of a mux tree: $procmux$5290 (pure)
    Root of a mux tree: $procmux$5296 (pure)
    Root of a mux tree: $procmux$5302 (pure)
    Root of a mux tree: $procmux$5311 (pure)
    Root of a mux tree: $procmux$5320 (pure)
    Root of a mux tree: $procmux$5329 (pure)
    Root of a mux tree: $procmux$5347 (pure)
    Root of a mux tree: $procmux$5353 (pure)
    Root of a mux tree: $procmux$5362 (pure)
    Root of a mux tree: $procmux$5365 (pure)
    Root of a mux tree: $procmux$5368 (pure)
    Root of a mux tree: $procmux$5371 (pure)
    Root of a mux tree: $procmux$5374
    Root of a mux tree: $procmux$5377 (pure)
    Root of a mux tree: $procmux$5387 (pure)
    Root of a mux tree: $procmux$5408 (pure)
    Root of a mux tree: $procmux$5415 (pure)
    Root of a mux tree: $procmux$5418
    Root of a mux tree: $procmux$5421 (pure)
    Root of a mux tree: $procmux$5424 (pure)
    Root of a mux tree: $procmux$5427 (pure)
    Root of a mux tree: $procmux$5430 (pure)
    Root of a mux tree: $procmux$5433 (pure)
    Root of a mux tree: $procmux$5436 (pure)
    Root of a mux tree: $procmux$5439 (pure)
    Root of a mux tree: $procmux$5442 (pure)
    Root of a mux tree: $procmux$5445 (pure)
    Root of a mux tree: $procmux$5448 (pure)
    Root of a mux tree: $procmux$5451 (pure)
    Root of a mux tree: $procmux$5454 (pure)
    Root of a mux tree: $procmux$5457 (pure)
    Root of a mux tree: $procmux$5460 (pure)
    Root of a mux tree: $procmux$5463 (pure)
    Root of a mux tree: $procmux$5466 (pure)
    Root of a mux tree: $procmux$5469 (pure)
    Root of a mux tree: $procmux$5472 (pure)
    Root of a mux tree: $procmux$5475 (pure)
    Root of a mux tree: $procmux$5478 (pure)
    Root of a mux tree: $procmux$5481 (pure)
    Root of a mux tree: $procmux$5484 (pure)
    Root of a mux tree: $procmux$5493 (pure)
    Root of a mux tree: $procmux$5530
    Root of a mux tree: $procmux$5539
    Root of a mux tree: $procmux$5551 (pure)
    Root of a mux tree: $procmux$5570 (pure)
    Root of a mux tree: $procmux$5573 (pure)
    Root of a mux tree: $procmux$5607 (pure)
    Root of a mux tree: $procmux$5627 (pure)
    Root of a mux tree: $procmux$5649 (pure)
    Root of a mux tree: $procmux$5679 (pure)
    Root of a mux tree: $procmux$5687 (pure)
    Root of a mux tree: $procmux$5691 (pure)
    Root of a mux tree: $procmux$5704 (pure)
    Root of a mux tree: $procmux$5742 (pure)
    Root of a mux tree: $procmux$5751 (pure)
    Root of a mux tree: $procmux$5783 (pure)
    Root of a mux tree: $procmux$5791 (pure)
    Root of a mux tree: $procmux$5799 (pure)
    Root of a mux tree: $procmux$5802 (pure)
    Root of a mux tree: $procmux$5813 (pure)
    Root of a mux tree: $procmux$5818 (pure)
    Root of a mux tree: $procmux$5830 (pure)
    Root of a mux tree: $procmux$5846 (pure)
    Root of a mux tree: $procmux$5858 (pure)
    Root of a mux tree: $procmux$5877 (pure)
    Root of a mux tree: $procmux$5912 (pure)
    Root of a mux tree: $procmux$5923 (pure)
    Root of a mux tree: $procmux$5966 (pure)
    Root of a mux tree: $procmux$6008 (pure)
    Root of a mux tree: $procmux$6023 (pure)
    Root of a mux tree: $procmux$6067 (pure)
    Root of a mux tree: $procmux$6093 (pure)
    Root of a mux tree: $procmux$6105 (pure)
    Root of a mux tree: $procmux$6143 (pure)
    Root of a mux tree: $procmux$6161 (pure)
      Replacing known input bits on port A of cell $procmux$6159: \usbfsrx_rxnrzidecoder_state -> 1'1
      Replacing known input bits on port A of cell $procmux$6157: \usbfsrx_rxnrzidecoder_state -> 1'1
      Replacing known input bits on port A of cell $procmux$6152: \usbfsrx_rxnrzidecoder_state -> 1'0
      Replacing known input bits on port B of cell $procmux$6150: \usbfsrx_rxnrzidecoder_state -> 1'0
      Replacing known input bits on port A of cell $procmux$6147: \usbfsrx_rxnrzidecoder_state -> 1'0
    Root of a mux tree: $procmux$6181 (pure)
    Root of a mux tree: $procmux$6190 (pure)
    Root of a mux tree: $procmux$6201 (pure)
    Root of a mux tree: $procmux$6219 (pure)
    Root of a mux tree: $procmux$6222 (pure)
    Root of a mux tree: $procmux$6232 (pure)
    Root of a mux tree: $procmux$6237 (pure)
    Root of a mux tree: $procmux$6240 (pure)
    Root of a mux tree: $procmux$6243 (pure)
    Root of a mux tree: $procmux$6249 (pure)
    Root of a mux tree: $procmux$6258 (pure)
    Root of a mux tree: $procmux$6269 (pure)
    Root of a mux tree: $procmux$6279 (pure)
    Root of a mux tree: $procmux$6290 (pure)
    Root of a mux tree: $procmux$6338 (pure)
    Root of a mux tree: $procmux$6341 (pure)
    Root of a mux tree: $procmux$6357 (pure)
    Root of a mux tree: $procmux$6367 (pure)
    Root of a mux tree: $procmux$6373 (pure)
    Root of a mux tree: $procmux$6382 (pure)
    Root of a mux tree: $procmux$6392 (pure)
    Root of a mux tree: $procmux$6403
    Root of a mux tree: $procmux$6410 (pure)
    Root of a mux tree: $procmux$6413 (pure)
    Root of a mux tree: $procmux$6422 (pure)
    Root of a mux tree: $procmux$6425 (pure)
    Root of a mux tree: $procmux$6428 (pure)
    Root of a mux tree: $procmux$6437 (pure)
    Root of a mux tree: $procmux$6440 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2935 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2938 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2941 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2944 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2953 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2959 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2965 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2968 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2974 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2980 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2986 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2992 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2998 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3004 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3016 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3022 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3028 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3034 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3037 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3046 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3052 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3055 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3067 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3073 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3079 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3085 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3091 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3094 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3103 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3109 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3115 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3121 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3139 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3145 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3151 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3157 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3163 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3169 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3175 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3181 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3187 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3193 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3199 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3205 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3211 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3217 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3223 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3229 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3235 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3241 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3247 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3253 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3259 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3271 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3283 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3295 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3304 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3322 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3325 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3331 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3379
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3399
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3417
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3420 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1570$2469 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1583$2473
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1647$2489
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1657$2491
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1667$2493
    Root of a mux tree: $techmap\lm32_cpu.adder.$procmux$7084 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:92$707 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:93$710 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7356 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7359 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:599$127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6530 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6536 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6545 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6554 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6566 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6575 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6584 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6623 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6638 (pure)
      Replacing known input bits on port A of cell $techmap\lm32_cpu.instruction_unit.$procmux$6633: \lm32_cpu.instruction_unit.i_cyc_o -> 1'1
      Replacing known input bits on port A of cell $techmap\lm32_cpu.instruction_unit.$procmux$6631: \lm32_cpu.instruction_unit.i_cyc_o -> 1'1
      Replacing known input bits on port A of cell $techmap\lm32_cpu.instruction_unit.$procmux$6626: \lm32_cpu.instruction_unit.i_cyc_o -> 1'0
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6653 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6659 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6668 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6674 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6680 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6686 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6710
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6456 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6465 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6478 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6494 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6521 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6524 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2911 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2914 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2917 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2920 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2923 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2926 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2929 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2932 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7102 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7120 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7138 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6713 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6716 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6719 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6725 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6731 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6737 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6743 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6749 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6761 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6770 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6803 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6818 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6830 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6845 (pure)
      Replacing known input bits on port A of cell $techmap\lm32_cpu.load_store_unit.$procmux$6840: \lm32_cpu.load_store_unit.d_cyc_o -> 1'1
      Replacing known input bits on port A of cell $techmap\lm32_cpu.load_store_unit.$procmux$6833: \lm32_cpu.load_store_unit.d_cyc_o -> 1'0
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6857 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6866 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6884 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6927 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6971 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6988 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7012 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7035 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7045 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7081 (pure)
  Analyzing evaluation results.
    dead port 1/2 on $mux $procmux$4966.
    dead port 2/2 on $mux $procmux$6403.
    dead port 2/2 on $mux $techmap\lm32_cpu.$procmux$3286.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3310.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3343.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3346.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3349.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3355.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3358.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3364.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3387.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3390.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3396.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3405.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3408.
    dead port 1/2 on $mux $techmap\lm32_cpu.$procmux$3414.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7167.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7170.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7173.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7176.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7179.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7185.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7188.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7191.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7194.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7200.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7203.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7206.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7209.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7230.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7233.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7236.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7242.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7245.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7248.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7266.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7269.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7272.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7278.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7281.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7287.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7290.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7305.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7308.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7314.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7320.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7332.
    dead port 1/2 on $mux $techmap\lm32_cpu.decoder.$procmux$7353.
    dead port 1/2 on $mux $techmap\lm32_cpu.instruction_unit.$procmux$6692.
    dead port 1/2 on $mux $techmap\lm32_cpu.instruction_unit.$procmux$6695.
    dead port 1/2 on $mux $techmap\lm32_cpu.instruction_unit.$procmux$6701.
    dead port 2/2 on $mux $techmap\lm32_cpu.instruction_unit.$procmux$6707.
Removed 52 multiplexer ports.

21.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $techmap\lm32_cpu.interrupt_unit.$reduce_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:157$129: { \lm32_cpu.interrupt_unit.interrupt_n_exception [0] \lm32_cpu.interrupt_unit.interrupt_n_exception [1] \lm32_cpu.interrupt_unit.interrupt_n_exception [2] \lm32_cpu.interrupt_unit.interrupt_n_exception [3] \lm32_cpu.interrupt_unit.interrupt_n_exception [4] \lm32_cpu.interrupt_unit.interrupt_n_exception [5] \lm32_cpu.interrupt_unit.interrupt_n_exception [6] \lm32_cpu.interrupt_unit.interrupt_n_exception [7] \lm32_cpu.interrupt_unit.interrupt_n_exception [8] \lm32_cpu.interrupt_unit.interrupt_n_exception [9] \lm32_cpu.interrupt_unit.interrupt_n_exception [10] \lm32_cpu.interrupt_unit.interrupt_n_exception [11] \lm32_cpu.interrupt_unit.interrupt_n_exception [12] \lm32_cpu.interrupt_unit.interrupt_n_exception [13] \lm32_cpu.interrupt_unit.interrupt_n_exception [14] \lm32_cpu.interrupt_unit.interrupt_n_exception [15] \lm32_cpu.interrupt_unit.interrupt_n_exception [16] \lm32_cpu.interrupt_unit.interrupt_n_exception [17] \lm32_cpu.interrupt_unit.interrupt_n_exception [18] \lm32_cpu.interrupt_unit.interrupt_n_exception [19] \lm32_cpu.interrupt_unit.interrupt_n_exception [20] \lm32_cpu.interrupt_unit.interrupt_n_exception [21] \lm32_cpu.interrupt_unit.interrupt_n_exception [22] \lm32_cpu.interrupt_unit.interrupt_n_exception [23] \lm32_cpu.interrupt_unit.interrupt_n_exception [24] \lm32_cpu.interrupt_unit.interrupt_n_exception [25] \lm32_cpu.interrupt_unit.interrupt_n_exception [26] \lm32_cpu.interrupt_unit.interrupt_n_exception [27] \lm32_cpu.interrupt_unit.interrupt_n_exception [28] \lm32_cpu.interrupt_unit.interrupt_n_exception [29] \lm32_cpu.interrupt_unit.interrupt_n_exception [30] \lm32_cpu.interrupt_unit.interrupt_n_exception [31] }
    New input vector for $reduce_or cell $techmap\lm32_cpu.instruction_unit.icache.$reduce_or$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:361$2852: { \lm32_cpu.instruction_unit.icache.state [0] \lm32_cpu.instruction_unit.icache.state [1] }
    New input vector for $reduce_or cell $techmap\lm32_cpu.$procmux$3338_ANY: { $techmap\lm32_cpu.$procmux$3338_CMP [0] $techmap\lm32_cpu.$procmux$3338_CMP [1] $techmap\lm32_cpu.$procmux$3338_CMP [2] }
    New input vector for $reduce_and cell $techmap\lm32_cpu.instruction_unit.$reduce_and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:633$2843: { \lm32_cpu.instruction_unit.i_adr_o [2] \lm32_cpu.instruction_unit.i_adr_o [3] }
    Consolidated identical input bits for $mux cell $procmux$3423:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742
      New ports: A=1'0, B=1'1, Y=$0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0]
      New connections: $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [7:1] = { $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0] $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0] $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0] $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0] $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0] $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0] $0$memwr$\storage_6$top.v:4872$786_EN[7:0]$1742 [0] }
    Consolidated identical input bits for $mux cell $procmux$3432:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735
      New ports: A=1'0, B=1'1, Y=$0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0]
      New connections: $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [7:1] = { $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0] $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0] $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0] $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0] $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0] $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0] $0$memwr$\storage_5$top.v:4856$785_EN[7:0]$1735 [0] }
    Consolidated identical input bits for $mux cell $procmux$3441:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728
      New ports: A=1'0, B=1'1, Y=$0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0]
      New connections: $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [7:1] = { $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0] $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0] $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0] $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0] $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0] $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0] $0$memwr$\storage_4$top.v:4840$784_EN[7:0]$1728 [0] }
    Consolidated identical input bits for $mux cell $procmux$3450:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721
      New ports: A=1'0, B=1'1, Y=$0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0]
      New connections: $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [7:1] = { $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0] $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0] $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0] $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0] $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0] $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0] $0$memwr$\storage_3$top.v:4824$783_EN[7:0]$1721 [0] }
    Consolidated identical input bits for $mux cell $procmux$3459:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714
      New ports: A=1'0, B=1'1, Y=$0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0]
      New connections: $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [7:1] = { $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0] $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0] $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0] $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0] $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0] $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0] $0$memwr$\storage_2$top.v:4808$782_EN[7:0]$1714 [0] }
    Consolidated identical input bits for $mux cell $procmux$3471:
      Old ports: A=10'0000000000, B=10'1111111111, Y=$0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705
      New ports: A=1'0, B=1'1, Y=$0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0]
      New connections: $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [9:1] = { $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] $0$memwr$\storage_1$top.v:4739$781_EN[9:0]$1705 [0] }
    Consolidated identical input bits for $mux cell $procmux$3483:
      Old ports: A=10'0000000000, B=10'1111111111, Y=$0$memwr$\storage$top.v:4722$780_EN[9:0]$1698
      New ports: A=1'0, B=1'1, Y=$0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0]
      New connections: $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [9:1] = { $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] $0$memwr$\storage$top.v:4722$780_EN[9:0]$1698 [0] }
    Consolidated identical input bits for $mux cell $procmux$3492:
      Old ports: A=0, B=255, Y=$0$memwr$\mem$top.v:4705$776_EN[31:0]$1684
      New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0]
      New connections: $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [31:1] = { 24'000000000000000000000000 $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0] $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0] $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0] $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0] $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0] $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0] $0$memwr$\mem$top.v:4705$776_EN[31:0]$1684 [0] }
    Consolidated identical input bits for $mux cell $procmux$3501:
      Old ports: A=0, B=65280, Y=$0$memwr$\mem$top.v:4707$777_EN[31:0]$1687
      New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8]
      New connections: { $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [31:9] $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [7:0] } = { 16'0000000000000000 $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8] $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8] $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8] $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8] $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8] $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8] $0$memwr$\mem$top.v:4707$777_EN[31:0]$1687 [8] 8'00000000 }
    Consolidated identical input bits for $mux cell $procmux$3510:
      Old ports: A=0, B=16711680, Y=$0$memwr$\mem$top.v:4709$778_EN[31:0]$1690
      New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16]
      New connections: { $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [31:17] $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [15:0] } = { 8'00000000 $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16] $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16] $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16] $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16] $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16] $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16] $0$memwr$\mem$top.v:4709$778_EN[31:0]$1690 [16] 16'0000000000000000 }
    Consolidated identical input bits for $mux cell $procmux$3519:
      Old ports: A=0, B=32'11111111000000000000000000000000, Y=$0$memwr$\mem$top.v:4711$779_EN[31:0]$1693
      New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24]
      New connections: { $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [31:25] $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [23:0] } = { $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24] $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24] $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24] $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24] $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24] $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24] $0$memwr$\mem$top.v:4711$779_EN[31:0]$1693 [24] 24'000000000000000000000000 }
    New ctrl vector for $pmux cell $procmux$4161: { $eq$top.v:2811$1324_Y $procmux$4200_CMP $procmux$4199_CMP $procmux$4198_CMP $procmux$4197_CMP $procmux$4196_CMP $procmux$4195_CMP $procmux$4194_CMP $procmux$4192_CMP $procmux$4191_CMP $procmux$4190_CMP $procmux$4189_CMP $procmux$4188_CMP $procmux$4186_CMP $procmux$4184_CMP $procmux$4183_CMP $procmux$4182_CMP $procmux$4181_CMP $procmux$4180_CMP $procmux$4178_CMP $procmux$4176_CMP $procmux$4175_CMP $procmux$4174_CMP $procmux$4173_CMP $procmux$4172_CMP $procmux$4171_CMP $procmux$4170_CMP $eq$top.v:2879$1426_Y $eq$top.v:2881$1429_Y $procmux$4166_CMP $eq$top.v:2885$1435_Y $eq$top.v:2887$1438_Y $procmux$4162_CMP }
    New ctrl vector for $pmux cell $procmux$4247: { $eq$top.v:2731$1240_Y $procmux$4263_CMP $procmux$4262_CMP $procmux$4261_CMP $procmux$4260_CMP $procmux$4259_CMP $procmux$4258_CMP $procmux$4257_CMP $procmux$4256_CMP $procmux$4254_CMP $procmux$4253_CMP $procmux$4252_CMP $procmux$4251_CMP $procmux$4250_CMP $procmux$4249_CMP $eq$top.v:2763$1288_Y }
    New ctrl vector for $pmux cell $procmux$4289: { $eq$top.v:2811$1324_Y $procmux$4201_CMP $procmux$4200_CMP $procmux$4199_CMP $procmux$4198_CMP $procmux$4197_CMP $procmux$4196_CMP $procmux$4195_CMP $procmux$4194_CMP $procmux$4192_CMP $procmux$4191_CMP $procmux$4190_CMP $procmux$4189_CMP $procmux$4188_CMP $procmux$4187_CMP $procmux$4186_CMP $procmux$4185_CMP $procmux$4184_CMP $procmux$4183_CMP $procmux$4182_CMP $procmux$4181_CMP $procmux$4180_CMP $procmux$4179_CMP $procmux$4178_CMP $auto$opt_reduce.cc:132:opt_mux$7798 $procmux$4176_CMP $procmux$4175_CMP $procmux$4174_CMP $procmux$4173_CMP $procmux$4172_CMP }
    New ctrl vector for $pmux cell $procmux$4339: { $procmux$4347_CMP $procmux$4346_CMP $procmux$4345_CMP $procmux$4344_CMP $procmux$4343_CMP $procmux$4342_CMP $procmux$4341_CMP $procmux$4340_CMP }
    New ctrl vector for $mux cell $procmux$4545: { }
    New ctrl vector for $pmux cell $procmux$4581: $auto$opt_reduce.cc:132:opt_mux$7800
    New ctrl vector for $mux cell $procmux$4627: { }
    New ctrl vector for $mux cell $procmux$4696: { }
    New ctrl vector for $mux cell $procmux$4777: { }
    New ctrl vector for $mux cell $procmux$4858: { }
    New ctrl vector for $pmux cell $procmux$5380: { $procmux$4585_CMP $procmux$4583_CMP $auto$opt_reduce.cc:132:opt_mux$7802 }
    New ctrl vector for $pmux cell $procmux$5387: { $procmux$4585_CMP $procmux$4583_CMP $auto$opt_reduce.cc:132:opt_mux$7804 }
    New ctrl vector for $pmux cell $procmux$5560: $auto$opt_reduce.cc:132:opt_mux$7806
    New ctrl vector for $pmux cell $procmux$5679: $auto$opt_reduce.cc:132:opt_mux$7808
    New ctrl vector for $pmux cell $procmux$5691: $auto$opt_reduce.cc:132:opt_mux$7810
    New ctrl vector for $pmux cell $procmux$5783: $auto$opt_reduce.cc:132:opt_mux$7812
    New ctrl vector for $pmux cell $procmux$5802: $auto$opt_reduce.cc:132:opt_mux$7814
    New ctrl vector for $pmux cell $procmux$5912: $auto$opt_reduce.cc:132:opt_mux$7816
    New ctrl vector for $pmux cell $procmux$5923: $auto$opt_reduce.cc:132:opt_mux$7818
    New ctrl vector for $pmux cell $procmux$6222: $auto$opt_reduce.cc:132:opt_mux$7820
    New ctrl vector for $pmux cell $procmux$6279: $auto$opt_reduce.cc:132:opt_mux$7822
    New ctrl vector for $pmux cell $procmux$6385: $auto$opt_reduce.cc:132:opt_mux$7824
    Consolidated identical input bits for $mux cell $techmap\lm32_cpu.$procmux$2935:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777
      New ports: A=1'0, B=1'1, Y=$techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0]
      New connections: $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [31:1] = { $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] $techmap\lm32_cpu.$0$memwr$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:3037$2418_EN[31:0]$2777 [0] }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.$procmux$3369: { $auto$opt_reduce.cc:132:opt_mux$7826 $techmap\lm32_cpu.$procmux$3375_CMP $techmap\lm32_cpu.$procmux$3374_CMP $techmap\lm32_cpu.$procmux$3373_CMP $techmap\lm32_cpu.$procmux$3372_CMP $techmap\lm32_cpu.$procmux$3371_CMP $techmap\lm32_cpu.$procmux$3370_CMP }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.instruction_unit.icache.$procmux$6461: $auto$opt_reduce.cc:132:opt_mux$7828
    Consolidated identical input bits for $mux cell $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2914:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904
      New ports: A=1'0, B=1'1, Y=$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0]
      New connections: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [31:1] = { $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2899_EN[31:0]$2904 [0] }
    Consolidated identical input bits for $mux cell $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2926:
      Old ports: A=22'0000000000000000000000, B=22'1111111111111111111111, Y=$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893
      New ports: A=1'0, B=1'1, Y=$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0]
      New connections: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [21:1] = { $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$0$memwr$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:121$2888_EN[21:0]$2893 [0] }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.mc_arithmetic.$procmux$6910: { $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP $auto$opt_reduce.cc:132:opt_mux$7830 }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.mc_arithmetic.$procmux$6992: { $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP $techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP $techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP $auto$opt_reduce.cc:132:opt_mux$7832 }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.mc_arithmetic.$procmux$7038: { $auto$opt_reduce.cc:132:opt_mux$7836 $auto$opt_reduce.cc:132:opt_mux$7834 $techmap\lm32_cpu.mc_arithmetic.$procmux$6911_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7799: { $procmux$4582_CMP $procmux$4583_CMP $procmux$4584_CMP $procmux$4585_CMP $procmux$4586_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7797: { $procmux$4177_CMP $procmux$4193_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7801: { $procmux$4582_CMP $procmux$4584_CMP $procmux$4586_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7803: { $procmux$4582_CMP $procmux$4584_CMP $procmux$4586_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7805: { $procmux$5561_CMP $procmux$5562_CMP $procmux$5563_CMP $procmux$5564_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7807: { $procmux$5650_CMP $procmux$5657_CMP $procmux$5667_CMP $procmux$5677_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7809: { $procmux$5657_CMP $procmux$5667_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7811: { $procmux$5752_CMP $procmux$5756_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7813: { $procmux$5752_CMP $procmux$5756_CMP $procmux$5760_CMP $procmux$5767_CMP $procmux$5777_CMP $procmux$5781_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7815: { $procmux$5878_CMP $procmux$5882_CMP $procmux$5886_CMP $procmux$5890_CMP $procmux$5894_CMP $procmux$5907_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7817: { $procmux$5878_CMP $procmux$5882_CMP $procmux$5886_CMP $procmux$5890_CMP $procmux$5894_CMP $procmux$5907_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7819: { $procmux$6202_CMP $procmux$6206_CMP $procmux$6210_CMP $procmux$6214_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7821: { $procmux$4582_CMP $procmux$4583_CMP $procmux$4584_CMP $procmux$4585_CMP $procmux$4586_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7823: { $procmux$4582_CMP $procmux$4583_CMP $procmux$4584_CMP $procmux$4585_CMP $procmux$4586_CMP }
  Optimizing cells in module \top.
Performed a total of 59 changes.

21.7.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7821' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7823'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7822 = $auto$opt_reduce.cc:132:opt_mux$7824
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7821' from module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7815' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7817'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7816 = $auto$opt_reduce.cc:132:opt_mux$7818
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7815' from module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7801' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7803'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7802 = $auto$opt_reduce.cc:132:opt_mux$7804
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7801' from module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7799' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7823'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7800 = $auto$opt_reduce.cc:132:opt_mux$7824
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7799' from module `\top'.
  Cell `$procmux$5496' is identical to cell `$procmux$5491'.
    Redirecting output \Y: $procmux$5496_Y = $procmux$5491_Y
    Removing $mux cell `$procmux$5496' from module `\top'.
  Cell `$procmux$5625' is identical to cell `$procmux$5605'.
    Redirecting output \Y: $procmux$5625_Y = $procmux$5605_Y
    Removing $mux cell `$procmux$5625' from module `\top'.
  Cell `$procmux$5627' is identical to cell `$procmux$5607'.
    Redirecting output \Y: \usb_ep_addr_next_value_ce0 = \usb_transfer_tok_next_value_ce1
    Removing $mux cell `$procmux$5627' from module `\top'.
  Cell `$procmux$5835' is identical to cell `$procmux$5826'.
    Redirecting output \Y: $procmux$5835_Y = $procmux$5826_Y
    Removing $mux cell `$procmux$5835' from module `\top'.
  Cell `$procmux$5863' is identical to cell `$procmux$5854'.
    Redirecting output \Y: $procmux$5863_Y = $procmux$5854_Y
    Removing $mux cell `$procmux$5863' from module `\top'.
  Cell `$procmux$6006' is identical to cell `$procmux$5964'.
    Redirecting output \Y: $procmux$6006_Y = $procmux$5964_Y
    Removing $mux cell `$procmux$6006' from module `\top'.
  Cell `$procmux$6174' is identical to cell `$procmux$6147'.
    Redirecting output \Y: $procmux$6174_Y = $procmux$6147_Y
    Removing $mux cell `$procmux$6174' from module `\top'.
  Cell `$procmux$6177' is identical to cell `$procmux$6150'.
    Redirecting output \Y: $procmux$6177_Y = $procmux$6150_Y
    Removing $mux cell `$procmux$6177' from module `\top'.
  Cell `$procmux$6179' is identical to cell `$procmux$6152'.
    Redirecting output \Y: $procmux$6179_Y = $procmux$6152_Y
    Removing $mux cell `$procmux$6179' from module `\top'.
  Cell `$procmux$6184' is identical to cell `$procmux$5811'.
    Redirecting output \Y: $procmux$6184_Y = $procmux$5811_Y
    Removing $mux cell `$procmux$6184' from module `\top'.
  Cell `$procmux$6188' is identical to cell `$procmux$5811'.
    Redirecting output \Y: $procmux$6188_Y = $procmux$5811_Y
    Removing $mux cell `$procmux$6188' from module `\top'.
  Cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6517' is identical to cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6513'.
    Redirecting output \Y: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6517_Y = $techmap\lm32_cpu.instruction_unit.icache.$procmux$6513_Y
    Removing $mux cell `$techmap\lm32_cpu.instruction_unit.icache.$procmux$6517' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6936' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6931'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6936_Y = $techmap\lm32_cpu.mc_arithmetic.$procmux$6931_Y
    Removing $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6936' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6940' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6931'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6940_Y = $techmap\lm32_cpu.mc_arithmetic.$procmux$6931_Y
    Removing $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6940' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6944' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6931'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6944_Y = $techmap\lm32_cpu.mc_arithmetic.$procmux$6931_Y
    Removing $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6944' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6948' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6931'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$6948_Y = $techmap\lm32_cpu.mc_arithmetic.$procmux$6931_Y
    Removing $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6948' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7000' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$6996'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7000_Y = $techmap\lm32_cpu.mc_arithmetic.$procmux$6996_Y
    Removing $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7000' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7027' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7023'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7027_Y = $techmap\lm32_cpu.mc_arithmetic.$procmux$7023_Y
    Removing $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7027' from module `\top'.
  Cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7057' is identical to cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7052'.
    Redirecting output \Y: $techmap\lm32_cpu.mc_arithmetic.$procmux$7057_Y = $techmap\lm32_cpu.mc_arithmetic.$procmux$7052_Y
    Removing $mux cell `$techmap\lm32_cpu.mc_arithmetic.$procmux$7057' from module `\top'.
Removed a total of 23 cells.

21.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values).

21.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removing unused `$eq' cell `$procmux$4169_CMP0'.
  removing unused `$eq' cell `$procmux$4255_CMP0'.
  removed 473 unused temporary wires.
Removed 477 unused cells and 4447 unused wires.

21.7.5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing away select inverter for $mux cell `$procmux$3863' in module `top'.
Optimizing away select inverter for $mux cell `$procmux$4049' in module `top'.
Replacing $mux cell `$procmux$6190' (?) in module `\top' with constant driver `\usb_rx_nrzi_o_valid0 = $procmux$5811_Y'.

21.7.5.9. Rerunning OPT passes. (Maybe there is more to do..)

21.7.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$3423 (pure)
    Root of a mux tree: $procmux$3426 (pure)
    Root of a mux tree: $procmux$3429 (pure)
    Root of a mux tree: $procmux$3432 (pure)
    Root of a mux tree: $procmux$3435 (pure)
    Root of a mux tree: $procmux$3438 (pure)
    Root of a mux tree: $procmux$3441 (pure)
    Root of a mux tree: $procmux$3444 (pure)
    Root of a mux tree: $procmux$3447 (pure)
    Root of a mux tree: $procmux$3450 (pure)
    Root of a mux tree: $procmux$3453 (pure)
    Root of a mux tree: $procmux$3456 (pure)
    Root of a mux tree: $procmux$3459 (pure)
    Root of a mux tree: $procmux$3462 (pure)
    Root of a mux tree: $procmux$3465 (pure)
    Root of a mux tree: $procmux$3468 (pure)
    Root of a mux tree: $procmux$3471 (pure)
    Root of a mux tree: $procmux$3474 (pure)
    Root of a mux tree: $procmux$3477 (pure)
    Root of a mux tree: $procmux$3480 (pure)
    Root of a mux tree: $procmux$3483 (pure)
    Root of a mux tree: $procmux$3486 (pure)
    Root of a mux tree: $procmux$3489 (pure)
    Root of a mux tree: $procmux$3492 (pure)
    Root of a mux tree: $procmux$3495 (pure)
    Root of a mux tree: $procmux$3498 (pure)
    Root of a mux tree: $procmux$3501 (pure)
    Root of a mux tree: $procmux$3504 (pure)
    Root of a mux tree: $procmux$3507 (pure)
    Root of a mux tree: $procmux$3510 (pure)
    Root of a mux tree: $procmux$3513 (pure)
    Root of a mux tree: $procmux$3516 (pure)
    Root of a mux tree: $procmux$3519 (pure)
    Root of a mux tree: $procmux$3522 (pure)
    Root of a mux tree: $procmux$3525 (pure)
    Root of a mux tree: $procmux$3531 (pure)
    Root of a mux tree: $procmux$3540 (pure)
    Root of a mux tree: $procmux$3549 (pure)
    Root of a mux tree: $procmux$3558 (pure)
    Root of a mux tree: $procmux$3567 (pure)
    Root of a mux tree: $procmux$3576 (pure)
    Root of a mux tree: $procmux$3585 (pure)
    Root of a mux tree: $procmux$3594 (pure)
    Root of a mux tree: $procmux$3603 (pure)
    Root of a mux tree: $procmux$3612 (pure)
    Root of a mux tree: $procmux$3621 (pure)
    Root of a mux tree: $procmux$3630 (pure)
    Root of a mux tree: $procmux$3639 (pure)
    Root of a mux tree: $procmux$3648 (pure)
    Root of a mux tree: $procmux$3657 (pure)
    Root of a mux tree: $procmux$3666 (pure)
    Root of a mux tree: $procmux$3755 (pure)
    Root of a mux tree: $procmux$3773 (pure)
    Root of a mux tree: $procmux$3863 (pure)
    Root of a mux tree: $procmux$3869 (pure)
    Root of a mux tree: $procmux$3872 (pure)
    Root of a mux tree: $procmux$3878 (pure)
    Root of a mux tree: $procmux$3881 (pure)
    Root of a mux tree: $procmux$3887 (pure)
    Root of a mux tree: $procmux$3890 (pure)
    Root of a mux tree: $procmux$3896 (pure)
    Root of a mux tree: $procmux$3902 (pure)
    Root of a mux tree: $procmux$3908 (pure)
    Root of a mux tree: $procmux$3914 (pure)
    Root of a mux tree: $procmux$3920 (pure)
    Root of a mux tree: $procmux$3926 (pure)
    Root of a mux tree: $procmux$3932 (pure)
    Root of a mux tree: $procmux$3941 (pure)
    Root of a mux tree: $procmux$3950 (pure)
    Root of a mux tree: $procmux$3959 (pure)
    Root of a mux tree: $procmux$3968 (pure)
    Root of a mux tree: $procmux$3977 (pure)
    Root of a mux tree: $procmux$3986 (pure)
    Root of a mux tree: $procmux$3995 (pure)
    Root of a mux tree: $procmux$4004 (pure)
    Root of a mux tree: $procmux$4010 (pure)
    Root of a mux tree: $procmux$4022 (pure)
    Root of a mux tree: $procmux$4028 (pure)
    Root of a mux tree: $procmux$4034 (pure)
    Root of a mux tree: $procmux$4043 (pure)
    Root of a mux tree: $procmux$4049 (pure)
    Root of a mux tree: $procmux$4064 (pure)
    Root of a mux tree: $procmux$4070 (pure)
    Root of a mux tree: $procmux$4076 (pure)
    Root of a mux tree: $procmux$4082 (pure)
    Root of a mux tree: $procmux$4088 (pure)
    Root of a mux tree: $procmux$4094 (pure)
    Root of a mux tree: $procmux$4100 (pure)
    Root of a mux tree: $procmux$4106 (pure)
    Root of a mux tree: $procmux$4112 (pure)
    Root of a mux tree: $procmux$4118 (pure)
    Root of a mux tree: $procmux$4124 (pure)
    Root of a mux tree: $procmux$4130 (pure)
    Root of a mux tree: $procmux$4136 (pure)
    Root of a mux tree: $procmux$4145 (pure)
    Root of a mux tree: $procmux$4151 (pure)
    Root of a mux tree: $procmux$4157 (pure)
    Root of a mux tree: $procmux$4206 (pure)
    Root of a mux tree: $procmux$4220 (pure)
    Root of a mux tree: $procmux$4234 (pure)
    Root of a mux tree: $procmux$4268 (pure)
    Root of a mux tree: $procmux$4285 (pure)
    Root of a mux tree: $procmux$4329 (pure)
    Root of a mux tree: $procmux$4332 (pure)
    Root of a mux tree: $procmux$4352 (pure)
    Root of a mux tree: $procmux$4355 (pure)
    Root of a mux tree: $procmux$4358 (pure)
    Root of a mux tree: $procmux$4361 (pure)
    Root of a mux tree: $procmux$4373 (pure)
    Root of a mux tree: $procmux$4376 (pure)
    Root of a mux tree: $procmux$4388 (pure)
    Root of a mux tree: $procmux$4391 (pure)
    Root of a mux tree: $procmux$4403 (pure)
    Root of a mux tree: $procmux$4406 (pure)
    Root of a mux tree: $procmux$4418 (pure)
    Root of a mux tree: $procmux$4421 (pure)
    Root of a mux tree: $procmux$4439 (pure)
    Root of a mux tree: $procmux$4451 (pure)
    Root of a mux tree: $procmux$4457 (pure)
    Root of a mux tree: $procmux$4460 (pure)
    Root of a mux tree: $procmux$4478 (pure)
    Root of a mux tree: $procmux$4493 (pure)
    Root of a mux tree: $procmux$4496 (pure)
    Root of a mux tree: $procmux$4499 (pure)
    Root of a mux tree: $procmux$4502 (pure)
    Root of a mux tree: $procmux$4508 (pure)
    Root of a mux tree: $procmux$4514 (pure)
    Root of a mux tree: $procmux$4523 (pure)
    Root of a mux tree: $procmux$4541 (pure)
    Root of a mux tree: $procmux$4550 (pure)
    Root of a mux tree: $procmux$4559 (pure)
    Root of a mux tree: $procmux$4568 (pure)
    Root of a mux tree: $procmux$4577 (pure)
    Root of a mux tree: $procmux$4590 (pure)
    Root of a mux tree: $procmux$4596 (pure)
    Root of a mux tree: $procmux$4605 (pure)
    Root of a mux tree: $procmux$4614 (pure)
    Root of a mux tree: $procmux$4617 (pure)
    Root of a mux tree: $procmux$4623 (pure)
    Root of a mux tree: $procmux$4632 (pure)
    Root of a mux tree: $procmux$4641 (pure)
    Root of a mux tree: $procmux$4650 (pure)
    Root of a mux tree: $procmux$4659 (pure)
    Root of a mux tree: $procmux$4668 (pure)
    Root of a mux tree: $procmux$4674 (pure)
    Root of a mux tree: $procmux$4683 (pure)
    Root of a mux tree: $procmux$4692 (pure)
    Root of a mux tree: $procmux$4701 (pure)
    Root of a mux tree: $procmux$4710 (pure)
    Root of a mux tree: $procmux$4719 (pure)
    Root of a mux tree: $procmux$4728 (pure)
    Root of a mux tree: $procmux$4738 (pure)
    Root of a mux tree: $procmux$4744 (pure)
    Root of a mux tree: $procmux$4753 (pure)
    Root of a mux tree: $procmux$4762 (pure)
    Root of a mux tree: $procmux$4782 (pure)
    Root of a mux tree: $procmux$4791 (pure)
    Root of a mux tree: $procmux$4800 (pure)
    Root of a mux tree: $procmux$4809 (pure)
    Root of a mux tree: $procmux$4821 (pure)
    Root of a mux tree: $procmux$4827 (pure)
    Root of a mux tree: $procmux$4836 (pure)
    Root of a mux tree: $procmux$4845 (pure)
    Root of a mux tree: $procmux$4848 (pure)
    Root of a mux tree: $procmux$4854 (pure)
    Root of a mux tree: $procmux$4863 (pure)
    Root of a mux tree: $procmux$4872 (pure)
    Root of a mux tree: $procmux$4881 (pure)
    Root of a mux tree: $procmux$4890 (pure)
    Root of a mux tree: $procmux$4903 (pure)
    Root of a mux tree: $procmux$4909 (pure)
    Root of a mux tree: $procmux$4918 (pure)
    Root of a mux tree: $procmux$4927 (pure)
    Root of a mux tree: $procmux$4933 (pure)
    Root of a mux tree: $procmux$4945 (pure)
    Root of a mux tree: $procmux$4951 (pure)
    Root of a mux tree: $procmux$4957 (pure)
    Root of a mux tree: $procmux$4963 (pure)
    Root of a mux tree: $procmux$4972 (pure)
    Root of a mux tree: $procmux$4981 (pure)
    Root of a mux tree: $procmux$4987 (pure)
    Root of a mux tree: $procmux$4993 (pure)
    Root of a mux tree: $procmux$5002 (pure)
    Root of a mux tree: $procmux$5011 (pure)
    Root of a mux tree: $procmux$5017 (pure)
    Root of a mux tree: $procmux$5026 (pure)
    Root of a mux tree: $procmux$5032 (pure)
    Root of a mux tree: $procmux$5038 (pure)
    Root of a mux tree: $procmux$5044 (pure)
    Root of a mux tree: $procmux$5050 (pure)
    Root of a mux tree: $procmux$5059 (pure)
    Root of a mux tree: $procmux$5068 (pure)
    Root of a mux tree: $procmux$5083 (pure)
    Root of a mux tree: $procmux$5095 (pure)
    Root of a mux tree: $procmux$5104 (pure)
    Root of a mux tree: $procmux$5113 (pure)
    Root of a mux tree: $procmux$5128 (pure)
    Root of a mux tree: $procmux$5140 (pure)
    Root of a mux tree: $procmux$5149 (pure)
    Root of a mux tree: $procmux$5161 (pure)
    Root of a mux tree: $procmux$5173 (pure)
    Root of a mux tree: $procmux$5194 (pure)
    Root of a mux tree: $procmux$5206 (pure)
    Root of a mux tree: $procmux$5221 (pure)
    Root of a mux tree: $procmux$5227 (pure)
    Root of a mux tree: $procmux$5233 (pure)
    Root of a mux tree: $procmux$5251 (pure)
    Root of a mux tree: $procmux$5266 (pure)
    Root of a mux tree: $procmux$5275 (pure)
    Root of a mux tree: $procmux$5290 (pure)
    Root of a mux tree: $procmux$5296 (pure)
    Root of a mux tree: $procmux$5302 (pure)
    Root of a mux tree: $procmux$5311 (pure)
    Root of a mux tree: $procmux$5320 (pure)
    Root of a mux tree: $procmux$5329 (pure)
    Root of a mux tree: $procmux$5347 (pure)
    Root of a mux tree: $procmux$5353 (pure)
    Root of a mux tree: $procmux$5362 (pure)
    Root of a mux tree: $procmux$5365 (pure)
    Root of a mux tree: $procmux$5368 (pure)
    Root of a mux tree: $procmux$5371 (pure)
    Root of a mux tree: $procmux$5374
    Root of a mux tree: $procmux$5377 (pure)
    Root of a mux tree: $procmux$5387 (pure)
    Root of a mux tree: $procmux$5408 (pure)
    Root of a mux tree: $procmux$5415 (pure)
    Root of a mux tree: $procmux$5418
    Root of a mux tree: $procmux$5421 (pure)
    Root of a mux tree: $procmux$5424 (pure)
    Root of a mux tree: $procmux$5427 (pure)
    Root of a mux tree: $procmux$5430 (pure)
    Root of a mux tree: $procmux$5433 (pure)
    Root of a mux tree: $procmux$5436 (pure)
    Root of a mux tree: $procmux$5439 (pure)
    Root of a mux tree: $procmux$5442 (pure)
    Root of a mux tree: $procmux$5445 (pure)
    Root of a mux tree: $procmux$5448 (pure)
    Root of a mux tree: $procmux$5451 (pure)
    Root of a mux tree: $procmux$5454 (pure)
    Root of a mux tree: $procmux$5457 (pure)
    Root of a mux tree: $procmux$5460 (pure)
    Root of a mux tree: $procmux$5463 (pure)
    Root of a mux tree: $procmux$5466 (pure)
    Root of a mux tree: $procmux$5469 (pure)
    Root of a mux tree: $procmux$5472 (pure)
    Root of a mux tree: $procmux$5475 (pure)
    Root of a mux tree: $procmux$5478 (pure)
    Root of a mux tree: $procmux$5481 (pure)
    Root of a mux tree: $procmux$5484 (pure)
    Root of a mux tree: $procmux$5493 (pure)
    Root of a mux tree: $procmux$5530
    Root of a mux tree: $procmux$5539
    Root of a mux tree: $procmux$5551 (pure)
    Root of a mux tree: $procmux$5570 (pure)
    Root of a mux tree: $procmux$5573 (pure)
    Root of a mux tree: $procmux$5607 (pure)
    Root of a mux tree: $procmux$5649 (pure)
    Root of a mux tree: $procmux$5679 (pure)
    Root of a mux tree: $procmux$5687 (pure)
    Root of a mux tree: $procmux$5691 (pure)
    Root of a mux tree: $procmux$5704 (pure)
    Root of a mux tree: $procmux$5742 (pure)
    Root of a mux tree: $procmux$5751 (pure)
    Root of a mux tree: $procmux$5783 (pure)
    Root of a mux tree: $procmux$5791 (pure)
    Root of a mux tree: $procmux$5799 (pure)
    Root of a mux tree: $procmux$5802 (pure)
    Root of a mux tree: $procmux$5811 (pure)
    Root of a mux tree: $procmux$5813 (pure)
    Root of a mux tree: $procmux$5818 (pure)
    Root of a mux tree: $procmux$5826
    Root of a mux tree: $procmux$5830 (pure)
    Root of a mux tree: $procmux$5846 (pure)
    Root of a mux tree: $procmux$5854
    Root of a mux tree: $procmux$5858 (pure)
    Root of a mux tree: $procmux$5877 (pure)
    Root of a mux tree: $procmux$5912 (pure)
    Root of a mux tree: $procmux$5923 (pure)
    Root of a mux tree: $procmux$5964
    Root of a mux tree: $procmux$5966 (pure)
    Root of a mux tree: $procmux$6008 (pure)
    Root of a mux tree: $procmux$6023 (pure)
    Root of a mux tree: $procmux$6067 (pure)
    Root of a mux tree: $procmux$6093 (pure)
    Root of a mux tree: $procmux$6105 (pure)
    Root of a mux tree: $procmux$6143 (pure)
    Root of a mux tree: $procmux$6152
    Root of a mux tree: $procmux$6161 (pure)
    Root of a mux tree: $procmux$6181 (pure)
    Root of a mux tree: $procmux$6201 (pure)
    Root of a mux tree: $procmux$6219 (pure)
    Root of a mux tree: $procmux$6232 (pure)
    Root of a mux tree: $procmux$6237 (pure)
    Root of a mux tree: $procmux$6240 (pure)
    Root of a mux tree: $procmux$6243 (pure)
    Root of a mux tree: $procmux$6249 (pure)
    Root of a mux tree: $procmux$6258 (pure)
    Root of a mux tree: $procmux$6269 (pure)
    Root of a mux tree: $procmux$6279 (pure)
    Root of a mux tree: $procmux$6290 (pure)
    Root of a mux tree: $procmux$6338 (pure)
    Root of a mux tree: $procmux$6341 (pure)
    Root of a mux tree: $procmux$6357 (pure)
    Root of a mux tree: $procmux$6367 (pure)
    Root of a mux tree: $procmux$6373 (pure)
    Root of a mux tree: $procmux$6382 (pure)
    Root of a mux tree: $procmux$6392 (pure)
    Root of a mux tree: $procmux$6410 (pure)
    Root of a mux tree: $procmux$6413 (pure)
    Root of a mux tree: $procmux$6422 (pure)
    Root of a mux tree: $procmux$6425 (pure)
    Root of a mux tree: $procmux$6428 (pure)
    Root of a mux tree: $procmux$6437 (pure)
    Root of a mux tree: $procmux$6440 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2935 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2938 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2941 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2944 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2953 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2959 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2965 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2968 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2974 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2980 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2986 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2992 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2998 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3004 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3016 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3022 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3028 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3034 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3037 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3046 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3052 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3055 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3067 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3073 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3079 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3085 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3091 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3094 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3103 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3109 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3115 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3121 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3139 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3145 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3151 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3157 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3163 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3169 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3175 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3181 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3187 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3193 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3199 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3205 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3211 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3217 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3223 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3229 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3235 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3241 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3247 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3253 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3259 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3271 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3283 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3295 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3304 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3322 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3325 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3331 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3379
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3399
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3417
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3420 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1570$2469 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1583$2473
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1647$2489
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1657$2491
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1667$2493
    Root of a mux tree: $techmap\lm32_cpu.adder.$procmux$7084 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:92$707 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:93$710 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7356 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7359 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:599$127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6530 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6536 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6545 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6554 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6566 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6575 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6584 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6623 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6638 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6653 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6659 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6668 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6674 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6680 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6686 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6710
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6456 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6465 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6478 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6494 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6521 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6524 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2911 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2914 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2917 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2920 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2923 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2926 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2929 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2932 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7102 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7120 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7138 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6713 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6716 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6719 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6725 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6731 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6737 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6743 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6749 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6761 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6770 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6803 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6818 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6830 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6845 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6857 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6866 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6884 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6927 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6971 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6988 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7012 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7035 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7045 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7081 (pure)
  Analyzing evaluation results.
    dead port 1/2 on $mux $procmux$6222.
    dead port 2/2 on $mux $procmux$6222.
Removed 2 multiplexer ports.

21.7.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $procmux$5493: { $procmux$5526_CMP $procmux$5522_CMP $procmux$5506_CMP $eq$top.v:2071$894_Y $auto$opt_reduce.cc:132:opt_mux$7838 }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.instruction_unit.icache.$procmux$6503: { $auto$opt_reduce.cc:132:opt_mux$7840 $techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP $techmap\lm32_cpu.instruction_unit.icache.$procmux$6447_CMP }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.mc_arithmetic.$procmux$6933: { $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP $auto$opt_reduce.cc:132:opt_mux$7842 }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.mc_arithmetic.$procmux$6992: { $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP $auto$opt_reduce.cc:132:opt_mux$7844 $auto$opt_reduce.cc:132:opt_mux$7832 }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.mc_arithmetic.$procmux$7020: { $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP $auto$opt_reduce.cc:132:opt_mux$7846 $techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP }
    New ctrl vector for $pmux cell $techmap\lm32_cpu.mc_arithmetic.$procmux$7054: $auto$opt_reduce.cc:132:opt_mux$7848
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$7837: { $eq$top.v:2072$898_Y $procmux$5498_CMP }
  Optimizing cells in module \top.
Performed a total of 7 changes.

21.7.5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7845' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7847'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7846 = $auto$opt_reduce.cc:132:opt_mux$7848
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7845' from module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7843' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7847'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7844 = $auto$opt_reduce.cc:132:opt_mux$7848
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7843' from module `\top'.
Removed a total of 2 cells.

21.7.5.13. Executing OPT_RMDFF pass (remove dff with constant values).
Promoting init spec \usb_rx_line_state_dt = 1'0 to constant driver in module top.
Promoted 1 init specs to constant drivers.

21.7.5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removing unused non-port wire \usb_rx_line_state_dt.
  removed 4 unused temporary wires.
Removed 477 unused cells and 4451 unused wires.

21.7.5.15. Executing OPT_EXPR pass (perform const folding).

21.7.5.16. Rerunning OPT passes. (Maybe there is more to do..)

21.7.5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$3423 (pure)
    Root of a mux tree: $procmux$3426 (pure)
    Root of a mux tree: $procmux$3429 (pure)
    Root of a mux tree: $procmux$3432 (pure)
    Root of a mux tree: $procmux$3435 (pure)
    Root of a mux tree: $procmux$3438 (pure)
    Root of a mux tree: $procmux$3441 (pure)
    Root of a mux tree: $procmux$3444 (pure)
    Root of a mux tree: $procmux$3447 (pure)
    Root of a mux tree: $procmux$3450 (pure)
    Root of a mux tree: $procmux$3453 (pure)
    Root of a mux tree: $procmux$3456 (pure)
    Root of a mux tree: $procmux$3459 (pure)
    Root of a mux tree: $procmux$3462 (pure)
    Root of a mux tree: $procmux$3465 (pure)
    Root of a mux tree: $procmux$3468 (pure)
    Root of a mux tree: $procmux$3471 (pure)
    Root of a mux tree: $procmux$3474 (pure)
    Root of a mux tree: $procmux$3477 (pure)
    Root of a mux tree: $procmux$3480 (pure)
    Root of a mux tree: $procmux$3483 (pure)
    Root of a mux tree: $procmux$3486 (pure)
    Root of a mux tree: $procmux$3489 (pure)
    Root of a mux tree: $procmux$3492 (pure)
    Root of a mux tree: $procmux$3495 (pure)
    Root of a mux tree: $procmux$3498 (pure)
    Root of a mux tree: $procmux$3501 (pure)
    Root of a mux tree: $procmux$3504 (pure)
    Root of a mux tree: $procmux$3507 (pure)
    Root of a mux tree: $procmux$3510 (pure)
    Root of a mux tree: $procmux$3513 (pure)
    Root of a mux tree: $procmux$3516 (pure)
    Root of a mux tree: $procmux$3519 (pure)
    Root of a mux tree: $procmux$3522 (pure)
    Root of a mux tree: $procmux$3525 (pure)
    Root of a mux tree: $procmux$3531 (pure)
    Root of a mux tree: $procmux$3540 (pure)
    Root of a mux tree: $procmux$3549 (pure)
    Root of a mux tree: $procmux$3558 (pure)
    Root of a mux tree: $procmux$3567 (pure)
    Root of a mux tree: $procmux$3576 (pure)
    Root of a mux tree: $procmux$3585 (pure)
    Root of a mux tree: $procmux$3594 (pure)
    Root of a mux tree: $procmux$3603 (pure)
    Root of a mux tree: $procmux$3612 (pure)
    Root of a mux tree: $procmux$3621 (pure)
    Root of a mux tree: $procmux$3630 (pure)
    Root of a mux tree: $procmux$3639 (pure)
    Root of a mux tree: $procmux$3648 (pure)
    Root of a mux tree: $procmux$3657 (pure)
    Root of a mux tree: $procmux$3666 (pure)
    Root of a mux tree: $procmux$3755 (pure)
    Root of a mux tree: $procmux$3773 (pure)
    Root of a mux tree: $procmux$3863 (pure)
    Root of a mux tree: $procmux$3869 (pure)
    Root of a mux tree: $procmux$3872 (pure)
    Root of a mux tree: $procmux$3878 (pure)
    Root of a mux tree: $procmux$3881 (pure)
    Root of a mux tree: $procmux$3887 (pure)
    Root of a mux tree: $procmux$3890 (pure)
    Root of a mux tree: $procmux$3896 (pure)
    Root of a mux tree: $procmux$3902 (pure)
    Root of a mux tree: $procmux$3908 (pure)
    Root of a mux tree: $procmux$3914 (pure)
    Root of a mux tree: $procmux$3920 (pure)
    Root of a mux tree: $procmux$3926 (pure)
    Root of a mux tree: $procmux$3932 (pure)
    Root of a mux tree: $procmux$3941 (pure)
    Root of a mux tree: $procmux$3950 (pure)
    Root of a mux tree: $procmux$3959 (pure)
    Root of a mux tree: $procmux$3968 (pure)
    Root of a mux tree: $procmux$3977 (pure)
    Root of a mux tree: $procmux$3986 (pure)
    Root of a mux tree: $procmux$3995 (pure)
    Root of a mux tree: $procmux$4004 (pure)
    Root of a mux tree: $procmux$4010 (pure)
    Root of a mux tree: $procmux$4022 (pure)
    Root of a mux tree: $procmux$4028 (pure)
    Root of a mux tree: $procmux$4034 (pure)
    Root of a mux tree: $procmux$4043 (pure)
    Root of a mux tree: $procmux$4049 (pure)
    Root of a mux tree: $procmux$4064 (pure)
    Root of a mux tree: $procmux$4070 (pure)
    Root of a mux tree: $procmux$4076 (pure)
    Root of a mux tree: $procmux$4082 (pure)
    Root of a mux tree: $procmux$4088 (pure)
    Root of a mux tree: $procmux$4094 (pure)
    Root of a mux tree: $procmux$4100 (pure)
    Root of a mux tree: $procmux$4106 (pure)
    Root of a mux tree: $procmux$4112 (pure)
    Root of a mux tree: $procmux$4118 (pure)
    Root of a mux tree: $procmux$4124 (pure)
    Root of a mux tree: $procmux$4130 (pure)
    Root of a mux tree: $procmux$4136 (pure)
    Root of a mux tree: $procmux$4145 (pure)
    Root of a mux tree: $procmux$4151 (pure)
    Root of a mux tree: $procmux$4157 (pure)
    Root of a mux tree: $procmux$4206 (pure)
    Root of a mux tree: $procmux$4220 (pure)
    Root of a mux tree: $procmux$4234 (pure)
    Root of a mux tree: $procmux$4268 (pure)
    Root of a mux tree: $procmux$4285 (pure)
    Root of a mux tree: $procmux$4329 (pure)
    Root of a mux tree: $procmux$4332 (pure)
    Root of a mux tree: $procmux$4352 (pure)
    Root of a mux tree: $procmux$4355 (pure)
    Root of a mux tree: $procmux$4358 (pure)
    Root of a mux tree: $procmux$4361 (pure)
    Root of a mux tree: $procmux$4373 (pure)
    Root of a mux tree: $procmux$4376 (pure)
    Root of a mux tree: $procmux$4388 (pure)
    Root of a mux tree: $procmux$4391 (pure)
    Root of a mux tree: $procmux$4403 (pure)
    Root of a mux tree: $procmux$4406 (pure)
    Root of a mux tree: $procmux$4418 (pure)
    Root of a mux tree: $procmux$4421 (pure)
    Root of a mux tree: $procmux$4439 (pure)
    Root of a mux tree: $procmux$4451 (pure)
    Root of a mux tree: $procmux$4457 (pure)
    Root of a mux tree: $procmux$4460 (pure)
    Root of a mux tree: $procmux$4478 (pure)
    Root of a mux tree: $procmux$4493 (pure)
    Root of a mux tree: $procmux$4496 (pure)
    Root of a mux tree: $procmux$4499 (pure)
    Root of a mux tree: $procmux$4502 (pure)
    Root of a mux tree: $procmux$4508 (pure)
    Root of a mux tree: $procmux$4514 (pure)
    Root of a mux tree: $procmux$4523 (pure)
    Root of a mux tree: $procmux$4541 (pure)
    Root of a mux tree: $procmux$4550 (pure)
    Root of a mux tree: $procmux$4559 (pure)
    Root of a mux tree: $procmux$4568 (pure)
    Root of a mux tree: $procmux$4577 (pure)
    Root of a mux tree: $procmux$4590 (pure)
    Root of a mux tree: $procmux$4596 (pure)
    Root of a mux tree: $procmux$4605 (pure)
    Root of a mux tree: $procmux$4614 (pure)
    Root of a mux tree: $procmux$4617 (pure)
    Root of a mux tree: $procmux$4623 (pure)
    Root of a mux tree: $procmux$4632 (pure)
    Root of a mux tree: $procmux$4641 (pure)
    Root of a mux tree: $procmux$4650 (pure)
    Root of a mux tree: $procmux$4659 (pure)
    Root of a mux tree: $procmux$4668 (pure)
    Root of a mux tree: $procmux$4674 (pure)
    Root of a mux tree: $procmux$4683 (pure)
    Root of a mux tree: $procmux$4692 (pure)
    Root of a mux tree: $procmux$4701 (pure)
    Root of a mux tree: $procmux$4710 (pure)
    Root of a mux tree: $procmux$4719 (pure)
    Root of a mux tree: $procmux$4728 (pure)
    Root of a mux tree: $procmux$4738 (pure)
    Root of a mux tree: $procmux$4744 (pure)
    Root of a mux tree: $procmux$4753 (pure)
    Root of a mux tree: $procmux$4762 (pure)
    Root of a mux tree: $procmux$4782 (pure)
    Root of a mux tree: $procmux$4791 (pure)
    Root of a mux tree: $procmux$4800 (pure)
    Root of a mux tree: $procmux$4809 (pure)
    Root of a mux tree: $procmux$4821 (pure)
    Root of a mux tree: $procmux$4827 (pure)
    Root of a mux tree: $procmux$4836 (pure)
    Root of a mux tree: $procmux$4845 (pure)
    Root of a mux tree: $procmux$4848 (pure)
    Root of a mux tree: $procmux$4854 (pure)
    Root of a mux tree: $procmux$4863 (pure)
    Root of a mux tree: $procmux$4872 (pure)
    Root of a mux tree: $procmux$4881 (pure)
    Root of a mux tree: $procmux$4890 (pure)
    Root of a mux tree: $procmux$4903 (pure)
    Root of a mux tree: $procmux$4909 (pure)
    Root of a mux tree: $procmux$4918 (pure)
    Root of a mux tree: $procmux$4927 (pure)
    Root of a mux tree: $procmux$4933 (pure)
    Root of a mux tree: $procmux$4945 (pure)
    Root of a mux tree: $procmux$4951 (pure)
    Root of a mux tree: $procmux$4957 (pure)
    Root of a mux tree: $procmux$4963 (pure)
    Root of a mux tree: $procmux$4972 (pure)
    Root of a mux tree: $procmux$4981 (pure)
    Root of a mux tree: $procmux$4987 (pure)
    Root of a mux tree: $procmux$4993 (pure)
    Root of a mux tree: $procmux$5002 (pure)
    Root of a mux tree: $procmux$5011 (pure)
    Root of a mux tree: $procmux$5017 (pure)
    Root of a mux tree: $procmux$5026 (pure)
    Root of a mux tree: $procmux$5032 (pure)
    Root of a mux tree: $procmux$5038 (pure)
    Root of a mux tree: $procmux$5044 (pure)
    Root of a mux tree: $procmux$5050 (pure)
    Root of a mux tree: $procmux$5059 (pure)
    Root of a mux tree: $procmux$5068 (pure)
    Root of a mux tree: $procmux$5083 (pure)
    Root of a mux tree: $procmux$5095 (pure)
    Root of a mux tree: $procmux$5104 (pure)
    Root of a mux tree: $procmux$5113 (pure)
    Root of a mux tree: $procmux$5128 (pure)
    Root of a mux tree: $procmux$5140 (pure)
    Root of a mux tree: $procmux$5149 (pure)
    Root of a mux tree: $procmux$5161 (pure)
    Root of a mux tree: $procmux$5173 (pure)
    Root of a mux tree: $procmux$5194 (pure)
    Root of a mux tree: $procmux$5206 (pure)
    Root of a mux tree: $procmux$5221 (pure)
    Root of a mux tree: $procmux$5227 (pure)
    Root of a mux tree: $procmux$5233 (pure)
    Root of a mux tree: $procmux$5251 (pure)
    Root of a mux tree: $procmux$5266 (pure)
    Root of a mux tree: $procmux$5275 (pure)
    Root of a mux tree: $procmux$5290 (pure)
    Root of a mux tree: $procmux$5296 (pure)
    Root of a mux tree: $procmux$5302 (pure)
    Root of a mux tree: $procmux$5311 (pure)
    Root of a mux tree: $procmux$5320 (pure)
    Root of a mux tree: $procmux$5329 (pure)
    Root of a mux tree: $procmux$5347 (pure)
    Root of a mux tree: $procmux$5353 (pure)
    Root of a mux tree: $procmux$5362 (pure)
    Root of a mux tree: $procmux$5365 (pure)
    Root of a mux tree: $procmux$5368 (pure)
    Root of a mux tree: $procmux$5371 (pure)
    Root of a mux tree: $procmux$5374
    Root of a mux tree: $procmux$5377 (pure)
    Root of a mux tree: $procmux$5387 (pure)
    Root of a mux tree: $procmux$5408 (pure)
    Root of a mux tree: $procmux$5415 (pure)
    Root of a mux tree: $procmux$5418
    Root of a mux tree: $procmux$5421 (pure)
    Root of a mux tree: $procmux$5424 (pure)
    Root of a mux tree: $procmux$5427 (pure)
    Root of a mux tree: $procmux$5430 (pure)
    Root of a mux tree: $procmux$5433 (pure)
    Root of a mux tree: $procmux$5436 (pure)
    Root of a mux tree: $procmux$5439 (pure)
    Root of a mux tree: $procmux$5442 (pure)
    Root of a mux tree: $procmux$5445 (pure)
    Root of a mux tree: $procmux$5448 (pure)
    Root of a mux tree: $procmux$5451 (pure)
    Root of a mux tree: $procmux$5454 (pure)
    Root of a mux tree: $procmux$5457 (pure)
    Root of a mux tree: $procmux$5460 (pure)
    Root of a mux tree: $procmux$5463 (pure)
    Root of a mux tree: $procmux$5466 (pure)
    Root of a mux tree: $procmux$5469 (pure)
    Root of a mux tree: $procmux$5472 (pure)
    Root of a mux tree: $procmux$5475 (pure)
    Root of a mux tree: $procmux$5478 (pure)
    Root of a mux tree: $procmux$5481 (pure)
    Root of a mux tree: $procmux$5484 (pure)
    Root of a mux tree: $procmux$5493 (pure)
    Root of a mux tree: $procmux$5530
    Root of a mux tree: $procmux$5539
    Root of a mux tree: $procmux$5551 (pure)
    Root of a mux tree: $procmux$5570 (pure)
    Root of a mux tree: $procmux$5573 (pure)
    Root of a mux tree: $procmux$5607 (pure)
    Root of a mux tree: $procmux$5649 (pure)
    Root of a mux tree: $procmux$5679 (pure)
    Root of a mux tree: $procmux$5687 (pure)
    Root of a mux tree: $procmux$5691 (pure)
    Root of a mux tree: $procmux$5704 (pure)
    Root of a mux tree: $procmux$5742 (pure)
    Root of a mux tree: $procmux$5751 (pure)
    Root of a mux tree: $procmux$5783 (pure)
    Root of a mux tree: $procmux$5791 (pure)
    Root of a mux tree: $procmux$5799 (pure)
    Root of a mux tree: $procmux$5802 (pure)
    Root of a mux tree: $procmux$5811 (pure)
    Root of a mux tree: $procmux$5813 (pure)
    Root of a mux tree: $procmux$5818 (pure)
    Root of a mux tree: $procmux$5826
    Root of a mux tree: $procmux$5830 (pure)
    Root of a mux tree: $procmux$5846 (pure)
    Root of a mux tree: $procmux$5854
    Root of a mux tree: $procmux$5858 (pure)
    Root of a mux tree: $procmux$5877 (pure)
    Root of a mux tree: $procmux$5912 (pure)
    Root of a mux tree: $procmux$5923 (pure)
    Root of a mux tree: $procmux$5964
    Root of a mux tree: $procmux$5966 (pure)
    Root of a mux tree: $procmux$6008 (pure)
    Root of a mux tree: $procmux$6023 (pure)
    Root of a mux tree: $procmux$6067 (pure)
    Root of a mux tree: $procmux$6093 (pure)
    Root of a mux tree: $procmux$6105 (pure)
    Root of a mux tree: $procmux$6143 (pure)
    Root of a mux tree: $procmux$6152
    Root of a mux tree: $procmux$6161 (pure)
    Root of a mux tree: $procmux$6181 (pure)
    Root of a mux tree: $procmux$6201 (pure)
    Root of a mux tree: $procmux$6219 (pure)
    Root of a mux tree: $procmux$6232 (pure)
    Root of a mux tree: $procmux$6237 (pure)
    Root of a mux tree: $procmux$6240 (pure)
    Root of a mux tree: $procmux$6243 (pure)
    Root of a mux tree: $procmux$6249 (pure)
    Root of a mux tree: $procmux$6258 (pure)
    Root of a mux tree: $procmux$6269 (pure)
    Root of a mux tree: $procmux$6279 (pure)
    Root of a mux tree: $procmux$6290 (pure)
    Root of a mux tree: $procmux$6338 (pure)
    Root of a mux tree: $procmux$6341 (pure)
    Root of a mux tree: $procmux$6357 (pure)
    Root of a mux tree: $procmux$6367 (pure)
    Root of a mux tree: $procmux$6373 (pure)
    Root of a mux tree: $procmux$6382 (pure)
    Root of a mux tree: $procmux$6392 (pure)
    Root of a mux tree: $procmux$6410 (pure)
    Root of a mux tree: $procmux$6413 (pure)
    Root of a mux tree: $procmux$6422 (pure)
    Root of a mux tree: $procmux$6425 (pure)
    Root of a mux tree: $procmux$6428 (pure)
    Root of a mux tree: $procmux$6437 (pure)
    Root of a mux tree: $procmux$6440 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2935 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2938 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2941 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2944 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2953 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2959 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2965 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2968 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2974 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2980 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2986 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2992 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2998 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3004 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3016 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3022 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3028 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3034 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3037 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3046 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3052 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3055 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3067 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3073 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3079 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3085 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3091 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3094 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3103 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3109 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3115 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3121 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3139 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3145 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3151 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3157 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3163 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3169 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3175 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3181 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3187 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3193 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3199 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3205 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3211 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3217 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3223 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3229 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3235 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3241 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3247 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3253 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3259 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3271 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3283 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3295 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3304 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3322 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3325 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3331 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3379
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3399
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3417
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3420 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1570$2469 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1583$2473
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1647$2489
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1657$2491
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1667$2493
    Root of a mux tree: $techmap\lm32_cpu.adder.$procmux$7084 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:92$707 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:93$710 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7356 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7359 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:599$127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6530 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6536 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6545 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6554 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6566 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6575 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6584 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6623 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6638 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6653 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6659 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6668 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6674 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6680 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6686 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6710
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6456 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6465 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6478 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6494 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6521 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6524 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2911 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2914 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2917 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2920 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2923 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2926 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2929 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2932 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7102 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7120 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7138 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6713 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6716 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6719 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6725 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6731 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6737 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6743 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6749 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6761 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6770 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6803 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6818 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6830 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6845 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6857 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6866 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6884 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6927 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6971 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6988 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7012 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7035 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7045 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7081 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

21.7.5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.7.5.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7839' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7827'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7840 = $auto$opt_reduce.cc:132:opt_mux$7828
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7839' from module `\top'.
  Cell `$auto$opt_reduce.cc:126:opt_mux$7841' is identical to cell `$auto$opt_reduce.cc:126:opt_mux$7829'.
    Redirecting output \Y: $auto$opt_reduce.cc:132:opt_mux$7842 = $auto$opt_reduce.cc:132:opt_mux$7830
    Removing $reduce_or cell `$auto$opt_reduce.cc:126:opt_mux$7841' from module `\top'.
Removed a total of 2 cells.

21.7.5.20. Executing OPT_RMDFF pass (remove dff with constant values).

21.7.5.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removed 2 unused temporary wires.
Removed 477 unused cells and 4453 unused wires.

21.7.5.22. Executing OPT_EXPR pass (perform const folding).

21.7.5.23. Rerunning OPT passes. (Maybe there is more to do..)

21.7.5.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$3423 (pure)
    Root of a mux tree: $procmux$3426 (pure)
    Root of a mux tree: $procmux$3429 (pure)
    Root of a mux tree: $procmux$3432 (pure)
    Root of a mux tree: $procmux$3435 (pure)
    Root of a mux tree: $procmux$3438 (pure)
    Root of a mux tree: $procmux$3441 (pure)
    Root of a mux tree: $procmux$3444 (pure)
    Root of a mux tree: $procmux$3447 (pure)
    Root of a mux tree: $procmux$3450 (pure)
    Root of a mux tree: $procmux$3453 (pure)
    Root of a mux tree: $procmux$3456 (pure)
    Root of a mux tree: $procmux$3459 (pure)
    Root of a mux tree: $procmux$3462 (pure)
    Root of a mux tree: $procmux$3465 (pure)
    Root of a mux tree: $procmux$3468 (pure)
    Root of a mux tree: $procmux$3471 (pure)
    Root of a mux tree: $procmux$3474 (pure)
    Root of a mux tree: $procmux$3477 (pure)
    Root of a mux tree: $procmux$3480 (pure)
    Root of a mux tree: $procmux$3483 (pure)
    Root of a mux tree: $procmux$3486 (pure)
    Root of a mux tree: $procmux$3489 (pure)
    Root of a mux tree: $procmux$3492 (pure)
    Root of a mux tree: $procmux$3495 (pure)
    Root of a mux tree: $procmux$3498 (pure)
    Root of a mux tree: $procmux$3501 (pure)
    Root of a mux tree: $procmux$3504 (pure)
    Root of a mux tree: $procmux$3507 (pure)
    Root of a mux tree: $procmux$3510 (pure)
    Root of a mux tree: $procmux$3513 (pure)
    Root of a mux tree: $procmux$3516 (pure)
    Root of a mux tree: $procmux$3519 (pure)
    Root of a mux tree: $procmux$3522 (pure)
    Root of a mux tree: $procmux$3525 (pure)
    Root of a mux tree: $procmux$3531 (pure)
    Root of a mux tree: $procmux$3540 (pure)
    Root of a mux tree: $procmux$3549 (pure)
    Root of a mux tree: $procmux$3558 (pure)
    Root of a mux tree: $procmux$3567 (pure)
    Root of a mux tree: $procmux$3576 (pure)
    Root of a mux tree: $procmux$3585 (pure)
    Root of a mux tree: $procmux$3594 (pure)
    Root of a mux tree: $procmux$3603 (pure)
    Root of a mux tree: $procmux$3612 (pure)
    Root of a mux tree: $procmux$3621 (pure)
    Root of a mux tree: $procmux$3630 (pure)
    Root of a mux tree: $procmux$3639 (pure)
    Root of a mux tree: $procmux$3648 (pure)
    Root of a mux tree: $procmux$3657 (pure)
    Root of a mux tree: $procmux$3666 (pure)
    Root of a mux tree: $procmux$3755 (pure)
    Root of a mux tree: $procmux$3773 (pure)
    Root of a mux tree: $procmux$3863 (pure)
    Root of a mux tree: $procmux$3869 (pure)
    Root of a mux tree: $procmux$3872 (pure)
    Root of a mux tree: $procmux$3878 (pure)
    Root of a mux tree: $procmux$3881 (pure)
    Root of a mux tree: $procmux$3887 (pure)
    Root of a mux tree: $procmux$3890 (pure)
    Root of a mux tree: $procmux$3896 (pure)
    Root of a mux tree: $procmux$3902 (pure)
    Root of a mux tree: $procmux$3908 (pure)
    Root of a mux tree: $procmux$3914 (pure)
    Root of a mux tree: $procmux$3920 (pure)
    Root of a mux tree: $procmux$3926 (pure)
    Root of a mux tree: $procmux$3932 (pure)
    Root of a mux tree: $procmux$3941 (pure)
    Root of a mux tree: $procmux$3950 (pure)
    Root of a mux tree: $procmux$3959 (pure)
    Root of a mux tree: $procmux$3968 (pure)
    Root of a mux tree: $procmux$3977 (pure)
    Root of a mux tree: $procmux$3986 (pure)
    Root of a mux tree: $procmux$3995 (pure)
    Root of a mux tree: $procmux$4004 (pure)
    Root of a mux tree: $procmux$4010 (pure)
    Root of a mux tree: $procmux$4022 (pure)
    Root of a mux tree: $procmux$4028 (pure)
    Root of a mux tree: $procmux$4034 (pure)
    Root of a mux tree: $procmux$4043 (pure)
    Root of a mux tree: $procmux$4049 (pure)
    Root of a mux tree: $procmux$4064 (pure)
    Root of a mux tree: $procmux$4070 (pure)
    Root of a mux tree: $procmux$4076 (pure)
    Root of a mux tree: $procmux$4082 (pure)
    Root of a mux tree: $procmux$4088 (pure)
    Root of a mux tree: $procmux$4094 (pure)
    Root of a mux tree: $procmux$4100 (pure)
    Root of a mux tree: $procmux$4106 (pure)
    Root of a mux tree: $procmux$4112 (pure)
    Root of a mux tree: $procmux$4118 (pure)
    Root of a mux tree: $procmux$4124 (pure)
    Root of a mux tree: $procmux$4130 (pure)
    Root of a mux tree: $procmux$4136 (pure)
    Root of a mux tree: $procmux$4145 (pure)
    Root of a mux tree: $procmux$4151 (pure)
    Root of a mux tree: $procmux$4157 (pure)
    Root of a mux tree: $procmux$4206 (pure)
    Root of a mux tree: $procmux$4220 (pure)
    Root of a mux tree: $procmux$4234 (pure)
    Root of a mux tree: $procmux$4268 (pure)
    Root of a mux tree: $procmux$4285 (pure)
    Root of a mux tree: $procmux$4329 (pure)
    Root of a mux tree: $procmux$4332 (pure)
    Root of a mux tree: $procmux$4352 (pure)
    Root of a mux tree: $procmux$4355 (pure)
    Root of a mux tree: $procmux$4358 (pure)
    Root of a mux tree: $procmux$4361 (pure)
    Root of a mux tree: $procmux$4373 (pure)
    Root of a mux tree: $procmux$4376 (pure)
    Root of a mux tree: $procmux$4388 (pure)
    Root of a mux tree: $procmux$4391 (pure)
    Root of a mux tree: $procmux$4403 (pure)
    Root of a mux tree: $procmux$4406 (pure)
    Root of a mux tree: $procmux$4418 (pure)
    Root of a mux tree: $procmux$4421 (pure)
    Root of a mux tree: $procmux$4439 (pure)
    Root of a mux tree: $procmux$4451 (pure)
    Root of a mux tree: $procmux$4457 (pure)
    Root of a mux tree: $procmux$4460 (pure)
    Root of a mux tree: $procmux$4478 (pure)
    Root of a mux tree: $procmux$4493 (pure)
    Root of a mux tree: $procmux$4496 (pure)
    Root of a mux tree: $procmux$4499 (pure)
    Root of a mux tree: $procmux$4502 (pure)
    Root of a mux tree: $procmux$4508 (pure)
    Root of a mux tree: $procmux$4514 (pure)
    Root of a mux tree: $procmux$4523 (pure)
    Root of a mux tree: $procmux$4541 (pure)
    Root of a mux tree: $procmux$4550 (pure)
    Root of a mux tree: $procmux$4559 (pure)
    Root of a mux tree: $procmux$4568 (pure)
    Root of a mux tree: $procmux$4577 (pure)
    Root of a mux tree: $procmux$4590 (pure)
    Root of a mux tree: $procmux$4596 (pure)
    Root of a mux tree: $procmux$4605 (pure)
    Root of a mux tree: $procmux$4614 (pure)
    Root of a mux tree: $procmux$4617 (pure)
    Root of a mux tree: $procmux$4623 (pure)
    Root of a mux tree: $procmux$4632 (pure)
    Root of a mux tree: $procmux$4641 (pure)
    Root of a mux tree: $procmux$4650 (pure)
    Root of a mux tree: $procmux$4659 (pure)
    Root of a mux tree: $procmux$4668 (pure)
    Root of a mux tree: $procmux$4674 (pure)
    Root of a mux tree: $procmux$4683 (pure)
    Root of a mux tree: $procmux$4692 (pure)
    Root of a mux tree: $procmux$4701 (pure)
    Root of a mux tree: $procmux$4710 (pure)
    Root of a mux tree: $procmux$4719 (pure)
    Root of a mux tree: $procmux$4728 (pure)
    Root of a mux tree: $procmux$4738 (pure)
    Root of a mux tree: $procmux$4744 (pure)
    Root of a mux tree: $procmux$4753 (pure)
    Root of a mux tree: $procmux$4762 (pure)
    Root of a mux tree: $procmux$4782 (pure)
    Root of a mux tree: $procmux$4791 (pure)
    Root of a mux tree: $procmux$4800 (pure)
    Root of a mux tree: $procmux$4809 (pure)
    Root of a mux tree: $procmux$4821 (pure)
    Root of a mux tree: $procmux$4827 (pure)
    Root of a mux tree: $procmux$4836 (pure)
    Root of a mux tree: $procmux$4845 (pure)
    Root of a mux tree: $procmux$4848 (pure)
    Root of a mux tree: $procmux$4854 (pure)
    Root of a mux tree: $procmux$4863 (pure)
    Root of a mux tree: $procmux$4872 (pure)
    Root of a mux tree: $procmux$4881 (pure)
    Root of a mux tree: $procmux$4890 (pure)
    Root of a mux tree: $procmux$4903 (pure)
    Root of a mux tree: $procmux$4909 (pure)
    Root of a mux tree: $procmux$4918 (pure)
    Root of a mux tree: $procmux$4927 (pure)
    Root of a mux tree: $procmux$4933 (pure)
    Root of a mux tree: $procmux$4945 (pure)
    Root of a mux tree: $procmux$4951 (pure)
    Root of a mux tree: $procmux$4957 (pure)
    Root of a mux tree: $procmux$4963 (pure)
    Root of a mux tree: $procmux$4972 (pure)
    Root of a mux tree: $procmux$4981 (pure)
    Root of a mux tree: $procmux$4987 (pure)
    Root of a mux tree: $procmux$4993 (pure)
    Root of a mux tree: $procmux$5002 (pure)
    Root of a mux tree: $procmux$5011 (pure)
    Root of a mux tree: $procmux$5017 (pure)
    Root of a mux tree: $procmux$5026 (pure)
    Root of a mux tree: $procmux$5032 (pure)
    Root of a mux tree: $procmux$5038 (pure)
    Root of a mux tree: $procmux$5044 (pure)
    Root of a mux tree: $procmux$5050 (pure)
    Root of a mux tree: $procmux$5059 (pure)
    Root of a mux tree: $procmux$5068 (pure)
    Root of a mux tree: $procmux$5083 (pure)
    Root of a mux tree: $procmux$5095 (pure)
    Root of a mux tree: $procmux$5104 (pure)
    Root of a mux tree: $procmux$5113 (pure)
    Root of a mux tree: $procmux$5128 (pure)
    Root of a mux tree: $procmux$5140 (pure)
    Root of a mux tree: $procmux$5149 (pure)
    Root of a mux tree: $procmux$5161 (pure)
    Root of a mux tree: $procmux$5173 (pure)
    Root of a mux tree: $procmux$5194 (pure)
    Root of a mux tree: $procmux$5206 (pure)
    Root of a mux tree: $procmux$5221 (pure)
    Root of a mux tree: $procmux$5227 (pure)
    Root of a mux tree: $procmux$5233 (pure)
    Root of a mux tree: $procmux$5251 (pure)
    Root of a mux tree: $procmux$5266 (pure)
    Root of a mux tree: $procmux$5275 (pure)
    Root of a mux tree: $procmux$5290 (pure)
    Root of a mux tree: $procmux$5296 (pure)
    Root of a mux tree: $procmux$5302 (pure)
    Root of a mux tree: $procmux$5311 (pure)
    Root of a mux tree: $procmux$5320 (pure)
    Root of a mux tree: $procmux$5329 (pure)
    Root of a mux tree: $procmux$5347 (pure)
    Root of a mux tree: $procmux$5353 (pure)
    Root of a mux tree: $procmux$5362 (pure)
    Root of a mux tree: $procmux$5365 (pure)
    Root of a mux tree: $procmux$5368 (pure)
    Root of a mux tree: $procmux$5371 (pure)
    Root of a mux tree: $procmux$5374
    Root of a mux tree: $procmux$5377 (pure)
    Root of a mux tree: $procmux$5387 (pure)
    Root of a mux tree: $procmux$5408 (pure)
    Root of a mux tree: $procmux$5415 (pure)
    Root of a mux tree: $procmux$5418
    Root of a mux tree: $procmux$5421 (pure)
    Root of a mux tree: $procmux$5424 (pure)
    Root of a mux tree: $procmux$5427 (pure)
    Root of a mux tree: $procmux$5430 (pure)
    Root of a mux tree: $procmux$5433 (pure)
    Root of a mux tree: $procmux$5436 (pure)
    Root of a mux tree: $procmux$5439 (pure)
    Root of a mux tree: $procmux$5442 (pure)
    Root of a mux tree: $procmux$5445 (pure)
    Root of a mux tree: $procmux$5448 (pure)
    Root of a mux tree: $procmux$5451 (pure)
    Root of a mux tree: $procmux$5454 (pure)
    Root of a mux tree: $procmux$5457 (pure)
    Root of a mux tree: $procmux$5460 (pure)
    Root of a mux tree: $procmux$5463 (pure)
    Root of a mux tree: $procmux$5466 (pure)
    Root of a mux tree: $procmux$5469 (pure)
    Root of a mux tree: $procmux$5472 (pure)
    Root of a mux tree: $procmux$5475 (pure)
    Root of a mux tree: $procmux$5478 (pure)
    Root of a mux tree: $procmux$5481 (pure)
    Root of a mux tree: $procmux$5484 (pure)
    Root of a mux tree: $procmux$5493 (pure)
    Root of a mux tree: $procmux$5530
    Root of a mux tree: $procmux$5539
    Root of a mux tree: $procmux$5551 (pure)
    Root of a mux tree: $procmux$5570 (pure)
    Root of a mux tree: $procmux$5573 (pure)
    Root of a mux tree: $procmux$5607 (pure)
    Root of a mux tree: $procmux$5649 (pure)
    Root of a mux tree: $procmux$5679 (pure)
    Root of a mux tree: $procmux$5687 (pure)
    Root of a mux tree: $procmux$5691 (pure)
    Root of a mux tree: $procmux$5704 (pure)
    Root of a mux tree: $procmux$5742 (pure)
    Root of a mux tree: $procmux$5751 (pure)
    Root of a mux tree: $procmux$5783 (pure)
    Root of a mux tree: $procmux$5791 (pure)
    Root of a mux tree: $procmux$5799 (pure)
    Root of a mux tree: $procmux$5802 (pure)
    Root of a mux tree: $procmux$5811 (pure)
    Root of a mux tree: $procmux$5813 (pure)
    Root of a mux tree: $procmux$5818 (pure)
    Root of a mux tree: $procmux$5826
    Root of a mux tree: $procmux$5830 (pure)
    Root of a mux tree: $procmux$5846 (pure)
    Root of a mux tree: $procmux$5854
    Root of a mux tree: $procmux$5858 (pure)
    Root of a mux tree: $procmux$5877 (pure)
    Root of a mux tree: $procmux$5912 (pure)
    Root of a mux tree: $procmux$5923 (pure)
    Root of a mux tree: $procmux$5964
    Root of a mux tree: $procmux$5966 (pure)
    Root of a mux tree: $procmux$6008 (pure)
    Root of a mux tree: $procmux$6023 (pure)
    Root of a mux tree: $procmux$6067 (pure)
    Root of a mux tree: $procmux$6093 (pure)
    Root of a mux tree: $procmux$6105 (pure)
    Root of a mux tree: $procmux$6143 (pure)
    Root of a mux tree: $procmux$6152
    Root of a mux tree: $procmux$6161 (pure)
    Root of a mux tree: $procmux$6181 (pure)
    Root of a mux tree: $procmux$6201 (pure)
    Root of a mux tree: $procmux$6219 (pure)
    Root of a mux tree: $procmux$6232 (pure)
    Root of a mux tree: $procmux$6237 (pure)
    Root of a mux tree: $procmux$6240 (pure)
    Root of a mux tree: $procmux$6243 (pure)
    Root of a mux tree: $procmux$6249 (pure)
    Root of a mux tree: $procmux$6258 (pure)
    Root of a mux tree: $procmux$6269 (pure)
    Root of a mux tree: $procmux$6279 (pure)
    Root of a mux tree: $procmux$6290 (pure)
    Root of a mux tree: $procmux$6338 (pure)
    Root of a mux tree: $procmux$6341 (pure)
    Root of a mux tree: $procmux$6357 (pure)
    Root of a mux tree: $procmux$6367 (pure)
    Root of a mux tree: $procmux$6373 (pure)
    Root of a mux tree: $procmux$6382 (pure)
    Root of a mux tree: $procmux$6392 (pure)
    Root of a mux tree: $procmux$6410 (pure)
    Root of a mux tree: $procmux$6413 (pure)
    Root of a mux tree: $procmux$6422 (pure)
    Root of a mux tree: $procmux$6425 (pure)
    Root of a mux tree: $procmux$6428 (pure)
    Root of a mux tree: $procmux$6437 (pure)
    Root of a mux tree: $procmux$6440 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2935 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2938 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2941 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2944 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2953 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2959 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2965 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2968 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2974 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2980 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2986 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2992 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2998 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3004 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3016 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3022 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3028 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3034 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3037 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3046 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3052 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3055 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3067 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3073 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3079 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3085 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3091 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3094 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3103 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3109 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3115 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3121 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3139 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3145 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3151 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3157 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3163 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3169 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3175 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3181 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3187 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3193 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3199 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3205 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3211 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3217 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3223 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3229 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3235 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3241 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3247 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3253 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3259 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3271 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3283 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3295 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3304 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3322 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3325 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3331 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3379
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3399
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3417
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3420 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1570$2469 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1583$2473
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1647$2489
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1657$2491
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1667$2493
    Root of a mux tree: $techmap\lm32_cpu.adder.$procmux$7084 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:92$707 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:93$710 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7356 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7359 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:599$127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6530 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6536 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6545 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6554 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6566 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6575 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6584 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6623 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6638 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6653 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6659 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6668 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6674 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6680 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6686 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6710
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6456 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6465 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6478 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6494 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6521 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6524 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2911 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2914 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2917 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2920 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2923 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2926 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2929 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2932 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7102 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7120 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7138 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6713 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6716 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6719 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6725 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6731 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6737 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6743 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6749 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6761 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6770 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6803 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6818 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6830 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6845 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6857 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6866 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6884 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6927 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6971 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6988 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7012 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7035 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7045 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7081 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

21.7.5.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.7.5.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.7.5.27. Executing OPT_RMDFF pass (remove dff with constant values).

21.7.5.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 477 unused cells and 4453 unused wires.

21.7.5.29. Executing OPT_EXPR pass (perform const folding).

21.7.5.30. Finished OPT passes. (There is nothing left to do.)

21.7.6. Executing WREDUCE pass (reducing word size of cells).
Removed top 29 address bits (of 32) from memory init port top.$meminit$\mem_1$top.v:4760$1746 (mem_1).
Removed cell top.$procmux$3426 ($mux).
Removed cell top.$procmux$3429 ($mux).
Removed cell top.$procmux$3435 ($mux).
Removed cell top.$procmux$3438 ($mux).
Removed cell top.$procmux$3444 ($mux).
Removed cell top.$procmux$3447 ($mux).
Removed cell top.$procmux$3453 ($mux).
Removed cell top.$procmux$3456 ($mux).
Removed cell top.$procmux$3462 ($mux).
Removed cell top.$procmux$3465 ($mux).
Removed cell top.$procmux$3474 ($mux).
Removed cell top.$procmux$3477 ($mux).
Removed cell top.$procmux$3486 ($mux).
Removed cell top.$procmux$3489 ($mux).
Removed cell top.$procmux$3495 ($mux).
Removed cell top.$procmux$3498 ($mux).
Removed cell top.$procmux$3504 ($mux).
Removed cell top.$procmux$3507 ($mux).
Removed cell top.$procmux$3513 ($mux).
Removed cell top.$procmux$3516 ($mux).
Removed cell top.$procmux$3522 ($mux).
Removed cell top.$procmux$3525 ($mux).
Removed top 7 bits (of 8) from port B of cell top.$eq$top.v:4363$1590 ($eq).
Removed top 7 bits (of 8) from port B of cell top.$eq$top.v:4377$1599 ($eq).
Removed top 7 bits (of 8) from port B of cell top.$eq$top.v:4391$1608 ($eq).
Removed top 15 bits (of 16) from port B of cell top.$eq$top.v:4517$1667 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4171_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4172_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4173_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4174_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4175_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4176_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4177_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4178_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4179_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4180_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4181_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4182_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4183_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4184_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4185_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$procmux$4186_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4187_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4188_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4189_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4190_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4191_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4192_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4193_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$procmux$4194_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$procmux$4195_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$procmux$4196_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$procmux$4197_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$procmux$4198_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$procmux$4199_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$procmux$4200_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$procmux$4201_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$procmux$4215_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$4227_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$4228_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$procmux$4229_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$procmux$4249_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$procmux$4250_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$procmux$4251_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$procmux$4252_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$procmux$4253_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$procmux$4254_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$procmux$4256_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$procmux$4257_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$procmux$4258_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$procmux$4259_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$procmux$4260_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$procmux$4261_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$procmux$4262_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$procmux$4263_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell top.$procmux$4278 ($pmux).
Removed top 4 bits (of 8) from mux cell top.$procmux$4282 ($mux).
Removed top 4 bits (of 8) from mux cell top.$procmux$4285 ($mux).
Removed top 1 bits (of 4) from port B of cell top.$procmux$4341_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$procmux$4342_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$procmux$4343_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$procmux$4344_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$procmux$4345_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$procmux$4346_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$procmux$4347_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$procmux$4496 ($mux).
Removed top 2 bits (of 5) from port B of cell top.$procmux$4582_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$procmux$4583_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$procmux$4584_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$procmux$4585_CMP0 ($eq).
Removed top 1 bits (of 30) from mux cell top.$procmux$5377 ($mux).
Removed top 2 bits (of 5) from port B of cell top.$procmux$5409_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$procmux$5410_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$procmux$5411_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$procmux$5412_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5506_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$5510 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5522_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$procmux$5563_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5657_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$5660 ($mux).
Removed top 1 bits (of 3) from mux cell top.$procmux$5663 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5667_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$5670 ($mux).
Removed top 1 bits (of 3) from mux cell top.$procmux$5673 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$procmux$5677_CMP0 ($eq).
Removed top 2 bits (of 3) from mux cell top.$procmux$5696 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5726_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$5729 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5733_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$5736 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$procmux$5740_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5767_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5777_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$procmux$5781_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5890_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$5894_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$procmux$5907_CMP0 ($eq).
Removed top 2 bits (of 3) from mux cell top.$procmux$6012 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$6045_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$6048 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$6052_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$6055 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$procmux$6059_CMP0 ($eq).
Removed top 2 bits (of 3) from mux cell top.$procmux$6097 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$6127_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$6130 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$procmux$6134_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$procmux$6137 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$procmux$6141_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$procmux$6195_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$6206_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$procmux$6210_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$procmux$6214_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$techmap\lm32_cpu.$procmux$3381_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$techmap\lm32_cpu.$procmux$3375_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$techmap\lm32_cpu.$procmux$3373_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$techmap\lm32_cpu.$procmux$3371_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell top.$techmap\lm32_cpu.$procmux$3340 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$techmap\lm32_cpu.$procmux$3338_CMP2 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$techmap\lm32_cpu.$procmux$3338_CMP1 ($eq).
Removed cell top.$techmap\lm32_cpu.$procmux$2941 ($mux).
Removed cell top.$techmap\lm32_cpu.$procmux$2938 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$techmap\lm32_cpu.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2262$2689 ($eq).
Removed top 29 bits (of 32) from port A of cell top.$techmap\lm32_cpu.interrupt_unit.$and$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_interrupt.v:154$128 ($and).
Removed top 2 bits (of 32) from mux cell top.$techmap\lm32_cpu.decoder.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:599$127 ($mux).
Removed top 2 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:395$45 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:394$44 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:391$41 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:388$38 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:386$37 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:384$36 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:379$33 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:376$30 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:375$29 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:374$28 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:372$27 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:367$25 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:366$24 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:365$23 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:364$22 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:363$21 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:351$11 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:350$10 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:349$9 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:348$8 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:347$7 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:346$6 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:343$3 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:342$2 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$techmap\lm32_cpu.decoder.$eq$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:341$1 ($eq).
Removed top 31 bits (of 32) from mux cell top.$techmap\lm32_cpu.mc_arithmetic.$procmux$6996 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$techmap\lm32_cpu.mc_arithmetic.$procmux$6915_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$techmap\lm32_cpu.mc_arithmetic.$procmux$6914_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$techmap\lm32_cpu.mc_arithmetic.$procmux$6913_CMP0 ($eq).
Removed top 1 bits (of 33) from port A of cell top.$techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:156$512 ($sub).
Removed top 2 bits (of 4) from port B of cell top.$techmap\lm32_cpu.load_store_unit.$procmux$6903_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$techmap\lm32_cpu.load_store_unit.$procmux$6902_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$techmap\lm32_cpu.load_store_unit.$procmux$6901_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$techmap\lm32_cpu.load_store_unit.$procmux$6894_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$techmap\lm32_cpu.load_store_unit.$procmux$6893_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$techmap\lm32_cpu.load_store_unit.$procmux$6892_CMP0 ($eq).
Removed cell top.$techmap\lm32_cpu.instruction_unit.icache.$procmux$6478 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$techmap\lm32_cpu.instruction_unit.icache.$procmux$6463_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$techmap\lm32_cpu.instruction_unit.icache.$procmux$6462_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP0 ($eq).
Removed top 32 bits (of 33) from port B of cell top.$techmap\lm32_cpu.adder.addsub.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$705 ($sub).
Removed cell top.$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2932 ($mux).
Removed cell top.$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2929 ($mux).
Removed cell top.$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2920 ($mux).
Removed cell top.$techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2917 ($mux).
Removed top 24 bits (of 32) from wire top.$0$memwr$\mem$top.v:4705$776_DATA[31:0]$1683.
Removed top 24 bits (of 32) from wire top.$0$memwr$\mem$top.v:4705$776_EN[31:0]$1684.
Removed top 16 bits (of 32) from wire top.$0$memwr$\mem$top.v:4707$777_DATA[31:0]$1686.
Removed top 8 bits (of 32) from wire top.$0$memwr$\mem$top.v:4709$778_DATA[31:0]$1689.
Removed top 8 bits (of 32) from wire top.$0$memwr$\mem$top.v:4709$778_EN[31:0]$1690.
Removed top 4 bits (of 8) from wire top.$0\interface2_bank_bus_dat_r[7:0].
Removed top 24 bits (of 32) from wire top.$0\usbsoc_usbsoc_bus_wishbone_dat_r[31:0].
Removed top 4 bits (of 8) from wire top.$procmux$4278_Y.
Removed top 4 bits (of 8) from wire top.$procmux$4282_Y.
Removed top 1 bits (of 3) from wire top.$procmux$5510_Y.
Removed top 1 bits (of 3) from wire top.$procmux$5660_Y.
Removed top 1 bits (of 3) from wire top.$procmux$5663_Y.
Removed top 1 bits (of 3) from wire top.$procmux$5670_Y.
Removed top 1 bits (of 3) from wire top.$procmux$5673_Y.
Removed top 2 bits (of 3) from wire top.$procmux$5696_Y.
Removed top 1 bits (of 3) from wire top.$procmux$5729_Y.
Removed top 1 bits (of 3) from wire top.$procmux$5736_Y.
Removed top 2 bits (of 3) from wire top.$procmux$6012_Y.
Removed top 1 bits (of 3) from wire top.$procmux$6048_Y.
Removed top 1 bits (of 3) from wire top.$procmux$6055_Y.
Removed top 2 bits (of 3) from wire top.$procmux$6097_Y.
Removed top 1 bits (of 3) from wire top.$procmux$6130_Y.
Removed top 1 bits (of 3) from wire top.$procmux$6137_Y.
Removed top 3 bits (of 4) from wire top.$techmap\lm32_cpu.$4\eid_x[3:0].
Removed top 32 bits (of 33) from wire top.$techmap\lm32_cpu.adder.addsub.$logic_not$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$704_Y.
Removed top 29 bits (of 32) from wire top.lm32_cpu.interrupt.
Removed top 29 bits (of 32) from wire top.lm32_cpu.interrupt_unit.interrupt.
Removed top 29 bits (of 32) from wire top.lm32_cpu.interrupt_unit.ip.
Removed top 1 bits (of 30) from wire top.shared_adr.
Removed top 4 bits (of 30) from wire top.usbsoc_spiflash_bus_adr.
Removed top 4 bits (of 30) from wire top.usbsoc_usbsoc_bus_wishbone_adr.
Removed top 4 bits (of 30) from wire top.usbsoc_usbsoc_sram_bus_adr.

21.7.7. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $add$top.v:2232$935 ($add).
  creating $macc model for $add$top.v:2241$938 ($add).
  creating $macc model for $add$top.v:2298$964 ($add).
  creating $macc model for $add$top.v:2307$967 ($add).
  creating $macc model for $add$top.v:2364$993 ($add).
  creating $macc model for $add$top.v:2373$996 ($add).
  creating $macc model for $add$top.v:2430$1022 ($add).
  creating $macc model for $add$top.v:2439$1025 ($add).
  creating $macc model for $add$top.v:2496$1051 ($add).
  creating $macc model for $add$top.v:2505$1054 ($add).
  creating $macc model for $add$top.v:3159$1472 ($add).
  creating $macc model for $add$top.v:3180$1480 ($add).
  creating $macc model for $add$top.v:3194$1487 ($add).
  creating $macc model for $add$top.v:3210$1490 ($add).
  creating $macc model for $add$top.v:3223$1494 ($add).
  creating $macc model for $add$top.v:3242$1497 ($add).
  creating $macc model for $add$top.v:3272$1505 ($add).
  creating $macc model for $add$top.v:3275$1506 ($add).
  creating $macc model for $add$top.v:3279$1511 ($add).
  creating $macc model for $add$top.v:3294$1516 ($add).
  creating $macc model for $add$top.v:3297$1517 ($add).
  creating $macc model for $add$top.v:3301$1522 ($add).
  creating $macc model for $sub$top.v:3149$1469 ($sub).
  creating $macc model for $sub$top.v:3283$1512 ($sub).
  creating $macc model for $sub$top.v:3305$1523 ($sub).
  creating $macc model for $sub$top.v:3328$1525 ($sub).
  creating $macc model for $sub$top.v:3651$1574 ($sub).
  creating $macc model for $techmap\lm32_cpu.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1573$2470 ($add).
  creating $macc model for $techmap\lm32_cpu.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2549$2707 ($add).
  creating $macc model for $add$top.v:3380$1543 ($add).
  creating $macc model for $add$top.v:3356$1530 ($add).
  creating $macc model for $techmap\lm32_cpu.adder.addsub.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:89$701 ($add).
  creating $macc model for $techmap\lm32_cpu.adder.addsub.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:89$702 ($add).
  creating $macc model for $techmap\lm32_cpu.adder.addsub.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$703 ($sub).
  creating $macc model for $techmap\lm32_cpu.adder.addsub.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$705 ($sub).
  creating $macc model for $techmap\lm32_cpu.instruction_unit.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:565$2815 ($add).
  creating $macc model for $techmap\lm32_cpu.instruction_unit.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:791$2832 ($add).
  creating $macc model for $techmap\lm32_cpu.instruction_unit.icache.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:507$2887 ($add).
  creating $macc model for $add$top.v:4273$1577 ($add).
  creating $macc model for $techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:421$2869 ($sub).
  creating $macc model for $techmap\lm32_cpu.mc_arithmetic.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:278$536 ($add).
  creating $macc model for $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:156$512 ($sub).
  creating $macc model for $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528 ($sub).
  merging $macc model for $techmap\lm32_cpu.adder.addsub.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$703 into $techmap\lm32_cpu.adder.addsub.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$705.
  merging $macc model for $techmap\lm32_cpu.adder.addsub.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:89$701 into $techmap\lm32_cpu.adder.addsub.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:89$702.
  creating $alu model for $macc $techmap\lm32_cpu.mc_arithmetic.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:278$536.
  creating $alu model for $macc $techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:421$2869.
  creating $alu model for $macc $add$top.v:4273$1577.
  creating $alu model for $macc $techmap\lm32_cpu.instruction_unit.icache.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:507$2887.
  creating $alu model for $macc $techmap\lm32_cpu.instruction_unit.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:791$2832.
  creating $alu model for $macc $techmap\lm32_cpu.instruction_unit.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:565$2815.
  creating $alu model for $macc $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:156$512.
  creating $alu model for $macc $techmap\lm32_cpu.adder.addsub.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:89$702.
  creating $alu model for $macc $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528.
  creating $alu model for $macc $add$top.v:3356$1530.
  creating $alu model for $macc $add$top.v:3380$1543.
  creating $alu model for $macc $techmap\lm32_cpu.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2549$2707.
  creating $alu model for $macc $techmap\lm32_cpu.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1573$2470.
  creating $alu model for $macc $sub$top.v:3651$1574.
  creating $alu model for $macc $sub$top.v:3328$1525.
  creating $alu model for $macc $sub$top.v:3305$1523.
  creating $alu model for $macc $sub$top.v:3283$1512.
  creating $alu model for $macc $sub$top.v:3149$1469.
  creating $alu model for $macc $add$top.v:3301$1522.
  creating $alu model for $macc $add$top.v:3297$1517.
  creating $alu model for $macc $add$top.v:3294$1516.
  creating $alu model for $macc $add$top.v:3279$1511.
  creating $alu model for $macc $add$top.v:3275$1506.
  creating $alu model for $macc $add$top.v:3272$1505.
  creating $alu model for $macc $add$top.v:3242$1497.
  creating $alu model for $macc $add$top.v:3223$1494.
  creating $alu model for $macc $add$top.v:3210$1490.
  creating $alu model for $macc $add$top.v:3194$1487.
  creating $alu model for $macc $add$top.v:3180$1480.
  creating $alu model for $macc $add$top.v:3159$1472.
  creating $alu model for $macc $add$top.v:2505$1054.
  creating $alu model for $macc $add$top.v:2496$1051.
  creating $alu model for $macc $add$top.v:2439$1025.
  creating $alu model for $macc $add$top.v:2430$1022.
  creating $alu model for $macc $add$top.v:2373$996.
  creating $alu model for $macc $add$top.v:2364$993.
  creating $alu model for $macc $add$top.v:2307$967.
  creating $alu model for $macc $add$top.v:2298$964.
  creating $alu model for $macc $add$top.v:2241$938.
  creating $alu model for $macc $add$top.v:2232$935.
  creating $macc cell for $techmap\lm32_cpu.adder.addsub.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$705: $auto$alumacc.cc:354:replace_macc$7881
  creating $alu cell for $add$top.v:2232$935: $auto$alumacc.cc:474:replace_alu$7882
  creating $alu cell for $add$top.v:2241$938: $auto$alumacc.cc:474:replace_alu$7885
  creating $alu cell for $add$top.v:2298$964: $auto$alumacc.cc:474:replace_alu$7888
  creating $alu cell for $add$top.v:2307$967: $auto$alumacc.cc:474:replace_alu$7891
  creating $alu cell for $add$top.v:2364$993: $auto$alumacc.cc:474:replace_alu$7894
  creating $alu cell for $add$top.v:2373$996: $auto$alumacc.cc:474:replace_alu$7897
  creating $alu cell for $add$top.v:2430$1022: $auto$alumacc.cc:474:replace_alu$7900
  creating $alu cell for $add$top.v:2439$1025: $auto$alumacc.cc:474:replace_alu$7903
  creating $alu cell for $add$top.v:2496$1051: $auto$alumacc.cc:474:replace_alu$7906
  creating $alu cell for $add$top.v:2505$1054: $auto$alumacc.cc:474:replace_alu$7909
  creating $alu cell for $add$top.v:3159$1472: $auto$alumacc.cc:474:replace_alu$7912
  creating $alu cell for $add$top.v:3180$1480: $auto$alumacc.cc:474:replace_alu$7915
  creating $alu cell for $add$top.v:3194$1487: $auto$alumacc.cc:474:replace_alu$7918
  creating $alu cell for $add$top.v:3210$1490: $auto$alumacc.cc:474:replace_alu$7921
  creating $alu cell for $add$top.v:3223$1494: $auto$alumacc.cc:474:replace_alu$7924
  creating $alu cell for $add$top.v:3242$1497: $auto$alumacc.cc:474:replace_alu$7927
  creating $alu cell for $add$top.v:3272$1505: $auto$alumacc.cc:474:replace_alu$7930
  creating $alu cell for $add$top.v:3275$1506: $auto$alumacc.cc:474:replace_alu$7933
  creating $alu cell for $add$top.v:3279$1511: $auto$alumacc.cc:474:replace_alu$7936
  creating $alu cell for $add$top.v:3294$1516: $auto$alumacc.cc:474:replace_alu$7939
  creating $alu cell for $add$top.v:3297$1517: $auto$alumacc.cc:474:replace_alu$7942
  creating $alu cell for $add$top.v:3301$1522: $auto$alumacc.cc:474:replace_alu$7945
  creating $alu cell for $sub$top.v:3149$1469: $auto$alumacc.cc:474:replace_alu$7948
  creating $alu cell for $sub$top.v:3283$1512: $auto$alumacc.cc:474:replace_alu$7951
  creating $alu cell for $sub$top.v:3305$1523: $auto$alumacc.cc:474:replace_alu$7954
  creating $alu cell for $sub$top.v:3328$1525: $auto$alumacc.cc:474:replace_alu$7957
  creating $alu cell for $sub$top.v:3651$1574: $auto$alumacc.cc:474:replace_alu$7960
  creating $alu cell for $techmap\lm32_cpu.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1573$2470: $auto$alumacc.cc:474:replace_alu$7963
  creating $alu cell for $techmap\lm32_cpu.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:2549$2707: $auto$alumacc.cc:474:replace_alu$7966
  creating $alu cell for $add$top.v:3380$1543: $auto$alumacc.cc:474:replace_alu$7969
  creating $alu cell for $add$top.v:3356$1530: $auto$alumacc.cc:474:replace_alu$7972
  creating $alu cell for $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:250$528: $auto$alumacc.cc:474:replace_alu$7975
  creating $alu cell for $techmap\lm32_cpu.adder.addsub.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:89$702: $auto$alumacc.cc:474:replace_alu$7978
  creating $alu cell for $techmap\lm32_cpu.mc_arithmetic.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:156$512: $auto$alumacc.cc:474:replace_alu$7981
  creating $alu cell for $techmap\lm32_cpu.instruction_unit.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:565$2815: $auto$alumacc.cc:474:replace_alu$7984
  creating $alu cell for $techmap\lm32_cpu.instruction_unit.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_instruction_unit.v:791$2832: $auto$alumacc.cc:474:replace_alu$7987
  creating $alu cell for $techmap\lm32_cpu.instruction_unit.icache.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:507$2887: $auto$alumacc.cc:474:replace_alu$7990
  creating $alu cell for $add$top.v:4273$1577: $auto$alumacc.cc:474:replace_alu$7993
  creating $alu cell for $techmap\lm32_cpu.instruction_unit.icache.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:421$2869: $auto$alumacc.cc:474:replace_alu$7996
  creating $alu cell for $techmap\lm32_cpu.mc_arithmetic.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v:278$536: $auto$alumacc.cc:474:replace_alu$7999
  created 40 $alu and 1 $macc cells.

21.7.8. Executing SHARE pass (SAT-based resource sharing).
Found 13 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$memrd$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:113$2889 ($memrd):
    Found 3 activation_patterns using ctrl signal { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f $techmap\lm32_cpu.instruction_unit.icache.$procmux$6454_CMP \lm32_cpu.iflush }.
    No candidates found.
  Analyzing resource sharing options for $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$memrd$\mem$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_ram.v:113$2900 ($memrd):
    Found 1 activation_patterns using ctrl signal { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f \lm32_cpu.instruction_unit.icache.way_match }.
    No candidates found.
  Analyzing resource sharing options for $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1507$2420 ($memrd):
    Found 3 activation_patterns using ctrl signal { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f \lm32_cpu.load_store_unit.stall_x $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.raw_x_1 \lm32_cpu.raw_m_1 \lm32_cpu.raw_w_1 $techmap\lm32_cpu.$procmux$3381_CMP }.
    Found 1 candidates: $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419
    Analyzing resource sharing with $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419 ($memrd):
      Found 5 activation_patterns using ctrl signal { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f \lm32_cpu.load_store_unit.stall_x \lm32_cpu.mc_arithmetic.shift_left_d \lm32_cpu.mc_arithmetic.shift_right_d $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.branch_reg_d \lm32_cpu.d_result_sel_0_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_m_0 \lm32_cpu.raw_w_0 }.
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1507$2420: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.raw_x_1 \lm32_cpu.raw_m_1 \lm32_cpu.raw_w_1 $techmap\lm32_cpu.$procmux$3381_CMP } = 7'0010001
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1507$2420: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.load_store_unit.stall_x \lm32_cpu.raw_x_1 \lm32_cpu.raw_m_1 \lm32_cpu.raw_w_1 $techmap\lm32_cpu.$procmux$3381_CMP } = 6'000001
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1507$2420: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.load_store_unit.stall_x \lm32_cpu.raw_x_1 \lm32_cpu.raw_m_1 \lm32_cpu.raw_w_1 } = 5'00000
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.load_store_unit.stall_x \lm32_cpu.branch_reg_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_m_0 \lm32_cpu.raw_w_0 } = 6'001000
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.load_store_unit.stall_x \lm32_cpu.d_result_sel_0_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_m_0 \lm32_cpu.raw_w_0 } = 6'000000
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f \lm32_cpu.mc_arithmetic.shift_left_d \lm32_cpu.mc_arithmetic.shift_right_d $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.d_result_sel_0_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_m_0 \lm32_cpu.raw_w_0 } = 9'001010000
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f \lm32_cpu.mc_arithmetic.shift_right_d $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.d_result_sel_0_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_m_0 \lm32_cpu.raw_w_0 } = 8'00110000
      Activation pattern for cell $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.d_result_sel_0_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_m_0 \lm32_cpu.raw_w_0 } = 7'0010000
      Size of SAT problem: 145 cells, 1189 variables, 3048 clauses
      According to the SAT solver this pair of cells can not be shared.
      Model from SAT solver: { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f \lm32_cpu.load_store_unit.stall_x \lm32_cpu.mc_arithmetic.shift_left_d \lm32_cpu.mc_arithmetic.shift_right_d $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.branch_reg_d \lm32_cpu.d_result_sel_0_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_x_1 \lm32_cpu.raw_m_0 \lm32_cpu.raw_m_1 \lm32_cpu.raw_w_0 \lm32_cpu.raw_w_1 $techmap\lm32_cpu.$procmux$3381_CMP } = 15'010001000000000
  Analyzing resource sharing options for $techmap\lm32_cpu.$memrd$\registers$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1506$2419 ($memrd):
    Found 5 activation_patterns using ctrl signal { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.instruction_unit.icache.stall_f \lm32_cpu.load_store_unit.stall_x \lm32_cpu.mc_arithmetic.shift_left_d \lm32_cpu.mc_arithmetic.shift_right_d $techmap\lm32_cpu.mc_arithmetic.$procmux$6925_CMP \lm32_cpu.branch_reg_d \lm32_cpu.d_result_sel_0_d \lm32_cpu.raw_x_0 \lm32_cpu.raw_m_0 \lm32_cpu.raw_w_0 }.
    No candidates found.
  Analyzing resource sharing options for $memrd$\storage_6$top.v:4881$1745 ($memrd):
    Found 1 activation_patterns using ctrl signal \usb_endpointin2_asyncfifo2_re.
    No candidates found.
  Analyzing resource sharing options for $memrd$\storage_5$top.v:4865$1738 ($memrd):
    Found 1 activation_patterns using ctrl signal \usb_endpointout1_outbuf_asyncfifo1_re.
    No candidates found.
  Analyzing resource sharing options for $memrd$\storage_4$top.v:4849$1731 ($memrd):
    Found 1 activation_patterns using ctrl signal \usb_endpointin1_asyncfifo1_re.
    No candidates found.
  Analyzing resource sharing options for $memrd$\storage_3$top.v:4833$1724 ($memrd):
    Found 1 activation_patterns using ctrl signal \usb_endpointin0_asyncfifo0_re.
    No candidates found.
  Analyzing resource sharing options for $memrd$\storage_2$top.v:4817$1717 ($memrd):
    Found 1 activation_patterns using ctrl signal \usb_endpointout0_outbuf_asyncfifo0_re.
    No candidates found.
  Analyzing resource sharing options for $memrd$\storage_1$top.v:4745$1708 ($memrd):
    Found 1 activation_patterns using ctrl signal \usbsoc_usbsoc_uart_rx_fifo_do_read.
    No candidates found.
  Analyzing resource sharing options for $memrd$\storage$top.v:4728$1701 ($memrd):
    Found 1 activation_patterns using ctrl signal \usbsoc_usbsoc_uart_tx_fifo_do_read.
    No candidates found.
  Analyzing resource sharing options for $memrd$\mem_1$top.v:4757$1710 ($memrd):
    Found 1 activation_patterns using ctrl signal { \sel_r \sys_rst }.
    No candidates found.
  Analyzing resource sharing options for $memrd$\mem$top.v:4715$1694 ($memrd):
    Found 2 activation_patterns using ctrl signal { \lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.reset \lm32_cpu.load_store_unit.d_cyc_o \lm32_cpu.instruction_unit.i_cyc_o \lm32_cpu.I_ACK_I \lm32_cpu.D_ACK_I \done }.
    No candidates found.

21.7.9. Executing OPT pass (performing simple optimizations).

21.7.9.1. Executing OPT_EXPR pass (perform const folding).

21.7.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
  Cell `$procdff$7446' is identical to cell `$procdff$7436'.
    Redirecting output \Q: $memwr$\storage_4$top.v:4840$784_DATA = $memwr$\storage_6$top.v:4872$786_DATA
    Removing $dff cell `$procdff$7446' from module `\top'.
  Cell `$procdff$7451' is identical to cell `$procdff$7436'.
    Redirecting output \Q: $memwr$\storage_3$top.v:4824$783_DATA = $memwr$\storage_6$top.v:4872$786_DATA
    Removing $dff cell `$procdff$7451' from module `\top'.
  Cell `$procdff$7470' is identical to cell `$procdff$7469'.
    Redirecting output \Q: $memwr$\mem$top.v:4705$776_ADDR = \memadr
    Removing $dff cell `$procdff$7470' from module `\top'.
  Cell `$procdff$7473' is identical to cell `$procdff$7469'.
    Redirecting output \Q: $memwr$\mem$top.v:4707$777_ADDR = \memadr
    Removing $dff cell `$procdff$7473' from module `\top'.
  Cell `$procdff$7476' is identical to cell `$procdff$7469'.
    Redirecting output \Q: $memwr$\mem$top.v:4709$778_ADDR = \memadr
    Removing $dff cell `$procdff$7476' from module `\top'.
  Cell `$procdff$7479' is identical to cell `$procdff$7469'.
    Redirecting output \Q: $memwr$\mem$top.v:4711$779_ADDR = \memadr
    Removing $dff cell `$procdff$7479' from module `\top'.
  Cell `$procmux$4171_CMP0' is identical to cell `$eq$top.v:2873$1417'.
    Redirecting output \Y: $procmux$4171_CMP = $eq$top.v:2873$1417_Y
    Removing $eq cell `$procmux$4171_CMP0' from module `\top'.
  Cell `$procmux$4172_CMP0' is identical to cell `$eq$top.v:2871$1414'.
    Redirecting output \Y: $procmux$4172_CMP = $eq$top.v:2871$1414_Y
    Removing $eq cell `$procmux$4172_CMP0' from module `\top'.
  Cell `$procmux$4173_CMP0' is identical to cell `$eq$top.v:2869$1411'.
    Redirecting output \Y: $procmux$4173_CMP = $eq$top.v:2869$1411_Y
    Removing $eq cell `$procmux$4173_CMP0' from module `\top'.
  Cell `$procmux$4175_CMP0' is identical to cell `$eq$top.v:2865$1405'.
    Redirecting output \Y: $procmux$4175_CMP = $eq$top.v:2865$1405_Y
    Removing $eq cell `$procmux$4175_CMP0' from module `\top'.
  Cell `$procmux$4176_CMP0' is identical to cell `$eq$top.v:2863$1402'.
    Redirecting output \Y: $procmux$4176_CMP = $eq$top.v:2863$1402_Y
    Removing $eq cell `$procmux$4176_CMP0' from module `\top'.
  Cell `$procmux$4179_CMP0' is identical to cell `$eq$top.v:2857$1393'.
    Redirecting output \Y: $procmux$4179_CMP = $eq$top.v:2857$1393_Y
    Removing $eq cell `$procmux$4179_CMP0' from module `\top'.
  Cell `$procmux$4180_CMP0' is identical to cell `$eq$top.v:2855$1390'.
    Redirecting output \Y: $procmux$4180_CMP = $eq$top.v:2855$1390_Y
    Removing $eq cell `$procmux$4180_CMP0' from module `\top'.
  Cell `$procmux$4181_CMP0' is identical to cell `$eq$top.v:2853$1387'.
    Redirecting output \Y: $procmux$4181_CMP = $eq$top.v:2853$1387_Y
    Removing $eq cell `$procmux$4181_CMP0' from module `\top'.
  Cell `$procmux$4183_CMP0' is identical to cell `$eq$top.v:2849$1381'.
    Redirecting output \Y: $procmux$4183_CMP = $eq$top.v:2849$1381_Y
    Removing $eq cell `$procmux$4183_CMP0' from module `\top'.
  Cell `$procmux$4184_CMP0' is identical to cell `$eq$top.v:2847$1378'.
    Redirecting output \Y: $procmux$4184_CMP = $eq$top.v:2847$1378_Y
    Removing $eq cell `$procmux$4184_CMP0' from module `\top'.
  Cell `$procmux$4187_CMP0' is identical to cell `$eq$top.v:2841$1369'.
    Redirecting output \Y: $procmux$4187_CMP = $eq$top.v:2841$1369_Y
    Removing $eq cell `$procmux$4187_CMP0' from module `\top'.
  Cell `$procmux$4188_CMP0' is identical to cell `$eq$top.v:2839$1366'.
    Redirecting output \Y: $procmux$4188_CMP = $eq$top.v:2839$1366_Y
    Removing $eq cell `$procmux$4188_CMP0' from module `\top'.
  Cell `$procmux$4189_CMP0' is identical to cell `$eq$top.v:2837$1363'.
    Redirecting output \Y: $procmux$4189_CMP = $eq$top.v:2837$1363_Y
    Removing $eq cell `$procmux$4189_CMP0' from module `\top'.
  Cell `$procmux$4191_CMP0' is identical to cell `$eq$top.v:2833$1357'.
    Redirecting output \Y: $procmux$4191_CMP = $eq$top.v:2833$1357_Y
    Removing $eq cell `$procmux$4191_CMP0' from module `\top'.
  Cell `$procmux$4192_CMP0' is identical to cell `$eq$top.v:2831$1354'.
    Redirecting output \Y: $procmux$4192_CMP = $eq$top.v:2831$1354_Y
    Removing $eq cell `$procmux$4192_CMP0' from module `\top'.
  Cell `$procmux$4195_CMP0' is identical to cell `$eq$top.v:2825$1345'.
    Redirecting output \Y: $procmux$4195_CMP = $eq$top.v:2825$1345_Y
    Removing $eq cell `$procmux$4195_CMP0' from module `\top'.
  Cell `$procmux$4196_CMP0' is identical to cell `$eq$top.v:2823$1342'.
    Redirecting output \Y: $procmux$4196_CMP = $eq$top.v:2823$1342_Y
    Removing $eq cell `$procmux$4196_CMP0' from module `\top'.
  Cell `$procmux$4197_CMP0' is identical to cell `$eq$top.v:2821$1339'.
    Redirecting output \Y: $procmux$4197_CMP = $eq$top.v:2821$1339_Y
    Removing $eq cell `$procmux$4197_CMP0' from module `\top'.
  Cell `$procmux$4199_CMP0' is identical to cell `$eq$top.v:2817$1333'.
    Redirecting output \Y: $procmux$4199_CMP = $eq$top.v:2817$1333_Y
    Removing $eq cell `$procmux$4199_CMP0' from module `\top'.
  Cell `$procmux$4200_CMP0' is identical to cell `$eq$top.v:2815$1330'.
    Redirecting output \Y: $procmux$4200_CMP = $eq$top.v:2815$1330_Y
    Removing $eq cell `$procmux$4200_CMP0' from module `\top'.
  Cell `$procmux$4215_CMP0' is identical to cell `$eq$top.v:2799$1314'.
    Redirecting output \Y: $procmux$4215_CMP = $eq$top.v:2799$1314_Y
    Removing $eq cell `$procmux$4215_CMP0' from module `\top'.
  Cell `$procmux$4249_CMP0' is identical to cell `$eq$top.v:2761$1285'.
    Redirecting output \Y: $procmux$4249_CMP = $eq$top.v:2761$1285_Y
    Removing $eq cell `$procmux$4249_CMP0' from module `\top'.
  Cell `$procmux$4256_CMP0' is identical to cell `$eq$top.v:2747$1264'.
    Redirecting output \Y: $procmux$4256_CMP = $eq$top.v:2747$1264_Y
    Removing $eq cell `$procmux$4256_CMP0' from module `\top'.
  Cell `$procmux$4257_CMP0' is identical to cell `$eq$top.v:2745$1261'.
    Redirecting output \Y: $procmux$4257_CMP = $eq$top.v:2745$1261_Y
    Removing $eq cell `$procmux$4257_CMP0' from module `\top'.
  Cell `$procmux$4258_CMP0' is identical to cell `$eq$top.v:2743$1258'.
    Redirecting output \Y: $procmux$4258_CMP = $eq$top.v:2743$1258_Y
    Removing $eq cell `$procmux$4258_CMP0' from module `\top'.
  Cell `$procmux$4259_CMP0' is identical to cell `$eq$top.v:2741$1255'.
    Redirecting output \Y: $procmux$4259_CMP = $eq$top.v:2741$1255_Y
    Removing $eq cell `$procmux$4259_CMP0' from module `\top'.
  Cell `$procmux$4260_CMP0' is identical to cell `$eq$top.v:2739$1252'.
    Redirecting output \Y: $procmux$4260_CMP = $eq$top.v:2739$1252_Y
    Removing $eq cell `$procmux$4260_CMP0' from module `\top'.
  Cell `$procmux$4261_CMP0' is identical to cell `$eq$top.v:2737$1249'.
    Redirecting output \Y: $procmux$4261_CMP = $eq$top.v:2737$1249_Y
    Removing $eq cell `$procmux$4261_CMP0' from module `\top'.
  Cell `$procmux$4262_CMP0' is identical to cell `$eq$top.v:2735$1246'.
    Redirecting output \Y: $procmux$4262_CMP = $eq$top.v:2735$1246_Y
    Removing $eq cell `$procmux$4262_CMP0' from module `\top'.
  Cell `$procmux$4263_CMP0' is identical to cell `$eq$top.v:2733$1243'.
    Redirecting output \Y: $procmux$4263_CMP = $eq$top.v:2733$1243_Y
    Removing $eq cell `$procmux$4263_CMP0' from module `\top'.
  Cell `$procmux$4344_CMP0' is identical to cell `$eq$top.v:2582$1103'.
    Redirecting output \Y: $procmux$4344_CMP = $eq$top.v:2582$1103_Y
    Removing $eq cell `$procmux$4344_CMP0' from module `\top'.
  Cell `$procmux$4345_CMP0' is identical to cell `$eq$top.v:2580$1100'.
    Redirecting output \Y: $procmux$4345_CMP = $eq$top.v:2580$1100_Y
    Removing $eq cell `$procmux$4345_CMP0' from module `\top'.
  Cell `$procmux$4346_CMP0' is identical to cell `$eq$top.v:2578$1097'.
    Redirecting output \Y: $procmux$4346_CMP = $eq$top.v:2578$1097_Y
    Removing $eq cell `$procmux$4346_CMP0' from module `\top'.
  Cell `$procmux$4347_CMP0' is identical to cell `$eq$top.v:2576$1094'.
    Redirecting output \Y: $procmux$4347_CMP = $eq$top.v:2576$1094_Y
    Removing $eq cell `$procmux$4347_CMP0' from module `\top'.
Removed a total of 40 cells.

21.7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$3423 (pure)
    Root of a mux tree: $procmux$3432 (pure)
    Root of a mux tree: $procmux$3441 (pure)
    Root of a mux tree: $procmux$3450 (pure)
    Root of a mux tree: $procmux$3459 (pure)
    Root of a mux tree: $procmux$3468 (pure)
    Root of a mux tree: $procmux$3471 (pure)
    Root of a mux tree: $procmux$3480 (pure)
    Root of a mux tree: $procmux$3483 (pure)
    Root of a mux tree: $procmux$3492 (pure)
    Root of a mux tree: $procmux$3501 (pure)
    Root of a mux tree: $procmux$3510 (pure)
    Root of a mux tree: $procmux$3519 (pure)
    Root of a mux tree: $procmux$3531 (pure)
    Root of a mux tree: $procmux$3540 (pure)
    Root of a mux tree: $procmux$3549 (pure)
    Root of a mux tree: $procmux$3558 (pure)
    Root of a mux tree: $procmux$3567 (pure)
    Root of a mux tree: $procmux$3576 (pure)
    Root of a mux tree: $procmux$3585 (pure)
    Root of a mux tree: $procmux$3594 (pure)
    Root of a mux tree: $procmux$3603 (pure)
    Root of a mux tree: $procmux$3612 (pure)
    Root of a mux tree: $procmux$3621 (pure)
    Root of a mux tree: $procmux$3630 (pure)
    Root of a mux tree: $procmux$3639 (pure)
    Root of a mux tree: $procmux$3648 (pure)
    Root of a mux tree: $procmux$3657 (pure)
    Root of a mux tree: $procmux$3666 (pure)
    Root of a mux tree: $procmux$3755 (pure)
    Root of a mux tree: $procmux$3773 (pure)
    Root of a mux tree: $procmux$3863 (pure)
    Root of a mux tree: $procmux$3869 (pure)
    Root of a mux tree: $procmux$3872 (pure)
    Root of a mux tree: $procmux$3878 (pure)
    Root of a mux tree: $procmux$3881 (pure)
    Root of a mux tree: $procmux$3887 (pure)
    Root of a mux tree: $procmux$3890 (pure)
    Root of a mux tree: $procmux$3896 (pure)
    Root of a mux tree: $procmux$3902 (pure)
    Root of a mux tree: $procmux$3908 (pure)
    Root of a mux tree: $procmux$3914 (pure)
    Root of a mux tree: $procmux$3920 (pure)
    Root of a mux tree: $procmux$3926 (pure)
    Root of a mux tree: $procmux$3932 (pure)
    Root of a mux tree: $procmux$3941 (pure)
    Root of a mux tree: $procmux$3950 (pure)
    Root of a mux tree: $procmux$3959 (pure)
    Root of a mux tree: $procmux$3968 (pure)
    Root of a mux tree: $procmux$3977 (pure)
    Root of a mux tree: $procmux$3986 (pure)
    Root of a mux tree: $procmux$3995 (pure)
    Root of a mux tree: $procmux$4004 (pure)
    Root of a mux tree: $procmux$4010 (pure)
    Root of a mux tree: $procmux$4022 (pure)
    Root of a mux tree: $procmux$4028 (pure)
    Root of a mux tree: $procmux$4034 (pure)
    Root of a mux tree: $procmux$4043 (pure)
    Root of a mux tree: $procmux$4049 (pure)
    Root of a mux tree: $procmux$4064 (pure)
    Root of a mux tree: $procmux$4070 (pure)
    Root of a mux tree: $procmux$4076 (pure)
    Root of a mux tree: $procmux$4082 (pure)
    Root of a mux tree: $procmux$4088 (pure)
    Root of a mux tree: $procmux$4094 (pure)
    Root of a mux tree: $procmux$4100 (pure)
    Root of a mux tree: $procmux$4106 (pure)
    Root of a mux tree: $procmux$4112 (pure)
    Root of a mux tree: $procmux$4118 (pure)
    Root of a mux tree: $procmux$4124 (pure)
    Root of a mux tree: $procmux$4130 (pure)
    Root of a mux tree: $procmux$4136 (pure)
    Root of a mux tree: $procmux$4145 (pure)
    Root of a mux tree: $procmux$4151 (pure)
    Root of a mux tree: $procmux$4157 (pure)
    Root of a mux tree: $procmux$4206 (pure)
    Root of a mux tree: $procmux$4220 (pure)
    Root of a mux tree: $procmux$4234 (pure)
    Root of a mux tree: $procmux$4268 (pure)
    Root of a mux tree: $procmux$4285 (pure)
    Root of a mux tree: $procmux$4329 (pure)
    Root of a mux tree: $procmux$4332 (pure)
    Root of a mux tree: $procmux$4352 (pure)
    Root of a mux tree: $procmux$4355 (pure)
    Root of a mux tree: $procmux$4358 (pure)
    Root of a mux tree: $procmux$4361 (pure)
    Root of a mux tree: $procmux$4373 (pure)
    Root of a mux tree: $procmux$4376 (pure)
    Root of a mux tree: $procmux$4388 (pure)
    Root of a mux tree: $procmux$4391 (pure)
    Root of a mux tree: $procmux$4403 (pure)
    Root of a mux tree: $procmux$4406 (pure)
    Root of a mux tree: $procmux$4418 (pure)
    Root of a mux tree: $procmux$4421 (pure)
    Root of a mux tree: $procmux$4439 (pure)
    Root of a mux tree: $procmux$4451 (pure)
    Root of a mux tree: $procmux$4457 (pure)
    Root of a mux tree: $procmux$4460 (pure)
    Root of a mux tree: $procmux$4478 (pure)
    Root of a mux tree: $procmux$4493 (pure)
    Root of a mux tree: $procmux$4496 (pure)
    Root of a mux tree: $procmux$4499 (pure)
    Root of a mux tree: $procmux$4502 (pure)
    Root of a mux tree: $procmux$4508 (pure)
    Root of a mux tree: $procmux$4514 (pure)
    Root of a mux tree: $procmux$4523 (pure)
    Root of a mux tree: $procmux$4541 (pure)
    Root of a mux tree: $procmux$4550 (pure)
    Root of a mux tree: $procmux$4559 (pure)
    Root of a mux tree: $procmux$4568 (pure)
    Root of a mux tree: $procmux$4577 (pure)
    Root of a mux tree: $procmux$4590 (pure)
    Root of a mux tree: $procmux$4596 (pure)
    Root of a mux tree: $procmux$4605 (pure)
    Root of a mux tree: $procmux$4614 (pure)
    Root of a mux tree: $procmux$4617 (pure)
    Root of a mux tree: $procmux$4623 (pure)
    Root of a mux tree: $procmux$4632 (pure)
    Root of a mux tree: $procmux$4641 (pure)
    Root of a mux tree: $procmux$4650 (pure)
    Root of a mux tree: $procmux$4659 (pure)
    Root of a mux tree: $procmux$4668 (pure)
    Root of a mux tree: $procmux$4674 (pure)
    Root of a mux tree: $procmux$4683 (pure)
    Root of a mux tree: $procmux$4692 (pure)
    Root of a mux tree: $procmux$4701 (pure)
    Root of a mux tree: $procmux$4710 (pure)
    Root of a mux tree: $procmux$4719 (pure)
    Root of a mux tree: $procmux$4728 (pure)
    Root of a mux tree: $procmux$4738 (pure)
    Root of a mux tree: $procmux$4744 (pure)
    Root of a mux tree: $procmux$4753 (pure)
    Root of a mux tree: $procmux$4762 (pure)
    Root of a mux tree: $procmux$4782 (pure)
    Root of a mux tree: $procmux$4791 (pure)
    Root of a mux tree: $procmux$4800 (pure)
    Root of a mux tree: $procmux$4809 (pure)
    Root of a mux tree: $procmux$4821 (pure)
    Root of a mux tree: $procmux$4827 (pure)
    Root of a mux tree: $procmux$4836 (pure)
    Root of a mux tree: $procmux$4845 (pure)
    Root of a mux tree: $procmux$4848 (pure)
    Root of a mux tree: $procmux$4854 (pure)
    Root of a mux tree: $procmux$4863 (pure)
    Root of a mux tree: $procmux$4872 (pure)
    Root of a mux tree: $procmux$4881 (pure)
    Root of a mux tree: $procmux$4890 (pure)
    Root of a mux tree: $procmux$4903 (pure)
    Root of a mux tree: $procmux$4909 (pure)
    Root of a mux tree: $procmux$4918 (pure)
    Root of a mux tree: $procmux$4927 (pure)
    Root of a mux tree: $procmux$4933 (pure)
    Root of a mux tree: $procmux$4945 (pure)
    Root of a mux tree: $procmux$4951 (pure)
    Root of a mux tree: $procmux$4957 (pure)
    Root of a mux tree: $procmux$4963 (pure)
    Root of a mux tree: $procmux$4972 (pure)
    Root of a mux tree: $procmux$4981 (pure)
    Root of a mux tree: $procmux$4987 (pure)
    Root of a mux tree: $procmux$4993 (pure)
    Root of a mux tree: $procmux$5002 (pure)
    Root of a mux tree: $procmux$5011 (pure)
    Root of a mux tree: $procmux$5017 (pure)
    Root of a mux tree: $procmux$5026 (pure)
    Root of a mux tree: $procmux$5032 (pure)
    Root of a mux tree: $procmux$5038 (pure)
    Root of a mux tree: $procmux$5044 (pure)
    Root of a mux tree: $procmux$5050 (pure)
    Root of a mux tree: $procmux$5059 (pure)
    Root of a mux tree: $procmux$5068 (pure)
    Root of a mux tree: $procmux$5083 (pure)
    Root of a mux tree: $procmux$5095 (pure)
    Root of a mux tree: $procmux$5104 (pure)
    Root of a mux tree: $procmux$5113 (pure)
    Root of a mux tree: $procmux$5128 (pure)
    Root of a mux tree: $procmux$5140 (pure)
    Root of a mux tree: $procmux$5149 (pure)
    Root of a mux tree: $procmux$5161 (pure)
    Root of a mux tree: $procmux$5173 (pure)
    Root of a mux tree: $procmux$5194 (pure)
    Root of a mux tree: $procmux$5206 (pure)
    Root of a mux tree: $procmux$5221 (pure)
    Root of a mux tree: $procmux$5227 (pure)
    Root of a mux tree: $procmux$5233 (pure)
    Root of a mux tree: $procmux$5251 (pure)
    Root of a mux tree: $procmux$5266 (pure)
    Root of a mux tree: $procmux$5275 (pure)
    Root of a mux tree: $procmux$5290 (pure)
    Root of a mux tree: $procmux$5296 (pure)
    Root of a mux tree: $procmux$5302 (pure)
    Root of a mux tree: $procmux$5311 (pure)
    Root of a mux tree: $procmux$5320 (pure)
    Root of a mux tree: $procmux$5329 (pure)
    Root of a mux tree: $procmux$5347 (pure)
    Root of a mux tree: $procmux$5353 (pure)
    Root of a mux tree: $procmux$5362 (pure)
    Root of a mux tree: $procmux$5365 (pure)
    Root of a mux tree: $procmux$5368 (pure)
    Root of a mux tree: $procmux$5371 (pure)
    Root of a mux tree: $procmux$5374 (pure)
    Root of a mux tree: $procmux$5377 (pure)
    Root of a mux tree: $procmux$5387 (pure)
    Root of a mux tree: $procmux$5408 (pure)
    Root of a mux tree: $procmux$5415 (pure)
    Root of a mux tree: $procmux$5418
    Root of a mux tree: $procmux$5421 (pure)
    Root of a mux tree: $procmux$5424 (pure)
    Root of a mux tree: $procmux$5427 (pure)
    Root of a mux tree: $procmux$5430 (pure)
    Root of a mux tree: $procmux$5433 (pure)
    Root of a mux tree: $procmux$5436 (pure)
    Root of a mux tree: $procmux$5439 (pure)
    Root of a mux tree: $procmux$5442 (pure)
    Root of a mux tree: $procmux$5445 (pure)
    Root of a mux tree: $procmux$5448 (pure)
    Root of a mux tree: $procmux$5451 (pure)
    Root of a mux tree: $procmux$5454 (pure)
    Root of a mux tree: $procmux$5457 (pure)
    Root of a mux tree: $procmux$5460 (pure)
    Root of a mux tree: $procmux$5463 (pure)
    Root of a mux tree: $procmux$5466 (pure)
    Root of a mux tree: $procmux$5469 (pure)
    Root of a mux tree: $procmux$5472 (pure)
    Root of a mux tree: $procmux$5475 (pure)
    Root of a mux tree: $procmux$5478 (pure)
    Root of a mux tree: $procmux$5481 (pure)
    Root of a mux tree: $procmux$5484 (pure)
    Root of a mux tree: $procmux$5493 (pure)
    Root of a mux tree: $procmux$5530
    Root of a mux tree: $procmux$5539
    Root of a mux tree: $procmux$5551 (pure)
    Root of a mux tree: $procmux$5570 (pure)
    Root of a mux tree: $procmux$5573 (pure)
    Root of a mux tree: $procmux$5607 (pure)
    Root of a mux tree: $procmux$5649 (pure)
    Root of a mux tree: $procmux$5679 (pure)
    Root of a mux tree: $procmux$5687 (pure)
    Root of a mux tree: $procmux$5691 (pure)
    Root of a mux tree: $procmux$5704 (pure)
    Root of a mux tree: $procmux$5742 (pure)
    Root of a mux tree: $procmux$5751 (pure)
    Root of a mux tree: $procmux$5783 (pure)
    Root of a mux tree: $procmux$5791 (pure)
    Root of a mux tree: $procmux$5799 (pure)
    Root of a mux tree: $procmux$5802 (pure)
    Root of a mux tree: $procmux$5811 (pure)
    Root of a mux tree: $procmux$5813 (pure)
    Root of a mux tree: $procmux$5818 (pure)
    Root of a mux tree: $procmux$5826
    Root of a mux tree: $procmux$5830 (pure)
    Root of a mux tree: $procmux$5846 (pure)
    Root of a mux tree: $procmux$5854
    Root of a mux tree: $procmux$5858 (pure)
    Root of a mux tree: $procmux$5877 (pure)
    Root of a mux tree: $procmux$5912 (pure)
    Root of a mux tree: $procmux$5923 (pure)
    Root of a mux tree: $procmux$5964
    Root of a mux tree: $procmux$5966 (pure)
    Root of a mux tree: $procmux$6008 (pure)
    Root of a mux tree: $procmux$6023 (pure)
    Root of a mux tree: $procmux$6067 (pure)
    Root of a mux tree: $procmux$6093 (pure)
    Root of a mux tree: $procmux$6105 (pure)
    Root of a mux tree: $procmux$6143 (pure)
    Root of a mux tree: $procmux$6152
    Root of a mux tree: $procmux$6161 (pure)
    Root of a mux tree: $procmux$6181 (pure)
    Root of a mux tree: $procmux$6201 (pure)
    Root of a mux tree: $procmux$6219 (pure)
    Root of a mux tree: $procmux$6232 (pure)
    Root of a mux tree: $procmux$6237 (pure)
    Root of a mux tree: $procmux$6240 (pure)
    Root of a mux tree: $procmux$6243 (pure)
    Root of a mux tree: $procmux$6249 (pure)
    Root of a mux tree: $procmux$6258 (pure)
    Root of a mux tree: $procmux$6269 (pure)
    Root of a mux tree: $procmux$6279 (pure)
    Root of a mux tree: $procmux$6290 (pure)
    Root of a mux tree: $procmux$6309 (pure)
    Root of a mux tree: $procmux$6316 (pure)
    Root of a mux tree: $procmux$6338 (pure)
    Root of a mux tree: $procmux$6341 (pure)
    Root of a mux tree: $procmux$6357 (pure)
    Root of a mux tree: $procmux$6367 (pure)
    Root of a mux tree: $procmux$6373 (pure)
    Root of a mux tree: $procmux$6382 (pure)
    Root of a mux tree: $procmux$6392 (pure)
    Root of a mux tree: $procmux$6410 (pure)
    Root of a mux tree: $procmux$6413 (pure)
    Root of a mux tree: $procmux$6422 (pure)
    Root of a mux tree: $procmux$6425 (pure)
    Root of a mux tree: $procmux$6428 (pure)
    Root of a mux tree: $procmux$6437 (pure)
    Root of a mux tree: $procmux$6440 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2935 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2944 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2953 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2959 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2965 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2968 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2974 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2980 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2986 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2992 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$2998 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3004 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3016 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3022 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3028 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3034 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3037 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3046 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3052 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3055 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3067 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3073 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3079 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3085 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3091 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3094 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3103 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3109 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3115 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3121 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3139 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3145 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3151 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3157 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3163 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3169 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3175 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3181 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3187 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3193 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3199 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3205 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3211 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3217 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3223 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3229 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3235 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3241 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3247 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3253 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3259 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3271 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3283 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3295 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3304 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3322 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3325 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3331 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3379
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3399
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3417
    Root of a mux tree: $techmap\lm32_cpu.$procmux$3420 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1570$2469 (pure)
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1583$2473
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1647$2489
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1657$2491
    Root of a mux tree: $techmap\lm32_cpu.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_cpu.v:1667$2493 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.$procmux$7084 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:92$707 (pure)
    Root of a mux tree: $techmap\lm32_cpu.adder.addsub.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:93$710 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7356 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$procmux$7359 (pure)
    Root of a mux tree: $techmap\lm32_cpu.decoder.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_decoder.v:599$127 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6530 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6536 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6545 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6554 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6566 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6575 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6584 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6623 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6638 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6653 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6659 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6668 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6674 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6680 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6686 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.$procmux$6710
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6456 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6465 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6475 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6494 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6521 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$procmux$6524 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.$ternary$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_icache.v:325$2848 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2911 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_data_ram.$procmux$2914 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2923 (pure)
    Root of a mux tree: $techmap\lm32_cpu.instruction_unit.icache.memories[0].way_0_tag_ram.$procmux$2926 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7102 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7120 (pure)
    Root of a mux tree: $techmap\lm32_cpu.interrupt_unit.$procmux$7138 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6713 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6716 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6719 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6725 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6731 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6737 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6743 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6749 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6761 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6770 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6803 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6818 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6830 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6845 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6857 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6866 (pure)
    Root of a mux tree: $techmap\lm32_cpu.load_store_unit.$procmux$6884 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6927 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6971 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$6988 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7012 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7035 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7045 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7061 (pure)
    Root of a mux tree: $techmap\lm32_cpu.mc_arithmetic.$procmux$7081 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

21.7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.7.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.7.9.6. Executing OPT_RMDFF pass (remove dff with constant values).

21.7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removing unused `$sub' cell `$techmap\lm32_cpu.adder.addsub.$sub$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:90$703'.
  removing unused `$add' cell `$techmap\lm32_cpu.adder.addsub.$add$/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_addsub.v:89$701'.
  removed 104 unused temporary wires.
Removed 479 unused cells and 4557 unused wires.

21.7.9.8. Executing OPT_EXPR pass (perform const folding).

21.7.9.9. Rerunning OPT passes. (Maybe there is more to do..)

21.7.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$3423 (pure)
    Root of a mux tree: $procmux$3432 (pure)
    Root of a mux tree: $procmux$3441 (pure)
    Root of a mux tree: $procmux$3450 (pure)
    Root of a mux tree: $procmux$3459 (pure)
    Root of a mux tree: $procmux$3468 (pure)
    Root of a mux tree: $procmux$3471 (pure)
    Root of a mux tree: $procmux$3480 (pure)
    Root of a mux tree: $procmux$3483 (pure)
    Root of a mux tree: $procmux$3492 (pure)
    Root of a mux tree: $procmux$3501 (pure)
    Root of a mux tree: $procmux$3510 (pure)
    Root of a mux tree: $procmux$3519 (pure)
    Root of a mux tree: $procmux$3531 (pure)
    Root of a mux tree: $procmux$3540 (pure)
    Root of a mux tree: $procmux$3549 (pure)
    Root of a mux tree: $procmux$3558 (pure)
    Root of a mux tree: $procmux$3567 (pure)
    Root of a mux tree: $procmux$3576 (pure)
    Root of a mux tree: $procmux$3585 (pure)
    Root of a mux tree: $procmux$3594 (pure)
    Root of a mux tree: $procmux$3603 (pure)
    Root of a mux tree: $procmux$3612 (pure)
    Root of a mux tree: $procmux$3621 (pure)
    Root of a mux tree: $procmux$3630 (pure)
    Root of a mux tree: $procmux$3639 (pure)
    Root of a mux tree: $procmux$3648 (pure)
    Root of a mux tree: $procmux$3657 (pure)
    Root of a mux tree: $procmux$3666 (pure)
    Root of a mux tree: $procmux$3755 (pure)
    Root of a mux tree: $procmux$3773 (pure)
    Root of a mux tree: $procmux$3863 (pure)
    Root of a mux tree: $procmux$3869 (pure)
    Root of a mux tree: $procmux$3872 (pure)
    Root of a mux tree: $procmux$3878 (pure)
    Root of a mux tree: $procmux$3881 (pure)
    Root of a mux tree: $procmux$3887 (pure)
    Root of a mux tree: $procmux$3890 (pure)
    Root of a mux tree: $procmux$3896 (pure)
    Root of a mux tree: $procmux$3902 (pure)
    Root of a mux tree: $procmux$3908 (pure)
    Root of a mux tree: $procmux$3914 (pure)
    Root of a mux tree: $procmux$3920 (pure)
    Root of a mux tree: $procmux$3926 (pure)
    Root of a mux tree: $procmux$3932 (pure)
    Root of a mux tree: $procmux$3941 (pure)
    Root of a mux tree: $procmux$3950 (pure)
    Root of a mux tree: $procmux$3959 (pure)
    Root of a mux tree: $procmux$3968 (pure)
    Root of a mux tree: $procmux$3977 (pure)
    Root of a mux tree: $procmux$3986 (pure)
    Root of a mux tree: $procmux$3995 (pure)
    Root of a mux tree: $procmux$4004 (pure)
    Root of a mux tree: $procmux$4010 (pure)
    Root of a mux tree: $procmux$4022 (pure)
    Root of a mux tree: $procmux$4028 (pure)
    Root of a mux tree: $procmux$4034 (pure)
    Root of a mux tree: $procmux$4043 (pure)
    Root of a mux tree: $procmux$4049 (pure)
    Root of a mux tree: $procmux$4064 (pure)
    Root of a mux tree: $procmux$4070 (pure)
    Root of a mux tree: $procmux$4076 (pure)
    Root of a mux tree: $procmux$4082 (pure)
    Root of a mux tree: $procmux$4088 (pure)
    Root of a mux tree: $procmux$4094 (pure)
    Root of a mux tree: $procmux$4100 (pure)
    Root of a mux tree: $procmux$4106 (pure)
    Root of a mux tree: $procmux$4112 (pure)
    Root of a mux tree: $procmux$4118 (pure)
    Root of a mux tree: $procmux$4124 (pure)
    Root of a mux tree: $procmux$4130 (pure)
    Root of a mux tree: $procmux$4136 (pure)
    Root of a mux tree: $procmux$4145 (pure)
    Root of a mux tree: $procmux$4151 (pure)
    Root of a mux tree: $procmux$4157 (pure)
    Root of a mux tree: $procmux$4206 (pure)
    Root of a mux tree: $procmux$4220 (pure)
    Root of a mux tree: $procmux$4234 (pure)
    Root of a mux tree: $procmux$4268 (pure)
    Root of a mux tree: $procmux$4285 (pure)
    Root of a mux tree: $procmux$4329 (pure)
    Root of a mux tree: $procmux$4332 (pure)
    Root of a mux tree: $procmux$4352 (pure)
    Root of a mux tree: $procmux$4355 (pure)
    Root of a mux tree: $procmux$4358 (pure)
    Root of a mux tree: $procmux$4361 (pure)
    Root of a mux tree: $procmux$4373 (pure)
    Root of a mux tree: $procmux$4376 (pure)
    Root of a mux tree: $procmux$4388 (pure)
    Root of a mux tree: $procmux$4391 (pure)
    Root of a mux tree: $procmux$4403 (pure)
    Root of a mux tree: $procmux$4406 (pure)
    Root of a mux tree: $procmux$4418 (pure)
    Root of a mux tree: $procmux$4421 (pure)
    Root of a mux tree: $procmux$4439 (pure)
    Root of a mux tree: $procmux$4451 (pure)
    Root of a mux tree: $procmux$4457 (pure)
    Root of a mux tree: $procmux$4460 (pure)
    Root of a mux tree: $procmux$4478 (pure)
    Root of a mux tree: $procmux$4493 (pure)
    Root of a mux tree: $procmux$4496 (pure)
    Root of a mux tree: $procmux$4499 (pure)
    Root of a mux tree: $procmux$4502 (pure)
    Root of a mux tree: $procmux$4508 (pure)
    Root of a mux tree: $procmux$4514 (pure)
    Root of a mux tree: $procmux$4523 (pure)
    Root of a mux tree: $procmux$4541 (pure)
    Root of a mux tree: $procmux$4550 (pure)
    Root of a mux tree: $procmux$4559 (pure)
    Root of a mux tree: $procmux$4568 (pure)
    Root of a mux tree: $procmux$4577 (pure)
    Root of a mux tree: $procmux$4590 (pure)
    Root of a mux tree: $procmux$4596 (pure)
    Root of a mux tree: $procmux$4605 (pure)
    Root of a mux tree: $procmux$4614 (pure)
    Root of a mux tree: $procmux$4617 (pure)
    Root of a mux tree: $procmux$4623 (pure)
    Root of a mux tree: $procmux$4632 (pure)
    Root of a mux tree: $procmux$4641 (pure)
    Root of a mux tree: $procmux$4650 (pure)
    Root of a mux tree: $procmux$4659 (pure)
    Root of a mux tree: $procmux$4668 (pure)
    Root of a mux tree: $procmux$4674 (pure)
    Root of a mux tree: $procmux$4683 (pure)
    Root of a mux tree: $procmux$4692 (pure)
    Root of a mux tree: $procmux$4701 (pure)
    Root of a mux tree: $procmux$4710 (pure)
    Root of a mux tree: $procmux$4719 (pure)
    Root of a mux tree: $procmux$4728 (pure)
    Root of a mux tree: $procmux$4738 (pure)
    Root of a mux tree: $procmux$4744 (pure)
    Root of a mux tree: $procmux$4753 (pure)
    Root of a mux tree: $procmux$4762 (pure)
    Root of a mux tree: $procmux$4782 (pure)
    Root of a mux tree: $procmux$4791 (pure)
    Root of a mux tree: $procmux$4800 (pure)
    Root of a mux tree: $procmux$4809 (pure)
    Root of a mux tree: $procmux$4821 (pure)
    Root of a mux tree: $procmux$4827 (pure)
    Root of a mux tree: $procmux$4836 (pure)
    Root of a mux tree: $procmux$4845 (pure)
    Root of a mux tree: $procmux$4848 (pure)
    Root of a mux tree: $procmux$4854 (pure)
    Root of a mux tree: $procmux$4863 (pure)
    Root of a mux tree: $procmux$4872 (pure)
    Root of a mux tree: $procmux$4881 (pure)
    Root of a mux tree: $procmux$4890 (pure)
    Root of a mux tree: $procmux$4903 (pure)
    Root of a mux tree: $procmux$4909 (pure)
    Root of a mux tree: $procmux$4918 (pure)
    Root of a mux tree: $procmux$4927 (pure)
    Root of a mux tree: $procmux$4933 (pure)
    Root of a mux tree: $procmux$4945 (pure)
    Root of a mux tree: $procmux$4951 (pure)
    Root of a mux tree: $procmux$4957 (pure)
    Root of a mux tree: $procmux$4963 (pure)
    Root of a mux tree: $procmux$4972 (pure)
    Root of a mux tree: $procmux$4981 (pure)
    Root of a mux tree: $procmux$4987 (pure)
    Root of a mux tree: $procmux$4993 (pure)
    Root of a mux tree: $procmux$5002 (pure)
    Root of a mux tree: $procmux$5011 (pure)
    Root of a mux tree: $procmux$5017 (pure)
    Root of a mux tree: $procmux$5026 (pure)
    Root of a mux tree: $procmux$5032 (pure)
    Root of a mux tree: $procmux$5038 (pure)
    Root of a mux tree: $procmux$5044 (pure)
    Root of a mux tree: $procmux$5050 (pure)
    Root of a mux tree: $procmux$5059 (pure)
    Root of a mux tree: $procmux$5068 (pure)
    Root of a mux tree: $procmux$5083 (pure)
    Root of a mux tree: $procmux$5095 (pure)
    Root of a mux tree: $procmux$5104 (pure)
    Root of a mux tree: $procmux$5113 (pure)
    Root of a mux tree: $procmux$5128 (pure)
    Root of a mux tree: $procmux$5140 (pure)
    Root of a mux tree: $procmux$5149 (pure)
    Root of a mux tree: $procmux$5161 (pure)
    Root of a mux tree: $procmux$5173 (pure)
    Root of a mux tree: $procmux$5194 (pure)
    Root of a mux tree: $procmux$5206 (pure)
    Root of a mux tree: $procmux$5221 (pure)
    Root of a mux tree: $procmux$5227 (pure)
    Root of a mux tree: $procmux$5233 (pure)
    Root of a mux tree: $procmux$5251 (pure)
    Root of a mux tree: $procmux$5266 (pure)
    Root of a mux tree: $procmux$5275 (pure)
    Root of a mux tree: $procmux$5290 (pure)
    Root of a mux tree: $procmux$5296 (pure)
    Root of a mux tree: $procmux$5302 (pure)
    Root of a mux tree: $procmux$5311 (pure)
    Root of a mux tree: $procmux$5320 (pure)
    Root of a mux tree: $procmux$5329 (pure)
    Root of a mux tree: $procmux$5347 (pure)
    Root of a mux tree: $procmux$5353 (pure)
    Root of a mux tree: $procmux$5362 (pu