HDMI Testing Instructions

HDMI-Testing.txt

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# Test 0 - 5V power supply test

 * Power on the board with nothing connected to the HDMI ports.

 * On RX ports, +5V pin should be ~0V.
 * On TX ports, +5V pin should be 5V.

 * Shorting the +5V pin to ground on any port should not cause board
malfunction. (When shorting the 5V to GND on the TX ports, the associated
5V regulator may get hot and enter thermal shutdown. )

 * Shorting one of the +5V pins to ground should not cause any effect on
the +5V pins on the other connectors.

##### Obtained Result

 * All Result obtained
----------------------------

# Test 1 - All high output (nothing connected), no heating issue

## Setup

* Set all the HDMI connected pins on the FPGA as output, sending high.
* Nothing should be connected to the HDMI connector.
* This test should be done for *all* HDMI ports, both receive and send.

## Results

* The HPD, SDA and SCL lines should be ~3.3V on the FPGA side of the
buffer and ~5V on the HDMI connector side of the buffer.

* The CEC line should be ~3.3V on the  FPGA side of the buffer and ~3.3V
on the HDMI connector side of the buffer.

* There should be minimal current draw from the 5V regulators and none of
the resistors should be getting hot.


##### Obtained Result

 ** HDMI connector side of the buffer
   ** HDMI IN 1(RX)                ** HDMI IN 2(RX)
      CEC   => ~3.33V                  CEC => ~3.18V
      SCL   => ~4.77V                  SCL => ~4.64V
      SDA   => ~4.77V                  SDA => ~4.64V
      HPD   => ~4.77V                  HPD => ~4.64V

   ** HDMI OUT 1(TX)               ** HDMI OUT 2(TX)
      CEC   => ~3.18V                  CEC => ~3.18V
      SCL   => ~4.94V                  SCL => ~4.94V
      SDA   => ~4.94V                  SDA => ~4.94V
      HPD   => ~0.0V                   HPD => ~2.17V


 ** FPGA side of the buffer
   ** HDMI IN 1(RX)                ** HDMI IN 2(RX)
      CEC   => ~3.3V                    CEC => ~3.3V
      SCL   => ~3.3V                    SCL => ~3.3V
      SDA   => ~3.3V                    SDA => ~3.3V
      HPD   => ~3.3V                    HPD => ~3.3V

   ** HDMI OUT 1(TX)               ** HDMI OUT 2(TX)
      CEC   => ~3.3V                    CEC => ~3.3V
      SCL   => ~3.3V                    SCL => ~3.3V
      SDA   => ~3.3V                    SDA => ~3.3V
      HPD   => ~0.0V                    HPD => ~3.3V


----------------------------

# Test 2 - All low output (nothing connected)

## Setup

* Set all the HDMI connected pins on the FPGA as output, sending low.
* Nothing should be connected to the HDMI connector.
* This test should be done for *all* HDMI ports, both receive and send.

## Results

* All of HPD, CEC, SDA and SCL should be ~0V on both the FPGA side and the
HDMI connector side of the buffer.

* There will be some current draw from the 5V regulators but it should be
on the order of 1-2 milliamps or less. Neither the regulators nor any
resistors should be getting hot.

##### Obtained Result

 * All Result obtained

----------------------------

# Test 3 - All pins input, nothing connected

## Setup

* Set all the HDMI connected pins on the FPGA as inputs.
* Nothing should be connected to the HDMI connector.
* This test should be done for *all* HDMI ports, both receive and send.

## Results - All ports

* The SDA and SCL lines should be ~3.3V on the FPGA side of the buffer and
~5V on the HDMI connector side of the buffer. The FPGA should be reading
this value as 1.

* The CEC line should be ~3.3V on the  FPGA side of the buffer and ~3.3V
on the HDMI connector side of the buffer. The FPGA should be reading this
value as 1.

## Results - RX ports

 * HPD should be ~3.3V on the FPGA side and ~5V on the HDMI of the buffer.
The FPGA should be reading this value as 0.

## Results - TX ports

 * HPD should be ~0V on both the FPGA and HDMI connector sides of the
buffer. The FPGA should be reading this value as 0.

##### Obtained Result

 ** HDMI IN 2(RX)
    * SDA & SCL result obtained. Reading obtained 1.        
    * CEC ~2.96V - FPGA side of the buffer and ~3.3V on the HDMI connector side of the buffer. Reading obtained 1.
    * HPD ~2.35V FPGA side of the buffer and ~5V on the HDMI of the buffer. Reading obtained 1.

 ** HDMI IN 1(RX)
    * SDA & SCL result obtained. Reading obtained 1.        
    * CEC ~2.96V FPGA side of the buffer and ~3.3V on the HDMI connector side of the buffer. Reading obtained 1.
    * HPD ~2.45V FPGA side of the buffer and ~4.45V on the HDMI of the buffer.  Reading obtained 1.

 ** HDMI OUT 1(TX)
    * SDA & SCL result obtained. Reading obtained 1.        
    * CEC ~2.96V FPGA side of the buffer and ~3.3V on the HDMI connector side of the buffer. Reading obtained 1.
    * HPD ~0.0V FPGA side of the buffer and ~0.0V on the HDMI of the buffer.  Reading obtained 0.

 ** HDMI OUT 2(TX)
    * SDA & SCL result obtained. Reading obtained 1.        
    * CEC ~2.96V FPGA side of the buffer and ~3.3V on the HDMI connector side of the buffer. Reading obtained 1.
    * HPD ~0.0V FPGA side of the buffer and ~0.0V on the HDMI of the buffer.  Reading obtained 0.


----------------------------

# Test 4 - All output, square wave signal.

## Setup

* Set all the HDMI connected pins on the FPGA as outputs, make each pin
generate a ~500kHz square wave (exact frequency doesn't really matter, but
it should be roughly 500kHz).
* Nothing should be connected to the HDMI connector.
* This test should be done for *all* HDMI ports, both receive and send.

## Results - All ports

 * A 5V, 500kHz square wave should be found on the SCL, SDA and HPD lines.
 * A 3.3V, 500kHz square wave should be found on the CEC lines.


 ##### Obtained Result

 ** HDMI connector side of the buffer
   ** HDMI IN 1(RX)                      ** HDMI IN 2(RX)
      CEC => ~2.0V 500 MHz               CEC => ~2.0V 500 MHz
      SCL => ~4.5V 500 MHz               SCL => ~4.5V 500 MHz
      SDA => ~4.5V 500 MHz               SDA => ~4.5V 500 MHz
      HPD => ~1.0V 500 MHz               HPD => ~1.0V 500 MHz

   ** HDMI OUT 1(TX)                     **HDMI OUT 2(TX)
      CEC => ~2.0V 500 MHz               CEC => ~2.0V 500 MHz
      SCL => ~4.5V 500 MHz               SCL => ~4.5V 500 MHz
      SDA => ~4.5V 500 MHz               SDA => ~4.5V 500 MHz
      HPD => ~0.0V 00  MHz               HPD => ~2.0V 500 MHz


 ** FPGA side of the buffer
   ** HDMI IN 1(RX)                      ** HDMI IN 2(RX)
      CEC => ~3.3V 500 MHz               CEC => ~3.3V 500 MHz
      SCL => ~3.3V 500 MHz               SCL => ~3.3V 500 MHz
      SDA => ~3.3V 500 MHz               SDA => ~3.3V 500 MHz
      HPD => ~1.0V 500 MHz               HPD => ~1.0V 500 MHz

   ** HDMI OUT 1(TX)                     **HDMI OUT 2(TX)
      CEC => ~3.3V 500 MHz               CEC => ~3.3V 500 MHz
      SCL => ~3.3V 500 MHz               SCL => ~3.3V 500 MHz
      SDA => ~3.3V 500 MHz               SDA => ~3.3V 500 MHz
      HPD => ~0.0V 00  MHz               HPD => ~3.3V 500 MHz