dpram32.sim.v

`default_nettype none

/*
 * Dual Port (Async read, sync write) - 32 * 1-bit (LUT) RAM.
 */
//(* whitebox *)
module DPRAM32 (
  // Sync write port
  CLK, WE, WA, DI,
  // Async read port
  A, O
);
  // Memory data storage
  // --------------------------
  localparam DATA_WIDTH = 1;  // 1-bit
  localparam ADDR_WIDTH = 5;  // 2**5 == 32 positions
  localparam DATA_WORDS = 2 ** ADDR_WIDTH;
  reg [DATA_WIDTH-1:0] mem [0:DATA_WORDS-1];

  // Memory init from parameter...
  localparam MEM_SIZE = DATA_WIDTH * DATA_WORDS;
  parameter [MEM_SIZE-1:0] INIT_00 = 1'bx;
  genvar i;
  generate
    for(i = 0; i < DATA_WORDS; i++) begin
      initial mem[i] = INIT_00[i*DATA_WIDTH +: DATA_WIDTH];
    end
  endgenerate

  // Async read port
  // --------------------------
  // Read Address (unclocked)
  input wire [ADDR_WIDTH-1:0] A;
  // Data Output (unclocked)
  output wire O;

  // Read port
  always @(*) begin
    O = mem[A];
  end

  // Sync write port
  // --------------------------
  // Clock
  input wire CLK;
  // Write enable (clocked)
  input wire WE;
  // Write address (clocked)
  input wire [ADDR_WIDTH-1:0] WA;
  // Data input (clocked)
  input wire DI;

  always @(posedge CLK) begin
    if (WE) begin
      mem[WA] <= DI;
    end
  end

endmodule