roi-harness.patch

----------------------- minitests/roi_harness/README.md -----------------------
index 35d4111..6d57316 100644
@@ -1,35 +1,124 @@
 # ROI_HARNESS Minitest
 
 ## Purpose
 
-Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness
+Creates an harness bitstream which maps peripherals into a region of interest
+which can be reconfigured.
+
+The currently supported boards are;
+
+ * Artix 7 boards;
+  - [Basys 3](https://github.com/SymbiFlow/prjxray-db/tree/master/artix7/harness#basys-3)
+  - [Arty A7-35T](https://github.com/SymbiFlow/prjxray-db/tree/master/artix7/harness#arty-a7-35t)
+
+ * Zynq boards;
+  - [Zybo Z7-10](https://github.com/SymbiFlow/prjxray-db/tree/master/zynq7/harness#zybo-z7-10)
+
+The following configurations are supported;
+
+
+ * SWBUT - Harness which maps a board's switches, buttons and LEDs into the
+   region of interest (plus clock).
+
+
+ * PMOD - Harness which maps a board's PMOD connectors into the region of
+   interest (plus a clock).
+
+ * UART - Harness which maps a board's UART
+
+
+"ARTY-A7-SWBUT"
+        # 4 switches then 4 buttons
+        set sw_but "A8 C11 C10 A10  D9 C9 B9 B8"
+        # 4 LEDs then 4 RGB LEDs (green only)
+        set leds "H5 J5 T9 T10  F6 J4 J2 H6"
+
+        set pin "E3"
+        set net2pin(clk) $pin
+
+"ARTY-A7-PMOD"
+        set pmod_ja "G13 B11 A11 D12  D13 B18 A18 K16"
+        set pmod_jb "E15 E16 D15 C15  J17 J18 K15 J15"
+        set pmod_jc "U12 V12 V10 V11  U14 V14 T13 U13"
+
+        # CLK on Pmod JA
+        set pin [lindex $pmod_ja 0]
+        set net2pin(clk) $pin
+
+"ARTY-A7-UART"
+        # RST button and UART_RX
+        set arty_in  "C2 A9"
+        # LD7 and UART_TX
+        set arty_out "T10 D10"
+
+        # 100 MHz CLK onboard
+        set pin "E3"
+        set net2pin(clk) $pin
+
+"BASYS3-SWBUT"
+        # Slide switches
+        set ins "V17 V16 W16 W17 W15 V15 W14 W13 V2 T3 T2 R3 W2 U1 T1 R2"
+        set outs "U16 E19 U19 V19 W18 U15 U14 V14 V13 V3 W3 U3 P3 N3 P1 L1"
+
+        # UART
+        lappend ins B18
+        lappend outs A18
+
+
+        # 100 MHz CLK onboard
+        set pin "W5"
+        set net2pin(clk) $pin
+
+"ZYBOZ7-SWBUT"
+        # J15 - UART_RX - JE3
+        # G15 - SW0
+        # K18 - BTN0
+        # K19 - BTN1
+        set ins  "J15  G15  K18 K19"
+
+        # H15 - UART_TX - JE4
+        # E17 - ETH PHY reset (active low, keep high for 125 MHz clock)
+        # M14 - LD0
+        # G14 - LD2
+        # M15 - LD1
+        # D18 - LD3
+        set outs "H15  E17  M14 M15 D18 G14"
+
+        # 125 MHz CLK onboard
+        set pin "K17"
+        set net2pin(clk) $pin
+
+
+
+
+clk, inputs, and outputs to use as a partial reconfiguration test harness