Tim 'mithro' Ansell mithro

module top(
	input clk16,
	output reg spiflash_cs_n,
	output reg spiflash_clk,
	output reg spiflash_mosi,
	input spiflash_miso,
	output spiflash_wp,
	output spiflash_hold,

SPI PROM Requirements

The iCE40 SPI Flash configuration interface supports a variety of SPI Flash memory vendors and product families. However, Lattice does not specifically test, qualify, or otherwise endorse any specific SPI Flash vendor or product family. The iCE40 SPI interface supports SPI PROMs that they meet the following requirements.

The PROM must operate between 1.8V to 3.3V in order to trigger the iCE40 FPGA’s power-on reset circuit.
The PROM must support the 0x0B Fast Read command, using a 24-bit start address and has 8 dummy bits before the PROM provides first data (see Figure 9).
The PROM must have enough bits to program the iCE40 device.

Script for running as part of "preflight" checks on a CI system.

It should allow you to cancel build if it is only documentation, etc.

https://github.com/dev-id/Magic-Spoiler/blob/8111a06ab6682e020169991d5e2aa4fa503d787f/preflight.sh

	<!-- vim: set ai sw=1 ts=1 sta et: -->

	<!--
	Block RAM in 7 series is 36kbbit split into two 18kbit sections.
	The Block RAM is "true dual port".
	There are both Latches (first) and Registers (second) on the output (why!?)

	The RAM has extra bits that can be used for parity (DIP / DOP).

	-->

	<?xml version="1.0"?>
	<block name="example.net" instance="FPGA_packed_netlist[0]" architecture_id="SHA256:4f677e37c2eb41c5ca4d4ca832b1238a2cad5db9aa7f77d79414427e0b4af7d4" atom_netlist_id="SHA256:d580395e60a9d2f1fead66314d0861412355648fda2c12ab20ed041864660bb3">
	<inputs>clk</inputs>
	<outputs>out:LED2 out:LED3 out:LED4 out:LED5</outputs>
	<clocks>clk</clocks>
	<block name="$0\counter[28:0][28]" instance="BLK_TL-PLB[0]" mode="default">
	<inputs>
	<port name="lutff_0/in">counter[23] $abc$1426$n75_1 counter[22] counter[24]</port>
	<port name="lutff_1/in">$abc$1426$n71_1 counter[21] counter[19] counter[20]</port>
	<port name="lutff_2/in">open counter[25] $abc$1426$n79_1 open</port>

	/* FIXME: Use a smarter data structure. */
	class t_metadata_as {
	std::string value_;

	public:
	t_metadata_as(std::string v) : value_(v) {}
	t_metadata_as(const t_metadata_as &o) : value_(o.value_) {}
	int as_int() const;
	double as_double() const;
	std::string as_string() const { return value_; }

	class SwitchType(enum.Enum):
	mux = "mux"
	tristate = "tristate"
	pass_gate = "pass_gate"
	short = "short"
	buffer = "buffer"

	@property
	def isolating(self):
	"""If switch type is isolating.

	VPR ?= vpr
	YOSYS ?= yosys

	ifeq (,$(DEVICE))
	$(error "Please define $$DEVICE to a value in your architecture file.")
	endif

	##########################################################################

	OUTPUT_DIR ?= build

	#!/usr/bin/env python3
	#
	# Convert rr_graph file from Verilog-To-Routing into GraphViz `.dot` file.
	# https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#routing-resource-graph-file-format-xml

	from lxml import etree
	from io import StringIO, BytesIO

	tree = etree.parse('ff.rr_graph.xml')
	root = tree.getroot()

	*.log
	*.echo
	*.xml
	*.net
	*.route