Created
July 20, 2019 21:27
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| HW.GFX.GMA.Initialize | |
| HW.GFX.GMA.Panel.Setup_PP_Sequencer | |
| HW.GFX.GMA.Registers.Read: 0x0e200064 <- 0x000c7208:PCH_PP_ON_DELAYS | |
| HW.GFX.GMA.Registers.Read: 0x13880e20 <- 0x000c720c:PCH_PP_OFF_DELAYS | |
| HW.GFX.GMA.Registers.Read: 0x0004af06 <- 0x000c7210:PCH_PP_DIVISOR | |
| HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Read: 0x00000008 <- 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Write: 0x0000000a -> 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A | |
| HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP | |
| HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c2014:SFUSE_STRAP | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP | |
| HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c2014:SFUSE_STRAP | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL | |
| HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e00:DDI_BUF_TRANS_A_S0T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2 | |
| HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1 | |
| HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2 | |
| HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e14:DDI_BUF_TRANS_A_S2T2 | |
| HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2 | |
| HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e20:DDI_BUF_TRANS_A_S4T1 | |
| HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e24:DDI_BUF_TRANS_A_S4T2 | |
| HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2 | |
| HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2 | |
| HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1 | |
| HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2 | |
| HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2 | |
| HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2 | |
| HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e60:DDI_BUF_TRANS_B_S0T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2 | |
| HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1 | |
| HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2 | |
| HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e74:DDI_BUF_TRANS_B_S2T2 | |
| HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2 | |
| HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e80:DDI_BUF_TRANS_B_S4T1 | |
| HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e84:DDI_BUF_TRANS_B_S4T2 | |
| HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2 | |
| HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2 | |
| HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1 | |
| HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2 | |
| HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2 | |
| HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2 | |
| HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2 | |
| HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1 | |
| HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2 | |
| HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2 | |
| HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2 | |
| HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1 | |
| HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2 | |
| HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2 | |
| HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2 | |
| HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1 | |
| HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064efc:DDI_BUF_TRANS_C_S7T2 | |
| HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2 | |
| HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1 | |
| HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0 | |
| HW.GFX.GMA.Registers.Read: 0x08800000 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0 | |
| HW.GFX.GMA.Registers.Write: 0x0036db00 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0 | |
| HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL | |
| HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL | |
| HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL | |
| HW.GFX.GMA.Registers.Set_Mask: 0x000f8000 .S DPLL_CTRL2 | |
| HW.GFX.GMA.Registers.Read: 0x00a00001 <- 0x0006c05c:DPLL_CTRL2 | |
| HW.GFX.GMA.Registers.Write: 0x00af8001 -> 0x0006c05c:DPLL_CTRL2 | |
| HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT | |
| HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT | |
| HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT | |
| HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0x70000001 -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL | |
| HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL | |
| HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL | |
| HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL | |
| HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 | |
| HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX | |
| HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL | |
| HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL | |
| HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL | |
| HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ | |
| HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ | |
| HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ | |
| HW.GFX.GMA.Panel.On | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7200:PCH_PP_STATUS | |
| HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Write: 0x0000000b -> 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Display_Probing.Read_EDID | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0xf0000003 -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0xf0000023 -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B | |
| HW.GFX.GMA.Display_Probing.Read_EDID | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On | |
| HW.GFX.GMA.Registers.Read: 0xf0000013 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On | |
| HW.GFX.GMA.Registers.Read: 0xf0000013 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0xf00000b3 -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C | |
| HW.GFX.GMA.Display_Probing.Read_EDID | |
| HW.GFX.GMA.I2C.I2C_Read | |
| HW.GFX.GMA.I2C.Init_GMBUS | |
| HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0 | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 | |
| HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 | |
| HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 | |
| HW.GFX.GMA.I2C.Release_GMBUS | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 | |
| HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Display_Probing.Read_EDID | |
| HW.GFX.GMA.I2C.I2C_Read | |
| HW.GFX.GMA.I2C.Init_GMBUS | |
| HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0 | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 | |
| HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 | |
| HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 | |
| HW.GFX.GMA.I2C.Release_GMBUS | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 | |
| HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D | |
| HW.GFX.GMA.Panel.Wait_On | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Read: 0x0000000b <- 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Display_Probing.Read_EDID | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On | |
| HW.GFX.GMA.Registers.Read: 0xf0000053 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0xf00000fb -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A | |
| HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A | |
| HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1 | |
| HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A | |
| HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A | |
| HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A | |
| HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00064014:DDI_AUX_DATA_A_1 | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off | |
| HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off | |
| HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x00000080 !S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0xf000007f -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off | |
| HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x00000020 !S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0xf000001f -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off | |
| HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0xf0000007 -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR | |
| HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG | |
| HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 | |
| HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 | |
| HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045400:PWR_WELL_CTL_BIOS | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER | |
| HW.GFX.GMA.Panel.Off | |
| HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL | |
| HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS |
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