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mjg59/gist:e782a9c33dee3ce67c5ee68933ae1d29

Created July 21, 2019 19:23
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gistfile1.txt
[134.140989] HW.GFX.GMA.Initialize
[134.141256] HW.GFX.GMA.Panel.Setup_PP_Sequencer
[134.141278] HW.GFX.GMA.Registers.Read: 0x0e200001 <- 0x000c7208:PCH_PP_ON_DELAYS
[134.141321] HW.GFX.GMA.Registers.Read: 0x13880001 <- 0x000c720c:PCH_PP_OFF_DELAYS
[134.141370] HW.GFX.GMA.Registers.Read: 0x0004af06 <- 0x000c7210:PCH_PP_DIVISOR
[134.141405] PP: Using preset POWER_UP_DELAY of 361600 us.
[134.141428] PP: Using preset POWER_UP_TO_BL_ON of 100 us.
[134.141448] PP: Using preset POWER_DOWN_DELAY of 500000 us.
[134.141471] PP: Using preset BL_OFF_TO_POWER_DOWN of 100 us.
[134.141491] PP: Using preset POWER_CYCLE_DELAY of 500000 us.
[134.141513] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL
[134.141544] HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c7204:PCH_PP_CONTROL
[134.141578] HW.GFX.GMA.Registers.Write: 0x00000007 -> 0x000c7204:PCH_PP_CONTROL
[134.141619] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
[134.141634] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
[134.141669] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[134.141690] HW.GFX.GMA.Registers.Read: 0x10101010 <- 0x000c4030:SHOTPLUG_CTL
[134.141724] HW.GFX.GMA.Registers.Write: 0x13101010 -> 0x000c4030:SHOTPLUG_CTL
[134.141765] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
[134.141786] HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c2014:SFUSE_STRAP
[134.141820] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[134.141842] HW.GFX.GMA.Registers.Read: 0x10101010 <- 0x000c4030:SHOTPLUG_CTL
[134.141876] HW.GFX.GMA.Registers.Write: 0x10101013 -> 0x000c4030:SHOTPLUG_CTL
[134.141916] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
[134.141937] HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c2014:SFUSE_STRAP
[134.141971] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[134.141992] HW.GFX.GMA.Registers.Read: 0x10101010 <- 0x000c4030:SHOTPLUG_CTL
[134.142027] HW.GFX.GMA.Registers.Write: 0x10101310 -> 0x000c4030:SHOTPLUG_CTL
[134.142067] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e00:DDI_BUF_TRANS_A_S0T1
[134.142102] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2
[134.142136] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1
[134.142170] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2
[134.142205] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1
[134.142239] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e14:DDI_BUF_TRANS_A_S2T2
[134.142273] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1
[134.142307] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2
[134.142343] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e20:DDI_BUF_TRANS_A_S4T1
[134.142377] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e24:DDI_BUF_TRANS_A_S4T2
[134.142412] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1
[134.142447] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2
[134.142481] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1
[134.142515] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2
[134.142549] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1
[134.142583] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2
[134.142618] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1
[134.142652] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2
[134.142686] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1
[134.142720] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2
[134.142755] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e60:DDI_BUF_TRANS_B_S0T1
[134.142789] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2
[134.142823] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1
[134.142857] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2
[134.142892] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1
[134.142928] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e74:DDI_BUF_TRANS_B_S2T2
[134.142963] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1
[134.142997] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2
[134.143032] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e80:DDI_BUF_TRANS_B_S4T1
[134.143066] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e84:DDI_BUF_TRANS_B_S4T2
[134.143101] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1
[134.143135] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2
[134.143170] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1
[134.143204] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2
[134.143239] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1
[134.143273] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2
[134.143308] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1
[134.143346] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2
[134.143381] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1
[134.143416] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2
[134.143451] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1
[134.143485] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2
[134.143520] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1
[134.143555] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2
[134.143589] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1
[134.143624] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2
[134.143659] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1
[134.143693] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2
[134.143728] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1
[134.143763] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2
[134.143797] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1
[134.143832] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2
[134.143867] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1
[134.143901] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2
[134.143936] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1
[134.143971] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064efc:DDI_BUF_TRANS_C_S7T2
[134.144005] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1
[134.144040] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2
[134.144075] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1
[134.144109] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2
[134.144144] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0
[134.144160] HW.GFX.GMA.Registers.Read: 0x08800000 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0
[134.144194] HW.GFX.GMA.Registers.Write: 0x0036db00 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0
[134.144229] HW.GFX.GMA.Power_And_Clocks_Haswell.PSR_Off
[134.144243] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_EDP
[134.144259] HW.GFX.GMA.Registers.Read: 0x00100001 <- 0x0006f800:SRD_CTL_EDP
[134.144293] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_A
[134.144309] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00060800:SRD_CTL_A
[134.144345] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_B
[134.144360] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00061800:SRD_CTL_B
[134.144395] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_C
[134.144410] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00062800:SRD_CTL_C
[134.144445] HW.GFX.GMA.Panel.Backlight_Off
[134.144459] HW.GFX.GMA.Registers.Unset_Mask: 0x00000004 !S PCH_PP_CONTROL
[134.144490] HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c7204:PCH_PP_CONTROL
[134.144525] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
[134.144566] HW.GFX.GMA.Panel.Off
[134.144586] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[134.144621] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL
[134.144652] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
[134.144686] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL
[134.144734] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[134.144769] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x38000000 & 0x000c7200:PCH_PP_STATUS
[135.197940] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7200:PCH_PP_STATUS
[135.198003] HW.GFX.GMA.Pipe_Setup.All_Off
[135.198118] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
[135.198144] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL
[135.198178] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
[135.198212] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
[135.198246] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000700a0:CUR_FBC_CTL_A
[135.198280] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPACNTR
[135.198304] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070280:SPACNTR
[135.198338] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070280:SPACNTR
[135.198372] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007017c:CUR_BUF_CFG_A
[135.198408] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070140:CUR_WM_A_0
[135.198441] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070144:CUR_WM_A_1
[135.198475] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070148:CUR_WM_A_2
[135.198509] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007014c:CUR_WM_A_3
[135.198542] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070150:CUR_WM_A_4
[135.198576] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070154:CUR_WM_A_5
[135.198610] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070158:CUR_WM_A_6
[135.198644] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007015c:CUR_WM_A_7
[135.198677] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007027c:PLANE_BUF_CFG_1_A
[135.198711] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070240:PLANE_WM_1_A_0
[135.198745] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070244:PLANE_WM_1_A_1
[135.198778] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070248:PLANE_WM_1_A_2
[135.198812] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007024c:PLANE_WM_1_A_3
[135.198846] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070250:PLANE_WM_1_A_4
[135.198879] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070254:PLANE_WM_1_A_5
[135.198913] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070258:PLANE_WM_1_A_6
[135.198947] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007025c:PLANE_WM_1_A_7
[135.198981] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045270:WM_LINETIME_A
[135.199015] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPACNTR
[135.199039] HW.GFX.GMA.Registers.Read: 0xc4842000 <- 0x00070180:DSPACNTR
[135.199073] HW.GFX.GMA.Registers.Write: 0x44842000 -> 0x00070180:DSPACNTR
[135.199107] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF
[135.199141] HW.GFX.GMA.Registers.Read: 0x82010002 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL
[135.199175] HW.GFX.GMA.Registers.Is_Set_Mask: PIPE_EDP_CONF
[135.199190] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x0007f008:PIPE_EDP_CONF
[135.199223] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PIPE_EDP_CONF
[135.199248] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x0007f008:PIPE_EDP_CONF
[135.199281] HW.GFX.GMA.Registers.Write: 0x40000000 -> 0x0007f008:PIPE_EDP_CONF
[135.199315] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x0007f008:PIPE_EDP_CONF
[135.205269] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0006f400:PIPE_EDP_DDI_FUNC_CTL
[135.205705] HW.GFX.GMA.Registers.Is_Set_Mask: PIPEACONF
[135.205721] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070008:PIPEACONF
[135.205754] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00070008:PIPEACONF
[135.205798] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00060400:PIPEA_DDI_FUNC_CTL
[135.206239] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A
[135.206264] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A
[135.206297] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A
[135.206331] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A
[135.206775] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A
[135.206800] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A
[135.206834] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A
[135.206867] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A
[135.207309] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046140:TRANSA_CLK_SEL
[135.207343] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071080:CUR_CTL_B
[135.207377] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000710a0:CUR_FBC_CTL_B
[135.207844] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPBCNTR
[135.207869] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071280:SPBCNTR
[135.207902] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071280:SPBCNTR
[135.207936] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007117c:CUR_BUF_CFG_B
[135.208379] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071140:CUR_WM_B_0
[135.208415] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071144:CUR_WM_B_1
[135.208449] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071148:CUR_WM_B_2
[135.208914] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007114c:CUR_WM_B_3
[135.208948] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071150:CUR_WM_B_4
[135.208982] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071154:CUR_WM_B_5
[135.209450] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071158:CUR_WM_B_6
[135.209484] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007115c:CUR_WM_B_7
[135.209518] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007127c:PLANE_BUF_CFG_1_B
[135.209984] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071240:PLANE_WM_1_B_0
[135.210018] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071244:PLANE_WM_1_B_1
[135.210052] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071248:PLANE_WM_1_B_2
[135.210520] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007124c:PLANE_WM_1_B_3
[135.210554] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071250:PLANE_WM_1_B_4
[135.210588] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071254:PLANE_WM_1_B_5
[135.211054] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071258:PLANE_WM_1_B_6
[135.211088] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007125c:PLANE_WM_1_B_7
[135.211122] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045274:WM_LINETIME_B
[135.211590] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPBCNTR
[135.211615] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071180:DSPBCNTR
[135.211649] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071180:DSPBCNTR
[135.211682] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007119c:DSPBSURF
[135.212124] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL
[135.212158] HW.GFX.GMA.Registers.Is_Set_Mask: PIPEBCONF
[135.212173] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071008:PIPEBCONF
[135.212207] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00071008:PIPEBCONF
[135.212661] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00061400:PIPEB_DDI_FUNC_CTL
[135.212695] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_B
[135.212720] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068980:PS_CTRL_1_B
[135.212753] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068980:PS_CTRL_1_B
[135.213194] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068974:PS_WIN_SZ_1_B
[135.213228] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_B
[135.213252] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068a80:PS_CTRL_2_B
[135.213286] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068a80:PS_CTRL_2_B
[135.213730] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068a74:PS_WIN_SZ_2_B
[135.213764] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046144:TRANSB_CLK_SEL
[135.213798] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072080:CUR_CTL_C
[135.214264] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000720a0:CUR_FBC_CTL_C
[135.214299] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPCCNTR
[135.214353] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072280:SPCCNTR
[135.214393] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072280:SPCCNTR
[135.214817] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007217c:CUR_BUF_CFG_C
[135.214886] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072140:CUR_WM_C_0
[135.215350] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072144:CUR_WM_C_1
[135.215425] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072148:CUR_WM_C_2
[135.215869] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007214c:CUR_WM_C_3
[135.215903] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072150:CUR_WM_C_4
[135.215937] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072154:CUR_WM_C_5
[135.215970] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072158:CUR_WM_C_6
[135.216406] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007215c:CUR_WM_C_7
[135.216440] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007227c:PLANE_BUF_CFG_1_C
[135.216473] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072240:PLANE_WM_1_C_0
[135.216939] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072244:PLANE_WM_1_C_1
[135.216973] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072248:PLANE_WM_1_C_2
[135.217006] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007224c:PLANE_WM_1_C_3
[135.217040] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072250:PLANE_WM_1_C_4
[135.217475] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072254:PLANE_WM_1_C_5
[135.217509] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072258:PLANE_WM_1_C_6
[135.217543] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007225c:PLANE_WM_1_C_7
[135.218009] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045278:WM_LINETIME_C
[135.218043] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPCCNTR
[135.218067] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072180:DSPCCNTR
[135.218101] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072180:DSPCCNTR
[135.218545] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007219c:DSPCSURF
[135.218580] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL
[135.218613] HW.GFX.GMA.Registers.Is_Set_Mask: PIPECCONF
[135.218628] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072008:PIPECCONF
[135.218662] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00072008:PIPECCONF
[135.219079] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00062400:PIPEC_DDI_FUNC_CTL
[135.219113] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_C
[135.219138] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00069180:PS_CTRL_1_C
[135.219171] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00069180:PS_CTRL_1_C
[135.219615] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00069174:PS_WIN_SZ_1_C
[135.219649] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046148:TRANSC_CLK_SEL
[135.219683] HW.GFX.GMA.Connectors.DDI.Off
[135.219697] HW.GFX.GMA.Connectors.DDI.Digital_Off
[135.219711] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
[135.220149] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A
[135.220183] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DDI_BUF_CTL_A
[135.220207] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
[135.220241] HW.GFX.GMA.Registers.Write: 0x00000013 -> 0x00064000:DDI_BUF_CTL_A
[135.220685] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_A
[135.220710] HW.GFX.GMA.Registers.Read: 0x80000300 <- 0x00064040:DP_TP_CTL_A
[135.220744] HW.GFX.GMA.Registers.Write: 0x00000300 -> 0x00064040:DP_TP_CTL_A
[135.220777] HW.GFX.GMA.Registers.Wait: 0x00000080 <- 0x00000080 & 0x00064000:DDI_BUF_CTL_A
[135.221219] HW.GFX.GMA.Registers.Set_Mask: 0x00008000 .S DPLL_CTRL2
[135.221244] HW.GFX.GMA.Registers.Read: 0x00a00001 <- 0x0006c05c:DPLL_CTRL2
[135.221277] HW.GFX.GMA.Registers.Write: 0x00a08001 -> 0x0006c05c:DPLL_CTRL2
[135.221311] HW.GFX.GMA.Connectors.DDI.Off
[135.221325] HW.GFX.GMA.Connectors.DDI.Digital_Off
[135.221338] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_B
[135.221756] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064100:DDI_BUF_CTL_B
[135.221790] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_B
[135.221816] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064140:DP_TP_CTL_B
[135.221849] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064140:DP_TP_CTL_B
[135.222289] HW.GFX.GMA.Registers.Set_Mask: 0x00010000 .S DPLL_CTRL2
[135.222314] HW.GFX.GMA.Registers.Read: 0x00a08001 <- 0x0006c05c:DPLL_CTRL2
[135.222347] HW.GFX.GMA.Registers.Write: 0x00a18001 -> 0x0006c05c:DPLL_CTRL2
[135.222381] HW.GFX.GMA.Connectors.DDI.Off
[135.222396] HW.GFX.GMA.Connectors.DDI.Digital_Off
[135.222410] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_C
[135.222824] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064200:DDI_BUF_CTL_C
[135.222858] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_C
[135.222882] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064240:DP_TP_CTL_C
[135.222916] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064240:DP_TP_CTL_C
[135.223359] HW.GFX.GMA.Registers.Set_Mask: 0x00020000 .S DPLL_CTRL2
[135.223385] HW.GFX.GMA.Registers.Read: 0x00a18001 <- 0x0006c05c:DPLL_CTRL2
[135.223419] HW.GFX.GMA.Registers.Write: 0x00a38001 -> 0x0006c05c:DPLL_CTRL2
[135.223452] HW.GFX.GMA.PLLs.All_Off
[135.223466] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S LCPLL2_CTL
[135.223894] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00046014:LCPLL2_CTL
[135.223928] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046014:LCPLL2_CTL
[135.223961] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S WRPLL_CTL_2
[135.223986] HW.GFX.GMA.Registers.Read: 0x00202418 <- 0x00046060:WRPLL_CTL_2
[135.224019] HW.GFX.GMA.Registers.Write: 0x00202418 -> 0x00046060:WRPLL_CTL_2
[135.224430] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S WRPLL_CTL_1
[135.224455] HW.GFX.GMA.Registers.Read: 0x00202418 <- 0x00046040:WRPLL_CTL_1
[135.224488] HW.GFX.GMA.Registers.Write: 0x00202418 -> 0x00046040:WRPLL_CTL_1
[135.224522] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.224964] HW.GFX.GMA.Registers.Read: 0x30000007 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.224998] HW.GFX.GMA.Registers.Read: 0x1000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.225032] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.225501] HW.GFX.GMA.Registers.Read: 0x10000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.225535] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.225568] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.225602] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.226034] HW.GFX.GMA.Registers.Read: 0x30000007 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.226068] HW.GFX.GMA.Registers.Read: 0x1000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.226102] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.226135] HW.GFX.GMA.Registers.Read: 0x10000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.226571] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.226605] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.226638] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.226652] HW.GFX.GMA.Registers.Read: 0x30000007 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.227104] HW.GFX.GMA.Registers.Read: 0x1000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.227138] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.227172] HW.GFX.GMA.Registers.Read: 0x10000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.227641] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.227675] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.227708] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.227722] HW.GFX.GMA.Registers.Read: 0x30000007 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.228174] HW.GFX.GMA.Registers.Read: 0x1000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.228208] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.228242] HW.GFX.GMA.Registers.Read: 0x10000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.228275] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.228711] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.228744] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.228790] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER
[135.229244] HW.GFX.GMA.Registers.Read: 0x1000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.229278] HW.GFX.GMA.Registers.Write: 0x10000007 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.229312] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.229325] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.229772] HW.GFX.GMA.Registers.Read: 0x10000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.229806] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.229839] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.230296] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.230330] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.230363] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DBUF_CTL
[135.230389] HW.GFX.GMA.Registers.Read: 0xc000000a <- 0x00045008:DBUF_CTL
[135.230423] HW.GFX.GMA.Registers.Write: 0x4000000a -> 0x00045008:DBUF_CTL
[135.230822] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00045008:DBUF_CTL
[135.230866] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S LCPLL1_CTL
[135.230890] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL
[135.230924] HW.GFX.GMA.Registers.Write: 0x40000000 -> 0x00046010:LCPLL1_CTL
[135.231368] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL
[135.231425] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.232869] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.232923] HW.GFX.GMA.Registers.Read: 0x10000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.233386] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.233442] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.233910] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.233944] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.233978] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.234443] HW.GFX.GMA.Registers.Unset_Mask: 0x00000002 !S PWR_WELL_CTL_BIOS
[135.234468] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.234516] HW.GFX.GMA.Registers.Write: 0x30000001 -> 0x00045400:PWR_WELL_CTL_BIOS
[135.234949] HW.GFX.GMA.Registers.Unset_Mask: 0x00000002 !S PWR_WELL_CTL_DRIVER
[135.234973] HW.GFX.GMA.Registers.Read: 0x10000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.235007] HW.GFX.GMA.Registers.Write: 0x10000001 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.235041] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.235467] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.235501] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.235534] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.235981] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.236015] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.236049] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.236082] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.236499] HW.GFX.GMA.Registers.Unset_Mask: 0x20000000 !S PWR_WELL_CTL_BIOS
[135.236523] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.236557] HW.GFX.GMA.Registers.Write: 0x10000003 -> 0x00045400:PWR_WELL_CTL_BIOS
[135.236593] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT
[135.236618] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT
[135.236651] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT
[135.238394] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS
[135.238439] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.238453] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.238486] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.238909] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.238943] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.238977] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.239427] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.239460] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER
[135.239485] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.239518] HW.GFX.GMA.Registers.Write: 0x30000001 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.239941] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.239985] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS
[135.240029] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.240459] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.240493] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.240526] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.240973] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.241007] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.241041] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.241074] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER
[135.241491] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.241524] HW.GFX.GMA.Registers.Write: 0x10000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.241558] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.242015] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL
[135.242049] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL
[135.242073] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL
[135.242107] HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL
[135.242542] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL
[135.242587] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[135.242601] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[135.242645] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
[135.242678] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[135.242712] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[135.242746] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[135.242790] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
[135.242823] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[135.242837] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[135.242881] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
[135.242914] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[135.242948] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[135.242981] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[135.243025] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA
[135.243059] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[135.243072] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[135.243116] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
[135.243149] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[135.243183] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[135.243217] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[135.243260] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL
[135.243569] HW.GFX.GMA.Registers.Read: 0xc000000a <- 0x00045008:DBUF_CTL
[135.243603] HW.GFX.GMA.Registers.Write: 0xc000000a -> 0x00045008:DBUF_CTL
[135.243636] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL
[135.244093] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
[135.244122] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ
[135.244157] HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ
[135.300102] HW.GFX.GMA.Panel.On
[135.300139] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7200:PCH_PP_STATUS
[135.300174] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
[135.300212] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000c7204:PCH_PP_CONTROL
[135.300245] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
[135.300293] HW.GFX.GMA.Display_Probing.Read_EDID
[135.300307] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.300605] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.300640] HW.GFX.GMA.Registers.Read: 0x10000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.300674] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.301129] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.301163] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.301197] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.301231] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.301657] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER
[135.301681] HW.GFX.GMA.Registers.Read: 0x10000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.301715] HW.GFX.GMA.Registers.Write: 0x90000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.301749] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.301793] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS
[135.301837] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.301851] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.301885] HW.GFX.GMA.Registers.Read: 0xd0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.301918] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.301952] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.301986] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.302020] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.302054] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.302097] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER
[135.302122] HW.GFX.GMA.Registers.Read: 0xd0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.302155] HW.GFX.GMA.Registers.Write: 0xd0000023 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.302189] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.302237] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
[135.302253] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
[135.302287] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
[135.302320] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
[135.302335] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
[135.302369] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
[135.302404] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
[135.303065] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[135.303099] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
[135.303114] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[135.303148] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
[135.303181] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
[135.303196] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[135.303230] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
[135.303264] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
[135.303926] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[135.303960] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
[135.303974] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[135.304008] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
[135.304046] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
[135.304061] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[135.304095] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
[135.304129] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
[135.304791] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[135.304825] HW.GFX.GMA.Display_Probing.Read_EDID
[135.304839] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.304852] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.304886] HW.GFX.GMA.Registers.Read: 0xd0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.304920] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.304954] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.304987] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.305021] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.305055] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.305069] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.305103] HW.GFX.GMA.Registers.Read: 0xd0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.305136] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.305170] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.305204] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.305238] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.305271] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.305315] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER
[135.305339] HW.GFX.GMA.Registers.Read: 0xd0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.305373] HW.GFX.GMA.Registers.Write: 0xd00000b3 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.305408] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.305452] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
[135.305468] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
[135.305501] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
[135.305535] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
[135.305550] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
[135.305584] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
[135.305617] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
[135.306278] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[135.306312] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
[135.306327] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[135.306361] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
[135.306396] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
[135.306411] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[135.306444] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
[135.306478] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
[135.307140] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[135.307174] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
[135.307189] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[135.307222] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
[135.307256] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
[135.307271] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[135.307305] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
[135.307338] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
[135.308000] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[135.308035] HW.GFX.GMA.Display_Probing.Read_EDID
[135.308048] HW.GFX.GMA.I2C.I2C_Read
[135.308062] HW.GFX.GMA.I2C.Init_GMBUS
[135.308076] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
[135.308115] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[135.308149] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[135.308197] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[135.318256] HW.GFX.GMA.Registers.Wait: Timed Out!
[135.318286] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
[135.318320] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
[135.318368] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[135.318421] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[135.318469] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[135.318516] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[135.318663] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
[135.318696] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
[135.318754] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
[135.318801] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
[135.318849] HW.GFX.GMA.I2C.Release_GMBUS
[135.318862] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[135.318910] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
[135.318957] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
[135.318995] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[135.319029] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[135.319076] HW.GFX.GMA.Display_Probing.Read_EDID
[135.319090] HW.GFX.GMA.I2C.I2C_Read
[135.319104] HW.GFX.GMA.I2C.Init_GMBUS
[135.319117] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
[135.319155] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[135.319189] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[135.319236] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[135.319303] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
[135.319337] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0
[135.319384] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[135.319434] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[135.319481] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[135.319529] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[135.319675] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
[135.319708] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
[135.319766] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
[135.319813] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
[135.319861] HW.GFX.GMA.I2C.Release_GMBUS
[135.319874] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[135.319922] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
[135.319969] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
[135.320007] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[135.320041] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[135.320088] HW.GFX.GMA.Panel.Wait_On
[135.320116] HW.GFX.GMA.Registers.Read: 0x9000000a <- 0x000c7200:PCH_PP_STATUS
[135.320149] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x38000000 & 0x000c7200:PCH_PP_STATUS
[135.662018] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.662056] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
[135.662094] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
[135.662128] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
[135.662185] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.662218] HW.GFX.GMA.Display_Probing.Read_EDID
[135.662232] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.662246] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.662280] HW.GFX.GMA.Registers.Read: 0xd00000f3 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.662318] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.662352] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.662385] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.662422] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.662455] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.662499] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
[135.662524] HW.GFX.GMA.Registers.Read: 0xd00000f3 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.662558] HW.GFX.GMA.Registers.Write: 0xd00000fb -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.662592] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.662636] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.662651] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064010:DDI_AUX_CTL_A
[135.662685] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.662719] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.662734] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064010:DDI_AUX_CTL_A
[135.662768] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.662801] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.663432] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.663466] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.663481] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.663514] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.663548] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.663563] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.663596] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.663630] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.664261] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.664295] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.664310] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.664343] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.664377] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.664392] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.664427] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.664461] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.665091] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.665125] HW.GFX.GMA.Panel.Wait_On
[135.665153] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.665208] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x38000000 & 0x000c7200:PCH_PP_STATUS
[135.665324] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.665392] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
[135.665453] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
[135.665506] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
[135.665578] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.665612] HW.GFX.GMA.Display_Probing.Read_EDID
[135.665626] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.665639] HW.GFX.GMA.Registers.Read: 0x70000057 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.665673] HW.GFX.GMA.Registers.Read: 0xd00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.665707] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.665741] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.665775] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.665809] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.665843] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.665857] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.665891] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.665927] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.665942] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.665975] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.666009] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.666640] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.666674] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.666689] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.666722] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.666756] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.666771] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.666804] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.666838] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.667469] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.667503] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.667518] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.667551] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.667585] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.667600] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.667634] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.667667] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.668298] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.668332] HW.GFX.GMA.Panel.Wait_On
[135.668360] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.668393] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x38000000 & 0x000c7200:PCH_PP_STATUS
[135.668462] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.668496] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
[135.668534] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
[135.668567] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
[135.668624] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.668658] HW.GFX.GMA.Display_Probing.Read_EDID
[135.668671] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[135.668685] HW.GFX.GMA.Registers.Read: 0x70000057 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.668719] HW.GFX.GMA.Registers.Read: 0xd00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.668753] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.668787] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.668820] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.668854] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.668888] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.668903] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.668936] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.668970] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.668985] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.669019] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.669052] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.669683] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.669717] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.669732] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.669765] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.669799] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.669814] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.669848] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.669881] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.670512] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.670548] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[135.670563] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.670596] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[135.670630] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[135.670645] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.670678] HW.GFX.GMA.Registers.Write: 0xd6300000 -> 0x00064010:DDI_AUX_CTL_A
[135.670712] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[135.671343] HW.GFX.GMA.Registers.Read: 0x55400000 <- 0x00064010:DDI_AUX_CTL_A
[135.671377] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.671391] HW.GFX.GMA.Registers.Read: 0x70000057 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.671426] HW.GFX.GMA.Registers.Read: 0xd00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.671460] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.671494] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.671528] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.671562] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.671596] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.671609] HW.GFX.GMA.Registers.Read: 0x70000057 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.671643] HW.GFX.GMA.Registers.Read: 0xd00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.671677] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.671711] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.671745] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.671779] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.671813] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.671857] HW.GFX.GMA.Registers.Unset_Mask: 0x00000080 !S PWR_WELL_CTL_DRIVER
[135.671881] HW.GFX.GMA.Registers.Read: 0xd00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.671915] HW.GFX.GMA.Registers.Write: 0xd000007f -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.671949] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.671962] HW.GFX.GMA.Registers.Read: 0x70000017 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.671996] HW.GFX.GMA.Registers.Read: 0xd000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.672030] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.672064] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.672098] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.672132] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.672166] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.672210] HW.GFX.GMA.Registers.Unset_Mask: 0x00000020 !S PWR_WELL_CTL_DRIVER
[135.672234] HW.GFX.GMA.Registers.Read: 0xd000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.672268] HW.GFX.GMA.Registers.Write: 0xd000001f -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.672302] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.672315] HW.GFX.GMA.Registers.Read: 0x70000007 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.672349] HW.GFX.GMA.Registers.Read: 0xd000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.672383] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.672419] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.672452] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.672486] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.672520] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.672564] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER
[135.672588] HW.GFX.GMA.Registers.Read: 0xd000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.672622] HW.GFX.GMA.Registers.Write: 0xd0000007 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.672655] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[135.672669] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[135.672703] HW.GFX.GMA.Registers.Read: 0xd0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.672739] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[135.672773] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[135.672807] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[135.672841] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[135.672875] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[135.672919] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_DRIVER
[135.672944] HW.GFX.GMA.Registers.Read: 0xd0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[135.672977] HW.GFX.GMA.Registers.Write: 0x50000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
[135.673011] HW.GFX.GMA.Panel.Off
[135.673039] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.673073] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL
[135.673111] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
[135.673145] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL
[135.673202] HW.GFX.GMA.Registers.Read: 0x80000008 <- 0x000c7200:PCH_PP_STATUS
[135.673236] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x38000000 & 0x000c7200:PCH_PP_STATUS
[136.697926] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7200:PCH_PP_STATUS
[136.697981] CONFIG =>
[136.697995] (Primary =>
[136.698013] (Port => Disabled,
[136.698027] Framebuffer =>
[136.698041] (Width => 1,
[136.698057] Height => 1,
[136.698072] Start_X => 0,
[136.698088] Start_Y => 0,
[136.698104] Stride => 1,
[136.698120] V_Stride => 1,
[136.698135] Tiling => Linear ,
[136.698150] Rotation => No_Rotation,
[136.698165] Offset => 0x00000000,
[136.698188] BPC => 8),
[136.698204] Mode =>
[136.698217] (Dotclock => 19200000,
[136.698240] H_Visible => 1,
[136.698255] H_Sync_Begin => 1,
[136.698271] H_Sync_End => 1,
[136.698287] H_Total => 1,
[136.698302] V_Visible => 1,
[136.698318] V_Sync_Begin => 1,
[136.698334] V_Sync_End => 1,
[136.698349] V_Total => 1,
[136.698367] H_Sync_Active_High => False,
[136.698381] V_Sync_Active_High => False,
[136.698395] BPC => 5)),
[136.698411] Secondary =>
[136.698426] (Port => Disabled,
[136.698439] Framebuffer =>
[136.698456] (Width => 1,
[136.698472] Height => 1,
[136.698487] Start_X => 0,
[136.698503] Start_Y => 0,
[136.698519] Stride => 1,
[136.698534] V_Stride => 1,
[136.698550] Tiling => Linear ,
[136.698565] Rotation => No_Rotation,
[136.698579] Offset => 0x00000000,
[136.698602] BPC => 8),
[136.698618] Mode =>
[136.698632] (Dotclock => 19200000,
[136.698654] H_Visible => 1,
[136.698670] H_Sync_Begin => 1,
[136.698685] H_Sync_End => 1,
[136.698701] H_Total => 1,
[136.698717] V_Visible => 1,
[136.698732] V_Sync_Begin => 1,
[136.698748] V_Sync_End => 1,
[136.698764] V_Total => 1,
[136.698779] H_Sync_Active_High => False,
[136.698793] V_Sync_Active_High => False,
[136.698807] BPC => 5)),
[136.698822] Tertiary =>
[136.698837] (Port => Disabled,
[136.698851] Framebuffer =>
[136.698864] (Width => 1,
[136.698880] Height => 1,
[136.698896] Start_X => 0,
[136.698911] Start_Y => 0,
[136.698927] Stride => 1,
[136.698942] V_Stride => 1,
[136.698958] Tiling => Linear ,
[136.698973] Rotation => No_Rotation,
[136.698987] Offset => 0x00000000,
[136.699010] BPC => 8),
[136.699026] Mode =>
[136.699045] (Dotclock => 19200000,
[136.699068] H_Visible => 1,
[136.699083] H_Sync_Begin => 1,
[136.699099] H_Sync_End => 1,
[136.699114] H_Total => 1,
[136.699130] V_Visible => 1,
[136.699146] V_Sync_Begin => 1,
[136.699161] V_Sync_End => 1,
[136.699177] V_Total => 1,
[136.699192] H_Sync_Active_High => False,
[136.699206] V_Sync_Active_High => False,
[136.699220] BPC => 5)));
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