Get Intel 64/IA-32 architecture paging features by CPUID

paging_features_cpuid.c

/*
 * Get Intel 64/IA-32 architecture paging features by CPUID
 *
 * Ref: Intel® 64 and IA-32 architectures software developer's manual
 *      combined volumes 3A, 3B, 3C, and 3D: System programming guide,
 *      pp.Vol. 3A 4-5 (Section 4.1.4 Enumeration of Paging Features by CPUID
 */

#include <stdio.h>
#include <stdlib.h>

static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
								unsigned int *ecx, unsigned int *edx)
{
	asm volatile("cpuid"
				 : "=a" (*eax),
				   "=b" (*ebx),
				   "=c" (*ecx),
				   "=d" (*edx)
				 : "0" (*eax), "2" (*ecx));
}

int main() {
	unsigned int eax, ebx, ecx, edx;

	eax = 1;
	native_cpuid(&eax, &ebx, &ecx, &edx);
	printf("PSE: %d\n", (edx >> 3) & 0x1);
	printf("PAE: %d\n", (edx >> 6) & 0x1);
	printf("PGE: %d\n", (edx >> 13) & 0x1);
	printf("PAT: %d\n", (edx >> 16) & 0x1);
	printf("PSE-36: %d\n", (edx >> 17) & 0x1);
	printf("PCID: %d\n", (ecx >> 17) & 0x1);

	eax = 0x7;
	ecx = 0x0;
	native_cpuid(&eax, &ebx, &ecx, &edx);
	printf("SMEP: %d\n", (ebx >> 7) & 0x1);
	printf("SMAP: %d\n", (ebx >> 20) & 0x1);
	printf("PKU: %d\n", (ecx >> 3) & 0x1);

	eax = 0x80000001;
	native_cpuid(&eax, &ebx, &ecx, &edx);
	printf("NX: %d\n", (edx >> 20) & 0x1);
	printf("Page1GB: %d\n", (edx >> 26) & 0x1);
	printf("LME: %d\n", (edx >> 29) & 0x1);

	eax = 0x80000008;
	native_cpuid(&eax, &ebx, &ecx, &edx);
	printf("Physical-address width: %d\n", eax & 0xFF);
	printf("Linear-address width: %d\n", (eax >> 8) & 0xFF);
}