Display bridge part of MNT Reform 2 DTS

mntreform2-dts-displaybridges.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2018 Boundary Devices
 * Copyright 2019-2020 MNT Research GmbH
 */

/dts-v1/;

#include "dt-bindings/input/input.h"
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/usb/pd.h"
#include "imx8mq.dtsi"

/ {
	model = "MNT Reform 2";
	compatible = "mnt,reform2", "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq";
	
	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm2 0 10000>;
		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		brightness-levels = <0 32 64 128 160 200 255>;
		default-brightness-level = <6>;
		status = "okay";
	};

	panel: panel {
		compatible = "innolux,n125hce-gn1", "simple-panel";
		//backlight = <&backlight>;
		status = "okay";
		no-hpd;
		power = <&reg_vref_3v3>;

		port@0 {
			panel_in: endpoint {
				remote-endpoint = <&edp_bridge_out>;
			};
		};
	};
};

&dcss {
	status = "okay";

	clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
	<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
	<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
	<&clk IMX8MQ_CLK_DC_PIXEL>,
	<&clk IMX8MQ_CLK_DISP_DTRC>;
	clock-names = "apb", "axi", "rtrm", "pix", "dtrc";

	assigned-clocks =
	<&clk IMX8MQ_CLK_DC_PIXEL>,
	<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
	<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
	<&clk IMX8MQ_CLK_DISP_AXI>,
	<&clk IMX8MQ_CLK_DISP_RTRM>;

	assigned-clock-parents =
	<&clk IMX8MQ_VIDEO_PLL1_OUT>,
	<&clk IMX8MQ_VIDEO_PLL1>,
	<&clk IMX8MQ_CLK_25M>,
	<&clk IMX8MQ_SYS1_PLL_800M>,
	<&clk IMX8MQ_SYS1_PLL_800M>;
	assigned-clock-rates = <594000000>, <0>, <0>,
	<800000000>,
	<400000000>;

	port@0 {
		dcss_out: endpoint {
			remote-endpoint = <&mipi_dsi_in>;
		};
	};
};

&lcdif {
	status = "okay";
	max-res = <1920>, <1080>;
};

&dphy {
	status = "okay";
};

&mipi_dsi {
	status = "okay";
	
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			mipi_dsi_in: endpoint {
				remote-endpoint = <&dcss_out>;
			};
		};
		port@1 {
			reg = <1>;
			dsi_out: endpoint {
				remote-endpoint = <&edp_bridge_in>;
			};
		};
	};
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";
	
	edp_bridge: sn65dsi86@2c {
		compatible = "ti,sn65dsi86";
		reg = <0x2c>;
		status = "okay";
		enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				edp_bridge_in: endpoint {
					remote-endpoint = <&dsi_out>;
				};
			};

			port@1 {
				reg = <1>;

				edp_bridge_out: endpoint {
					remote-endpoint = <&panel_in>;
				};
			};
		};
	};
};