vga_zorro_sdram_first_working.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:49:19 03/22/2016 
// Design Name: 
// Module Name:    z2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module z2(

input CLK50,

// zorro
input znCFGIN,
//output znCFGOUT,
output znSLAVEN,
input znBERR,
input znRST,
input zE7M,
input zREAD,
input zDOE,

// address bus
input znAS,
input znUDS,
input znLDS,
input zA1,
input zA2,
input zA3,
input zA4,
input zA5,
input zA6,
input zA7,
input zA8,
input zA9,
input zA10,
input zA11,
input zA12,
input zA13,
input zA14,
input zA15,
input zA16,
input zA17,
input zA18,
input zA19,
input zA20,
input zA21,
input zA22,
input zA23,

// data bus
output zDIR,
inout zD0,
inout zD1,
inout zD2,
inout zD3,
inout zD4,
inout zD5,
inout zD6,
inout zD7,
inout zD8,
inout zD9,
inout zD10,
inout zD11,
inout zD12,
inout zD13,
inout zD14,
inout zD15,

// vga debug out
output vgaR,
output vgaG,
output vgaB,
output vgaVSync,
output vgaHSync,

// leds
output reg [7:0] LEDS,

// SDRAM
output SDRAM_CLK,  
output SDRAM_CKE,  
output SDRAM_nCS,   
output SDRAM_nRAS,  
output SDRAM_nCAS,
output SDRAM_nWE,   
output [1:0]  SDRAM_DQM,  
output [12:0] A, 
output [1:0]  SDRAM_BA,
inout  [15:0] D
);

clk_wiz_v3_6 DCM(
  .CLK_IN1(CLK50),
  .CLK_OUT100(z_sample_clk), 
  .CLK_OUT25(vga_clk)
);

wire sdram_reset;
reg  ram_enable;
reg  [20:0] ram_addr;
wire [31:0] ram_data_out;
wire data_out_ready;
reg  [31:0] ram_data_in;
reg  ram_write;
reg  [3:0]  ram_byte_enable;
reg  [15:0] ram_data_buffer [639:0]; // 640x16bit packed as 320x32bit
reg  [22:0] fetch_x;
reg  fetching;


// SDRAM
SDRAM_Controller_v sdram(
  .clk(z_sample_clk),   
  .reset(sdram_reset),
  // command and write port
  .cmd_ready(cmd_ready), 
  .cmd_enable(ram_enable), 
  .cmd_wr(ram_write), 
  .cmd_byte_enable(ram_byte_enable), 
  .cmd_address(ram_addr), 
  .cmd_data_in(ram_data_in),
  // Read data port
  .data_out(ram_data_out),
  .data_out_ready(data_out_ready),

  // signals
  .SDRAM_CLK(SDRAM_CLK),  
  .SDRAM_CKE(SDRAM_CKE),  
  .SDRAM_CS(SDRAM_nCS), 
  .SDRAM_RAS(SDRAM_nRAS),
  .SDRAM_CAS(SDRAM_nCAS),
  .SDRAM_WE(SDRAM_nWE),   
  .SDRAM_DATA(D),
  .SDRAM_ADDR(A),
  .SDRAM_DQM(SDRAM_DQM),
  .SDRAM_BA(SDRAM_BA) 
);

assign sdram_reset = 0;

// vga registers
reg [9:0] counter_x;
reg [8:0] counter_y;
reg [11:0] counter_frame;
wire counter_xmaxed = (counter_x==767);
reg hs, vs;

reg cycle=0;

// recorder regs
//reg [10:0] cycle=0;
//reg [13:0] rt_cycle=0;

/*reg rec_e7m [0:639];
reg rec_as [0:639];
reg rec_read [0:639];
reg rec_uds [0:639];
reg rec_doe [0:639];
reg rec_addr1 [0:639];
reg rec_addr2 [0:639];
reg rec_addr3 [0:639];
reg rec_addr4 [0:639];
reg rec_addr5 [0:639];
reg rec_addr6 [0:639];
reg rec_addr7 [0:639];
reg rec_addr8 [0:639];
reg rec_addr9 [0:639];
reg rec_addr10 [0:639];
reg rec_addr11 [0:639];
reg rec_addr12 [0:639];
reg rec_addr13 [0:639];
reg rec_addr14 [0:639];
reg rec_addr15 [0:639];
reg rec_addr16 [0:639];
reg rec_addr17 [0:639];
reg rec_addr18 [0:639];
reg rec_addr19 [0:639];
reg rec_addr20 [0:639];
reg rec_addr21 [0:639];
reg rec_addr22 [0:639];
reg rec_addr23 [0:639];
reg rec_dataout [0:639];*/

//reg fb [0:256*128];

reg [23:0] zaddr;
reg [15:0] data;
reg [15:0] data_in;
reg dataout;

assign zDIR = ~dataout;
assign znSLAVEN = ~dataout;
assign zD0  = dataout?data[0]:1'bz;
assign zD1  = dataout?data[1]:1'bz;
assign zD2  = dataout?data[2]:1'bz;
assign zD3  = dataout?data[3]:1'bz;
assign zD4  = dataout?data[4]:1'bz;
assign zD5  = dataout?data[5]:1'bz;
assign zD6  = dataout?data[6]:1'bz;
assign zD7  = dataout?data[7]:1'bz;
assign zD8  = dataout?data[8]:1'bz;
assign zD9  = dataout?data[9]:1'bz;
assign zD10 = dataout?data[10]:1'bz;
assign zD11 = dataout?data[11]:1'bz;
assign zD12 = dataout?data[12]:1'bz;
assign zD13 = dataout?data[13]:1'bz;
assign zD14 = dataout?data[14]:1'bz;
assign zD15 = dataout?data[15]:1'bz;

reg [31:0] last_addr;
reg [15:0] write_data;
reg [22:0] write_x;

reg fb_write_ready;
reg fb_write_pending;

reg last_doe;

parameter max_fill = 32;

reg [23:0] writeq_addr [0:max_fill-1];
reg [15:0] writeq_data [0:max_fill-1];
reg [8:0] writeq_fill;
reg [8:0] writeq_drain;

always @(posedge z_sample_clk) begin

  /*rec_e7m[cycle]  <= zE7M;
  rec_as[cycle]   <= znAS;
  rec_read[cycle] <= zREAD;
  rec_uds[cycle]  <= znUDS;
  rec_doe[cycle]  <= zDOE;*/

  data_in[0] <= zD0;
  data_in[1] <= zD1;
  data_in[2] <= zD2;
  data_in[3] <= zD3;
  data_in[4] <= zD4;
  data_in[5] <= zD5;
  data_in[6] <= zD6;
  data_in[7] <= zD7;
  data_in[8] <= zD8;
  data_in[9] <= zD9;
  data_in[10] <= zD10;
  data_in[11] <= zD11;
  data_in[12] <= zD12;
  data_in[13] <= zD13;
  data_in[14] <= zD14;
  data_in[15] <= zD15;
  
  /*rec_addr23[cycle] <= zA23;
  rec_addr22[cycle] <= zA22;
  rec_addr21[cycle] <= zA21;
  rec_addr20[cycle] <= zA20;
  rec_addr19[cycle] <= zA19;
  rec_addr18[cycle] <= zA18;
  rec_addr17[cycle] <= zA17;
  rec_addr16[cycle] <= zA16;
  rec_addr15[cycle] <= zA15;
  rec_addr14[cycle] <= zA14;
  rec_addr13[cycle] <= zA13;
  rec_addr12[cycle] <= zA12;
  rec_addr11[cycle] <= zA11;
  rec_addr10[cycle] <= zA10;
  rec_addr9[cycle] <= zA9;
  rec_addr8[cycle] <= zA8;
  rec_addr7[cycle] <= zA7;
  rec_addr6[cycle] <= zA6;
  rec_addr5[cycle] <= zA5;
  rec_addr4[cycle] <= zA4;
  rec_addr3[cycle] <= zA3;
  rec_addr2[cycle] <= zA2;
  rec_addr1[cycle] <= zA1;*/
  
  /*rec_addr16[cycle] <= zD15;
  rec_addr15[cycle] <= zD14;
  rec_addr14[cycle] <= zD13;
  rec_addr13[cycle] <= zD12;
  rec_addr12[cycle] <= zD11;
  rec_addr11[cycle] <= zD10;
  rec_addr10[cycle] <= zD9;
  rec_addr9[cycle] <= zD8;
  rec_addr8[cycle] <= zD7;
  rec_addr7[cycle] <= zD6;
  rec_addr6[cycle] <= zD5;
  rec_addr5[cycle] <= zD4;
  rec_addr4[cycle] <= zD3;
  rec_addr3[cycle] <= zD2;
  rec_addr2[cycle] <= zD1;
  rec_addr1[cycle] <= zD0;*/
  
  zaddr[23] <= zA23;
  zaddr[22] <= zA22;
  zaddr[21] <= zA21;
  zaddr[20] <= zA20;
  zaddr[19] <= zA19;
  zaddr[18] <= zA18;
  zaddr[17] <= zA17;
  zaddr[16] <= zA16;
  zaddr[15] <= zA15;
  zaddr[14] <= zA14;
  zaddr[13] <= zA13;
  zaddr[12] <= zA12;
  zaddr[11] <= zA11;
  zaddr[10] <= zA10;
  zaddr[9] <= zA9;
  zaddr[8] <= zA8;
  zaddr[7] <= zA7;
  zaddr[6] <= zA6;
  zaddr[5] <= zA5;
  zaddr[4] <= zA4;
  zaddr[3] <= zA3;
  zaddr[2] <= zA2;
  zaddr[1] <= zA1;
  zaddr[0] <= 0;
  
  data <= (writeq_fill<max_fill)?'h0000:'hf57f;
  dataout <= ((zaddr=='he80000) && zDOE==1 && zREAD);
  
  ram_byte_enable <= 'b1111;
  ram_enable <= 1;

  /*
  if (!zREAD && zDOE && zaddr>='h200000 && zaddr<'h296000 && !fetching) begin
    if (cmd_ready) begin
      ram_data_in <= data_in|'h00000000;
      ram_addr <= ((zaddr&'hfffff));
      ram_write <= 1;
    end
    // TODO else put in write queue
  end
  */
  
  if (!zREAD && zDOE && zaddr>='h200000 && zaddr<'h296000) begin
    writeq_addr[writeq_fill] <= zaddr;
    writeq_data[writeq_fill] <= data_in;
    writeq_fill <= writeq_fill+1;
    
    last_addr <= zaddr;
  end
  
  if (counter_x == 0) begin
    fetch_x <= 0;
    fetching <= 1;
    ram_write <= 0;
    ram_addr  <= ((counter_y << 9));
    fb_write_ready <= 0;
    fb_write_pending <= 0;
  end else begin
    if (fetching) begin
      // read window
      
      if (data_out_ready && cmd_ready) begin
        ram_write <= 0;
        ram_addr  <= ((counter_y * 640) | fetch_x)<<2;
        
        ram_data_buffer[fetch_x] <= ram_data_out;
        fetch_x <= fetch_x + 1;
        if (fetch_x > 639) begin
          fetching <= 0;
          fetch_x  <= 0;
          fb_write_ready <= 1;
        end
      end
    end else begin
      // write window
      if (!fetching && counter_x<760) begin
        if (cmd_ready==1) begin
          if (writeq_fill>writeq_drain) begin
            ram_addr    <= 20'b0|(((writeq_addr[writeq_drain])&'hffffe)<<1); // store 16 bit in 32 bit cell
            ram_data_in <= 32'b0|(writeq_data[writeq_drain]);
            ram_write <= 1;
            fb_write_pending <= 0;
            fb_write_ready <= 0;
            writeq_drain <= writeq_drain + 1;
          end
        end
      end
    end
  end
  
  if (writeq_drain >= max_fill) begin
    writeq_drain <= 0;
    writeq_fill <= 0;
  end
  //rec_dataout[cycle] <= dataout;
  
  LEDS <= counter_frame;

  /*if (rt_cycle<1200) rt_cycle <= rt_cycle+1;
  else if ((counter_x==0 && counter_y==0) && !zREAD) begin
    rt_cycle<=0;
    LEDS <= LEDS+1;
  end
  cycle <= rt_cycle>>1;
  */
end

assign vgaHSync = ~hs;
assign vgaVSync = ~vs;

reg[15:0] rgb = 'h0000;
assign vgaR = rgb[0];
assign vgaG = rgb[5];
assign vgaB = rgb[11];

parameter offset_x = 120;

always @(posedge vga_clk) begin
  if(counter_xmaxed)
	 begin
		counter_x <= 0;
		counter_y <= counter_y + 1;
	 end
  else
    counter_x <= counter_x + 1;

  if(counter_y==0 && counter_xmaxed) begin
    counter_frame <= counter_frame + 1;
  end

  hs <= (counter_x[9:4]==0);   // active for 16 clocks
  vs <= (counter_y==0);   // active for 768 clocks

  if (counter_x>=offset_x && counter_x < (640+offset_x)) begin
	  if ((hs | vs))
	    rgb <= 0;
	  else
      /*if (counter_y>=64 && counter_x>=64)
        rgb <= fb[(counter_x-64) + ((counter_y-64)<<9)]?'hffff:0;
        
      else
        rgb <= 0;*/
      
      if (counter_y>440) begin
        if (counter_x>100)
          rgb <= (counter_x-100 < writeq_fill)?'hffff:0;
        else rgb <= 0;
      end else if (counter_y>420) begin
        if (counter_x<210)
          rgb <= 0;
        else if (counter_x<220)
          rgb <= last_addr[23]?'hff:0;
        else if (counter_x<230)
          rgb <= last_addr[22]?'hff:0;
        else if (counter_x<240)
          rgb <= last_addr[21]?'hff:0;
        else if (counter_x<250)
          rgb <= last_addr[20]?'hff:0;
        else if (counter_x<260)
          rgb <= last_addr[19]?'hff:0;
        else if (counter_x<270)
          rgb <= last_addr[18]?'hff:0;
        else if (counter_x<280)
          rgb <= last_addr[17]?'hff:0;
        else if (counter_x<290)
          rgb <= last_addr[16]?'hff:0;
        else if (counter_x<300)
          rgb <= last_addr[15]?'hff:0;
        else if (counter_x<310)
          rgb <= last_addr[14]?'hff:0;
        else if (counter_x<320)
          rgb <= last_addr[13]?'hff:0;
        else if (counter_x<330)
          rgb <= last_addr[12]?'hff:0;
        else if (counter_x<340)
          rgb <= last_addr[11]?'hff:0;
        else if (counter_x<350)
          rgb <= last_addr[10]?'hff:0;
        else if (counter_x<360)
          rgb <= last_addr[9]?'hff:0;
        else if (counter_x<370)
          rgb <= last_addr[8]?'hff:0;
        else if (counter_x<380)
          rgb <= last_addr[7]?'hff:0;
        else if (counter_x<390)
          rgb <= last_addr[6]?'hff:0;
        else if (counter_x<400)
          rgb <= last_addr[5]?'hff:0;
        else if (counter_x<410)
          rgb <= last_addr[4]?'hff:0;
        else if (counter_x<420)
          rgb <= last_addr[3]?'hff:0;
        else if (counter_x<430)
          rgb <= last_addr[2]?'hff:0;
        else if (counter_x<440)
          rgb <= last_addr[1]?'hff:0;
        else if (counter_x<450)
          rgb <= last_addr[0]?'hff:0;
        else 
          rgb <= 0;
        end
      else 
        rgb <= ram_data_buffer[counter_x-offset_x];
      /*if (counter_y>434)
        rgb <= rec_dataout[counter_x]?'hff:0;
      else if (counter_y>426)
        rgb <= rec_addr1[counter_x]||counter_y==427?'hf0:0;
      else if (counter_y>418)
        rgb <= rec_addr2[counter_x]||counter_y==419?'hf0:0;
      else if (counter_y>410)
        rgb <= rec_addr3[counter_x]||counter_y==411?'hf0:0;
      else if (counter_y>402)
        rgb <= rec_addr4[counter_x]||counter_y==403?'hf0:0;
      else if (counter_y>394)
        rgb <= rec_addr5[counter_x]||counter_y==395?'hf0:0;
      else if (counter_y>386)
        rgb <= rec_addr6[counter_x]||counter_y==387?'hf0:0;
      else if (counter_y>378)
        rgb <= rec_addr7[counter_x]||counter_y==379?'hf0:0;
        
      else if (counter_y>370)
        rgb <= rec_addr8[counter_x]||counter_y==371?'h0f:0;
      else if (counter_y>362)
        rgb <= rec_addr9[counter_x]||counter_y==363?'hf0:0;
      else if (counter_y>354)
        rgb <= rec_addr10[counter_x]||counter_y==355?'hf0:0;
      else if (counter_y>346)
        rgb <= rec_addr11[counter_x]||counter_y==347?'hf0:0;
      else if (counter_y>338)
        rgb <= rec_addr12[counter_x]||counter_y==339?'hf0:0;
      else if (counter_y>330)
        rgb <= rec_addr13[counter_x]||counter_y==331?'hf0:0;
      else if (counter_y>322)
        rgb <= rec_addr14[counter_x]||counter_y==323?'hf0:0;
      else if (counter_y>314)
        rgb <= rec_addr15[counter_x]||counter_y==315?'hf0:0;
        
      else if (counter_y>306)
        rgb <= rec_addr16[counter_x]||counter_y==307?'h0f:0;
      else if (counter_y>298)
        rgb <= rec_addr17[counter_x]||counter_y==299?'hf0:0;
      else if (counter_y>290)
        rgb <= rec_addr18[counter_x]||counter_y==291?'hf0:0;
      else if (counter_y>282)
        rgb <= rec_addr19[counter_x]||counter_y==283?'hf0:0;
      else if (counter_y>274)
        rgb <= rec_addr20[counter_x]||counter_y==275?'hf0:0;
      else if (counter_y>266)
        rgb <= rec_addr21[counter_x]||counter_y==267?'hf0:0;
      else if (counter_y>258)
        rgb <= rec_addr22[counter_x]||counter_y==259?'hf0:0;
      else if (counter_y>250)
        rgb <= rec_addr23[counter_x]||counter_y==251?'hf0:0;
    
      else if (counter_y>220)
        rgb <= rec_e7m[counter_x]?'hff:0;
      else if (counter_y>200)
        rgb <= rec_as[counter_x]?'hff:0;
      else if (counter_y>150)
        rgb <= rec_uds[counter_x]?'hff:0;
      else if (counter_y>100)
        rgb <= rec_read[counter_x]?'hff:0;
      else if (counter_y>50)
        rgb <= rec_doe[counter_x]?'hff:0;
      else
        rgb <= 0;
      end*/
  end else
    rgb <= 0;
end

endmodule