fulladd.vhd
library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port( Cin, x, y : in std_logic;
s, Cout : out std_logic);
end fulladd;
architecture func of fulladd is
begin
s <= x xor y xor Cin;
Cout <= (x and y) or (x and Cin) or (y and Cin);
end func;hex.vhd
library ieee;
use ieee.std_logic_1164.all;
entity hex is
port( sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7 : in std_logic;
a0,b0,c0,d0,e0,f0,g0,a1,b1,c1,d1,e1,f1,g1 : out std_logic);
end hex;
architecture func of hex is
begin
a0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw1) AND sw0);
b0 <= ((NOT sw3) AND sw2 AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND sw0);
c0 <= ((NOT sw3) AND (NOT sw2) AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1);
d0 <= ((NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw2 AND sw1 AND sw0) OR (sw3 AND (NOT sw2) AND sw1 AND (NOT sw0));
e0 <= ((NOT sw3) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1)) OR ((NOT sw2) AND (NOT sw1) AND sw0);
f0 <= ((NOT sw3) AND (NOT sw2) AND sw0) OR ((NOT sw3) AND (NOT sw2) AND sw1) OR ((NOT sw3) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1));
g0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1)) OR ((NOT sw3) AND sw2 AND sw1 AND sw0);
a1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw5) AND sw4);
b1 <= ((NOT sw7) AND sw6 AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND sw4);
c1 <= ((NOT sw7) AND (NOT sw6) AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5);
d1 <= ((NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw6 AND sw5 AND sw4) OR (sw7 AND (NOT sw6) AND sw5 AND (NOT sw4));
e1 <= ((NOT sw7) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5)) OR ((NOT sw6) AND (NOT sw5) AND sw4);
f1 <= ((NOT sw7) AND (NOT sw6) AND sw4) OR ((NOT sw7) AND (NOT sw6) AND sw5) OR ((NOT sw7) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5));
g1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5)) OR ((NOT sw7) AND sw6 AND sw5 AND sw4);
end func;lab2_01.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.lab2_01_package.all;
entity lab2_01 is
port( x,y : in std_logic_vector(7 downto 0);
Cout : out std_logic;
seg : out std_logic_vector(13 downto 0));
end lab2_01;
architecture func of lab2_01 is
signal c : std_logic_vector(7 downto 0);
signal s : std_logic_vector(7 downto 0);
begin
c(0) <= '0';
stage0 : fulladd port map(c(0),x(0),y(0),s(0),c(1));
stage1 : fulladd port map(c(1),x(1),y(1),s(1),c(2));
stage2 : fulladd port map(c(2),x(2),y(2),s(2),c(3));
stage3 : fulladd port map(c(3),x(3),y(3),s(3),c(4));
stage4 : fulladd port map(c(4),x(4),y(4),s(4),c(5));
stage5 : fulladd port map(c(5),x(5),y(5),s(5),c(6));
stage6 : fulladd port map(c(6),x(6),y(6),s(6),c(7));
stage7 : fulladd port map(c(7),x(7),y(7),s(7),cout);
stage8 : hex port map(s(0),s(1),s(2),s(3),s(4),s(5),s(6),s(7),seg(6),seg(5),seg(4),seg(3),seg(2),seg(1),seg(0),seg(13),seg(12),seg(11),seg(10),seg(9),seg(8),seg(7));
end func;fullsub.vhd
library ieee;
use ieee.std_logic_1164.all;
entity fullsub is
port( Bin, x, y : in std_logic;
d, Bout : out std_logic);
end fullsub;
architecture func of fullsub is
begin
d <= x xor y xor Bin;
Bout <= (not x and y) or (not x and Bin) or (y and Bin);
end func;hex.vhd
library ieee;
use ieee.std_logic_1164.all;
entity hex is
port( sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7 : in std_logic;
a0,b0,c0,d0,e0,f0,g0,a1,b1,c1,d1,e1,f1,g1 : out std_logic);
end hex;
architecture func of hex is
begin
a0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw1) AND sw0);
b0 <= ((NOT sw3) AND sw2 AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND sw0);
c0 <= ((NOT sw3) AND (NOT sw2) AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1);
d0 <= ((NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw2 AND sw1 AND sw0) OR (sw3 AND (NOT sw2) AND sw1 AND (NOT sw0));
e0 <= ((NOT sw3) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1)) OR ((NOT sw2) AND (NOT sw1) AND sw0);
f0 <= ((NOT sw3) AND (NOT sw2) AND sw0) OR ((NOT sw3) AND (NOT sw2) AND sw1) OR ((NOT sw3) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1));
g0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1)) OR ((NOT sw3) AND sw2 AND sw1 AND sw0);
a1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw5) AND sw4);
b1 <= ((NOT sw7) AND sw6 AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND sw4);
c1 <= ((NOT sw7) AND (NOT sw6) AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5);
d1 <= ((NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw6 AND sw5 AND sw4) OR (sw7 AND (NOT sw6) AND sw5 AND (NOT sw4));
e1 <= ((NOT sw7) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5)) OR ((NOT sw6) AND (NOT sw5) AND sw4);
f1 <= ((NOT sw7) AND (NOT sw6) AND sw4) OR ((NOT sw7) AND (NOT sw6) AND sw5) OR ((NOT sw7) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5));
g1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5)) OR ((NOT sw7) AND sw6 AND sw5 AND sw4);
end func;lab2_02.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.lab2_02_package.all;
entity lab2_02 is
port( x,y : in std_logic_vector(7 downto 0);
Bout : out std_logic;
seg : out std_logic_vector(13 downto 0));
end lab2_02;
architecture func of lab2_02 is
signal b : std_logic_vector(7 downto 0);
signal d : std_logic_vector(7 downto 0);
begin
stage0 : fullsub port map(b(0),x(0),y(0),d(0),b(1));
stage1 : fullsub port map(b(1),x(1),y(1),d(1),b(2));
stage2 : fullsub port map(b(2),x(2),y(2),d(2),b(3));
stage3 : fullsub port map(b(3),x(3),y(3),d(3),b(4));
stage4 : fullsub port map(b(4),x(4),y(4),d(4),b(5));
stage5 : fullsub port map(b(5),x(5),y(5),d(5),b(6));
stage6 : fullsub port map(b(6),x(6),y(6),d(6),b(7));
stage7 : fullsub port map(b(7),x(7),y(7),d(7),Bout);
stage8 : hex port map(d(0),d(1),d(2),d(3),d(4),d(5),d(6),d(7),seg(6),seg(5),seg(4),seg(3),seg(2),seg(1),seg(0),seg(13),seg(12),seg(11),seg(10),seg(9),seg(8),seg(7));
end func;fulladd.vhd
library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port( Cin, x, y : in std_logic;
s, Cout : out std_logic);
end fulladd;
architecture func of fulladd is
begin
s <= x xor y xor Cin;
Cout <= (x and y) or (x and Cin) or (y and Cin);
end func;hex.vhd
library ieee;
use ieee.std_logic_1164.all;
entity hex is
port( sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7 : in std_logic;
a0,b0,c0,d0,e0,f0,g0,a1,b1,c1,d1,e1,f1,g1 : out std_logic);
end hex;
architecture func of hex is
begin
a0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw1) AND sw0);
b0 <= ((NOT sw3) AND sw2 AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND sw0);
c0 <= ((NOT sw3) AND (NOT sw2) AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1);
d0 <= ((NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw2 AND sw1 AND sw0) OR (sw3 AND (NOT sw2) AND sw1 AND (NOT sw0));
e0 <= ((NOT sw3) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1)) OR ((NOT sw2) AND (NOT sw1) AND sw0);
f0 <= ((NOT sw3) AND (NOT sw2) AND sw0) OR ((NOT sw3) AND (NOT sw2) AND sw1) OR ((NOT sw3) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1));
g0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1)) OR ((NOT sw3) AND sw2 AND sw1 AND sw0);
a1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw5) AND sw4);
b1 <= ((NOT sw7) AND sw6 AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND sw4);
c1 <= ((NOT sw7) AND (NOT sw6) AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5);
d1 <= ((NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw6 AND sw5 AND sw4) OR (sw7 AND (NOT sw6) AND sw5 AND (NOT sw4));
e1 <= ((NOT sw7) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5)) OR ((NOT sw6) AND (NOT sw5) AND sw4);
f1 <= ((NOT sw7) AND (NOT sw6) AND sw4) OR ((NOT sw7) AND (NOT sw6) AND sw5) OR ((NOT sw7) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5));
g1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5)) OR ((NOT sw7) AND sw6 AND sw5 AND sw4);
end func;lab3_01.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.lab3_01_package.all;
entity lab3_01 is
port( A0,B0 : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(13 downto 0));
end lab3_01;
architecture func of lab3_01 is
signal s0,s1 : std_logic_vector(3 downto 0);
signal c0,c1 : std_logic_vector(4 downto 0);
signal A13,A10 : std_logic;
signal Cout : std_logic;
signal bit1 : std_logic_vector(3 downto 0);
begin
c0(0) <= '0';
stage0 : fulladd port map(c0(0),A0(0),B0(0),s0(0),c0(1));
stage1 : fulladd port map(c0(1),A0(1),B0(1),s0(1),c0(2));
stage2 : fulladd port map(c0(2),A0(2),B0(2),s0(2),c0(3));
stage3 : fulladd port map(c0(3),A0(3),B0(3),s0(3),c0(4));
Cout <= c0(4) or (s0(3) and s0(1)) or (s0(3) and s0(2));
c1(0) <= '0';
A13 <= '0';
A10 <= '0';
bit1(2) <= '0';
bit1(1) <= '0';
bit1(0) <= '0';
stage4 : fulladd port map(c1(0),A13,s0(0),s1(0),c1(1));
stage5 : fulladd port map(c1(1),Cout,s0(1),s1(1),c1(2));
stage6 : fulladd port map(c1(2),Cout,s0(2),s1(2),c1(3));
stage7 : fulladd port map(c1(3),A10,s0(3),s1(3),c1(4));
stage8 : hex port map(s1(0),s1(1),s1(2),s1(3),Cout,bit1(0),bit1(1),bit1(2),seg(6),seg(5),seg(4),seg(3),seg(2),seg(1),seg(0),seg(13),seg(12),seg(11),seg(10),seg(9),seg(8),seg(7));
end func;fulladd.vhd
library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port( Cin, x, y : in std_logic;
s, Cout : out std_logic);
end fulladd;
architecture func of fulladd is
begin
s <= x xor y xor Cin;
Cout <= (x and y) or (x and Cin) or (y and Cin);
end func;hex.vhd
library ieee;
use ieee.std_logic_1164.all;
entity hex is
port( sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7 : in std_logic;
a0,b0,c0,d0,e0,f0,g0,a1,b1,c1,d1,e1,f1,g1 : out std_logic);
end hex;
architecture func of hex is
begin
a0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw1) AND sw0);
b0 <= ((NOT sw3) AND sw2 AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND sw0);
c0 <= ((NOT sw3) AND (NOT sw2) AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1);
d0 <= ((NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw2 AND sw1 AND sw0) OR (sw3 AND (NOT sw2) AND sw1 AND (NOT sw0));
e0 <= ((NOT sw3) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1)) OR ((NOT sw2) AND (NOT sw1) AND sw0);
f0 <= ((NOT sw3) AND (NOT sw2) AND sw0) OR ((NOT sw3) AND (NOT sw2) AND sw1) OR ((NOT sw3) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1));
g0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1)) OR ((NOT sw3) AND sw2 AND sw1 AND sw0);
a1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw5) AND sw4);
b1 <= ((NOT sw7) AND sw6 AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND sw4);
c1 <= ((NOT sw7) AND (NOT sw6) AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5);
d1 <= ((NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw6 AND sw5 AND sw4) OR (sw7 AND (NOT sw6) AND sw5 AND (NOT sw4));
e1 <= ((NOT sw7) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5)) OR ((NOT sw6) AND (NOT sw5) AND sw4);
f1 <= ((NOT sw7) AND (NOT sw6) AND sw4) OR ((NOT sw7) AND (NOT sw6) AND sw5) OR ((NOT sw7) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5));
g1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5)) OR ((NOT sw7) AND sw6 AND sw5 AND sw4);
end func;lab3_02.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.lab3_02_package.all;
entity lab3_02 is
port( A0,B0 : in std_logic_vector(7 downto 0);
seg : out std_logic_vector(13 downto 0));
end lab3_02;
architecture func of lab3_02 is
signal s0,s1,s2,s3 : std_logic_vector(3 downto 0);
signal c0,c1,C2,c3 : std_logic_vector(4 downto 0);
signal A13,A10,A33,A30 : std_logic;
signal Cout0,Cout1 : std_logic;
begin
c0(0) <= '0';
stage0 : fulladd port map(c0(0),A0(0),B0(0),s0(0),c0(1));
stage1 : fulladd port map(c0(1),A0(1),B0(1),s0(1),c0(2));
stage2 : fulladd port map(c0(2),A0(2),B0(2),s0(2),c0(3));
stage3 : fulladd port map(c0(3),A0(3),B0(3),s0(3),c0(4));
Cout0 <= c0(4) or (s0(3) and s0(1)) or (s0(3) and s0(2));
c1(0) <= '0';
A13 <= '0';
A10 <= '0';
stage4 : fulladd port map(c1(0),A10,s0(0),s1(0),c1(1));
stage5 : fulladd port map(c1(1),Cout0,s0(1),s1(1),c1(2));
stage6 : fulladd port map(c1(2),Cout0,s0(2),s1(2),c1(3));
stage7 : fulladd port map(c1(3),A13,s0(3),s1(3),c1(4));
c2(0) <= Cout0;
stage8 : fulladd port map(c2(0),A0(4),B0(4),s2(0),c2(1));
stage9 : fulladd port map(c2(1),A0(5),B0(5),s2(1),c2(2));
stage10 : fulladd port map(c2(2),A0(6),B0(6),s2(2),c2(3));
stage11 : fulladd port map(c2(3),A0(7),B0(7),s2(3),c2(4));
Cout1 <= c2(4) or (s2(3) and s2(1)) or (s2(3) and s2(2));
c3(0) <= '0';
A33 <= '0';
A30 <= '0';
stage12 : fulladd port map(c3(0),A30,s2(0),s3(0),c3(1));
stage13 : fulladd port map(c3(1),Cout1,s2(1),s3(1),c3(2));
stage14 : fulladd port map(c3(2),Cout1,s2(2),s3(2),c3(3));
stage15 : fulladd port map(c3(3),A33,s2(3),s3(3),c3(4));
stage16 : hex port map(s1(0),s1(1),s1(2),s1(3),s3(0),s3(1),s3(2),s3(3),seg(6),seg(5),seg(4),seg(3),seg(2),seg(1),seg(0),seg(13),seg(12),seg(11),seg(10),seg(9),seg(8),seg(7));
end func;alu.vhd
library ieee;
use ieee.std_logic_1164.all;
entity alu is
port( Cin, A, B, less : in std_logic;
Ctrol : in std_logic_vector(3 downto 0);
Result : out std_logic;
Cout, set : buffer std_logic);
end alu;
architecture func of alu is
signal at, bt : std_logic;
begin
set <= at xor bt xor Cin;
with Ctrol(3) select
at <= a when '0',
not a when '1';
with Ctrol(2) select
bt <= b when '0',
not b when '1';
with Ctrol(1 downto 0) select
Result <= at and bt when "00",
at or bt when "01",
set when "10",
less when "11";
Cout <= (at and bt) or (at and Cin) or (bt and Cin);
end func;hex.vhd
library ieee;
use ieee.std_logic_1164.all;
entity hex is
port( sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7 : in std_logic;
a0,b0,c0,d0,e0,f0,g0,a1,b1,c1,d1,e1,f1,g1 : out std_logic);
end hex;
architecture func of hex is
begin
a0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw1) AND sw0);
b0 <= ((NOT sw3) AND sw2 AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND (NOT sw2) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1 AND sw0);
c0 <= ((NOT sw3) AND (NOT sw2) AND sw1 AND (NOT sw0)) OR (sw3 AND sw2 AND (NOT sw0)) OR (sw3 AND sw2 AND sw1);
d0 <= ((NOT sw2) AND (NOT sw1) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1) AND (NOT sw0)) OR (sw2 AND sw1 AND sw0) OR (sw3 AND (NOT sw2) AND sw1 AND (NOT sw0));
e0 <= ((NOT sw3) AND sw0) OR ((NOT sw3) AND sw2 AND (NOT sw1)) OR ((NOT sw2) AND (NOT sw1) AND sw0);
f0 <= ((NOT sw3) AND (NOT sw2) AND sw0) OR ((NOT sw3) AND (NOT sw2) AND sw1) OR ((NOT sw3) AND sw1 AND sw0) OR (sw3 AND sw2 AND (NOT sw1));
g0 <= ((NOT sw3) AND (NOT sw2) AND (NOT sw1)) OR ((NOT sw3) AND sw2 AND sw1 AND sw0);
a1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw5) AND sw4);
b1 <= ((NOT sw7) AND sw6 AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND (NOT sw6) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5 AND sw4);
c1 <= ((NOT sw7) AND (NOT sw6) AND sw5 AND (NOT sw4)) OR (sw7 AND sw6 AND (NOT sw4)) OR (sw7 AND sw6 AND sw5);
d1 <= ((NOT sw6) AND (NOT sw5) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5) AND (NOT sw4)) OR (sw6 AND sw5 AND sw4) OR (sw7 AND (NOT sw6) AND sw5 AND (NOT sw4));
e1 <= ((NOT sw7) AND sw4) OR ((NOT sw7) AND sw6 AND (NOT sw5)) OR ((NOT sw6) AND (NOT sw5) AND sw4);
f1 <= ((NOT sw7) AND (NOT sw6) AND sw4) OR ((NOT sw7) AND (NOT sw6) AND sw5) OR ((NOT sw7) AND sw5 AND sw4) OR (sw7 AND sw6 AND (NOT sw5));
g1 <= ((NOT sw7) AND (NOT sw6) AND (NOT sw5)) OR ((NOT sw7) AND sw6 AND sw5 AND sw4);
end func;lab4_01.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.lab4_01_package.all;
entity lab4_01 is
port( A, B : in std_logic_vector(6 downto 0);
Ctrol : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(13 downto 0));
end lab4_01;
architecture func of lab4_01 is
signal Result, cout, set : std_logic_vector(6 downto 0);
begin
G1:for i in 0 to 6 generate
G2:if i>0 generate
compute1:alu port map(cout(i-1), A(i), B(i), '0', Ctrol, Result(i), cout(i), set(i));
end generate;
G3:if i=0 generate
compute2:alu port map(Ctrol(2), A(0), B(0), set(6), Ctrol, Result(0), cout(0), set(i));
end generate;
end generate;
stage1:hex port map(Result(0), Result(1), Result(2), Result(3), Result(4), Result(5), Result(6), Cout(6),
seg(6), seg(5), seg(4), seg(3), seg(2), seg(1), seg(0), seg(13), seg(12), seg(11), seg(10), seg(9), seg(8), seg(7));
end func;lab5_01.vhd
library ieee;
use ieee.std_logic_1164.all;
entity lab5_01 is
generic (N : integer := 7);
port( clk : in std_logic;
clear : in std_logic;
load : in std_logic;
lr_sel : in std_logic;
di : in std_logic_vector( N downto 0);
sdi : in std_logic;
qo : buffer std_logic_vector( N downto 0));
end lab5_01;
architecture func of lab5_01 is
begin
process(clk)
begin
if rising_edge(clk) then
if clear='1' then
qo <= "00000000";
elsif load='1' then
qo <= di;
else
if lr_sel='0' then
for i in N downto 1 loop
qo(i) <= qo(i-1);
end loop;
qo(0) <= sdi;
else
for i in 1 to N-1 loop
qo(i) <= qo(i+1);
end loop;
qo(7) <= sdi;
end if;
end if;
end if;
end process;
end func;